TCC720
CLOCK GENERATOR
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
Preliminary Spec 0.51
7 - 8
EXTCLK Control Register (EXTCLKmode) 0x80000414
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DIVXT EX_PHASE[13:0]
DIVXT
[15:14]
EXTCLK Divisor Clock Select
0
use XIN pin as a divisor clock of EXTCLK generator
1
use PLL output as a divisor clock of EXTCLK generator
2, 3
use XTIN pin as a divisor clock of EXTCLK generator
EX_PHASE
[13:0]
EXTCLK Clock Frequency Select
e (!= 0)
f
EXTCLK
= f
DIV
* e / 2
14
0 f
EXTCLK
= f
DIV
*) The divisor clock is selected by DIVXT bit of EXTCLKmode. EXTCLK is also controlled by EXT bit of
CKCTRL register that can enable or disable EXTCLK. If this bit is set to high, EXTCLK is disabled and if it
is low, EXTCLK is enabled.
External clock is user-programmable clock that can be used various purposes, it is not used by
internal peripherals, and by setting GPIO registers, GPIO_B24 pin can output this clock to user
application board. Care must be taken not to use too high frequency that the GPIO_B24 pin
cannot cope with this signals, or the GPIO_B24 pin show no clock signal out.
Summary of Contents for TCC720
Page 1: ...USER S MANUAL TCC720 32 bit RISC Microprocessor For Digital Media Player Preliminary Rev 0 51...
Page 3: ...CHAPTER 1 INTRODUCTION...
Page 12: ...CHAPTER 2 ADDRESS REGISTER MAP...
Page 22: ...CHAPTER 3 DAI CDIF...
Page 33: ...CHAPTER 4 INTERRUPT CONTROLLER...
Page 38: ...CHAPTER 5 TIMER COUNTER...
Page 45: ...CHAPTER 6 GPIO PORT...
Page 53: ...CHAPTER 7 CLOCK GENERATOR...
Page 68: ...CHAPTER 8 USB CONTROLLER...
Page 82: ...CHAPTER 9 UART IrDA CONTROLLER...
Page 93: ...CHAPTER 10 GSIO PORT...
Page 99: ...CHAPTER 11 MISCELLANEOUS PERIPHERALS...
Page 106: ...CHAPTER 12 DMA CONTROLLER...
Page 115: ...CHAPTER 13 MEMORY CONTROLLER...
Page 130: ...CHAPTER 14 BOOTING PROCEDURE...
Page 140: ...CHAPTER 15 JTAG DEBUG INTERFACE...
Page 142: ...CHAPTER 16 PACKAGE DEMENSION...