TeleChips TCC720, User Manual, Page: 58 / 143

TCC720
CLOCK GENERATOR
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
Preliminary Spec 0.51
7 - 5
PLL Control Register (PLLmode) 0x80000404
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 XTE DIV1 S
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M
0 0 P
XTE
[19]
XTIN mode select
0 XTIN is disabled when power down is requested.
1 XTIN is only controlled by XTIN bit of CKCTRL register
DIV1
[18]
Divisor Clock1 Select
0 Use Oscillator as DIVCLK1
1 Use PLL output as DIVCLK1
S/M/P PLL Frequency Setting
S/M/P
f
PLL
= (M + 8) * f
Xin
/ ((P + 2) * 2
S
)
The TCC720 has one PLL for generating of internal main clock. This internal PLL can generate
the required frequency by setting internal register. The desired frequency can be acquired by
the following equation.
f
PLL
= (M + 8) * f
Xin
/ ((P + 2) * 2
S
)
Where, M, P, S can be set by PLLmode register. M has 8bit resolution, P has 6bit resolution,
and S has 2bit resolution.
PLL has standby mode for minimizing power consumption that can be controlled by PLL bit of
CKCTRL register.