TeleChips TCC720, User Manual

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TCC720
TIMER / COUNTER
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
Preliminary Spec 0.51
5 - 5
Timer/Counter Interrupt Request Register (TIREQ) 0x80000260
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 TWF TF5 TF4 TF3 TF2 TF1 TF0 0 TW
TI5 TI4 TI3 TI2 TI1 TI0
TWF Watchdog Timer Flag
1 Watchdog timer has reached to its reference value.
TFn Timer/Counter n Flag
1 Timer/counter n has been overflowed.
TWI Watchdog Timer Interrupt Request Flag
1 Watchdog timer has generated its interrupt.
TIn Timer/Counter n Interrupt Request Flag
1 Timer/counter n has generated its interrupt.
*) if a timer n has reached its reference value, the TFn is set. (bit n represents for Timer n). If its interrupt
request is enabled by set bit 3 of TCFGn register, the TIn is set. And if the TC bit of IEN register is set, the
timer interrupt is really generated, and this TIREQ register is used to determine which timer has requested
the interrupt. After checking these flags, user can clear these TFn, TIn field by writing “1” to corresponding
TIn bit field.