TeleChips TCC720, User Manual

Page: 123 / 143

TCC720
MEMORY CONTROLLER
32-bit RISC Microprocessor for Digital Media Player
Dec. 16. 2002
Preliminary Spec 0.51
13 - 8
JTEN
[5]
Type Master of Internal Memory Select
0 JTAG port is disabled
1
R/W
JTAG port is enabled
SDEN
[4]
Type Master of Internal Memory Select
0 SDRAM controller is disabled
1
R/W
SDRAM controller is enabled
SDS
[3]
Type SD_CLK output select
0 SDRAM Clock is out from SD_CLK pin
1
R/W
SD bit is out from SD_CLK pin
GPO
[1]
Type SD_CLK output
0 / 1 R/W When SDS bit is high, this bit is out through SD_CLK pin
IM
[2]
Type SD_CLK output select
0 Memory controller automatically into idle state, when there is no
memory request during 4 cycle of HCLK. If memory request occur,
memory controller can serve that request immediately.
1
R/W
Memory controller is always active regardless of request state,
unless power down or idle state begins.
RM
[0]
Type Remap Flag
0 The area 0 (0x00000000 ~ 0x0FFFFFFF) space is mapped to internal /
external boot ROM
1
R/W
The area 0 space is released from boot ROM
*) If external boot ROM is used, it is considered as default that it is attached to nCS3 chip select pin.
In initialization, RM flag direct that the lower address space is mapped to internal or external
boot PROM, as program running, the program contained in the internal or external boot ROM
must set the RM flag to 1. After this flag is set to 1, the lower address space is released from
boot PROM. This lower address space can be mapped to other memories including SDRAM or
Flash by changing the base address of that memories. The RM flag can be restored to 0 by
clearing bit [0] of 0xF0000008. The lower address space is remapped to boot ROM. Care must
be taken not to illegally change the RM flag.