Tektronix MTX100, User Manual

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Appendix A: Specifications
MTX100 MPEG Recorder & Player User Manual
AĆ3
Table AĆ2: Mainframe (Cont.)
Characteristics Description
PLL divide ratio
(Internal and external
reference, 27 MHz)
Output Clock = (X / (2Ă*ĂY * Z) ) * 27 MHz
512 t X t 131071
3400 t Y t 6000 (3400 is the best value.)
2 v Z v 65536
(External clock)
Parallel clock
(160 kHz v f v 25 MHz)
27 MHz-500 Hz v fref v 27 MHz+500 Hz
8 v Y v 16383 f
cmp
=Clock/(2*Y), 10kHz v f
cmp
v 40 kHz
512 v X v 131071 f
ref
(Typical 27 MHz)=f
cmp
*X/2
Serial clock
(1.28 MHz v f v 64 MHz)
8 v Y v 16383 f
cmp
=Clock/(16*Y), 10kHz v f
cmp
v 40 kHz
512 v X v 131071 f
ref
(Typical 27 MHz)=f
cmp
*X/2
P/N and Jitter (serial clock)
t -104 dBc/Hz at 21.455707 MHz +20 kHz (RBW=300 Hz)
DVBĆSPI interface
Connector type DĆsub, 25 pin
Data rate 1 Kbps to 200 Mbps
Pin assignments 1 DCLK
2 GND
3 to 10 DATA 7 to DATA 0
11 DVALID
12 PSYNC
13 Shield
14 DCLK
15 GND
16 to 23 DATA 7 to DATA 0
24 DVALID
25 PSYNC
Output
Output level, typical 330 mV to 550 mV (termination: internal 100 W . external 100 W ), bus LVDS with 50 W
termination
Offset 1.1 V to 1.5 V
Output resistance, typical 100 W , between differential outputs (output off)
Data delay, typical
±
5 ns from the falling edge of DCLK (See Figure AĆ1.)
Input
Input level, typical
u +100 mV, t -100 mV, (RI+)-(RI-) with 100 W termination
Input resistance, typical 100 W (between differential inputs)
Clock pulse width, typical T/2
±
T/10, T=1/f (f=byte clock frequency) (See Figure AĆ1.)
Data hold time, typical T/2
±
T/10, T=1/f (f=byte clock frequency, Data are latched on DCLK rising edge)
(See Figure AĆ1.)