Tektronix CMD 80, User Manual, Page: 374 / 672

Appendix D: Remote Control
D–18
CMD 80 Digital Radiocommunication Tester User Manual
A bit is set to 1 in the ESR in the case of certain events (for example: fault, ready
signal). Refer to Table D–8. These bits remain set until they are cleared by
reading the ESR (by the command *ESR?) or by the following conditions:
H
The commands *RST or *CLS
H
Switching the AC supply (note that the power-on bit is set in this case)
Using the ESE mask register, the user can select the bits in the ESR that also set
the sum bit ESB (bit 5 in the status byte) and trigger the service request. The
sum bit is therefore only set if at least one bit in the ESR and the corresponding
bit in the ESE are set to 1. The sum bit is automatically cleared again if the
previous condition is no longer fulfilled (for example, if the bits in the ESR have
been cleared by reading the ESR or if the ESE has been modified).
The ESE mask register is written by the command *ESE <value> (value is the
register contents in decimal form) and can be read again by the command *ESE?.
The value is set to 0 at AC power on if the power-on status clear flag is 1
(*PSC 1). The ESE mask register is not changed by other commands or interface
messages (DCL, SDC).
The bits listed in Table D–7 are used in the status byte (STB).
Table D–7: Bit allocation of status byte
Bit Number
*
Bus Line Description Meaning
2 DOI 3 ––– There is an entry in the error queue
3 DOI 4 ––– Sum bit of the Questionable status
4 DOI 5 MAV Message Available
Indicates that there is a message to be read in the
output buffer. The bit is 0 if the output buffer is
empty.
5 DOI 6 ESB Sum bit of the Event Status Register
6 DOI 7 RSQ Request Service
7 DOI 8 ––– Sum bit of the Operation status
*
Bits 0 and 1 are not used.
NOTE
. The status register bits are numbered from 0 to 7 in compliance with the
standard, but the bus data lines are designated DIO 1 to DIO 8.