Tektronix 7D14, Instruction Manual

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Circuit Description—7D14
After a LO DCU RESET input to the direct-clear input,
U733B 1- and 0-outputs are LO and HI respectively. The
J-input is HI (U733A is set by DCU RESET); the K-input,
connected to the 1 output, is LO. The next HI to LO
transition at the T (trigger) input sets the 1 and 0 outputs
of U733B to be HI and LO respectively. The J- and K-
inputs are now both HI. The next HI to LO transition at
the T-input will toggle U733B.
Triggered J-K flip-flop U735 generates the GATE signal
as determined by the inputs. The GATE is "on" when the
U735 1-output (pin 9) is HI and the O-output (pin 7) is LO.
U735 is triggered on the negative-going transition of the
Reference Frequency Gate stage (U731D) output applied
to the T-input. When triggered, the output changes states in
response to the levels set at the J- and K-inputs prior to the
trigger.
When the J- and K-inputs are set HI and LO respectively
by the U733B outputs, the next negative-going transition of
the Reference Frequency Gate stage output will trigger
U735 to set the 1-output HI to turn the GATE "on". When
the J- and K-inputs are set LO and HI respectively, the next
negative-going transition at the T input will set the 1 output
LO to turn the GATE "off".
A LO applied to the direct-set input over-rides the J-, K-,
and T-inputs to set the 1-output HI (GATE "on"). A LO
applied to the direct-clear input over-rides the J-, K-, and
T-inputs to set the 1-output LO (GATE "off").
A LO applied to the direct-set input from the Manual/
External Gate Input stage (U729A or P742) will turn the
GATE "on". A LO to the direct-clear input from the
Manual/External Gate Input stage (U708B) or from the
Reset Input stage (Q738) will turn the GATE "off".
The U735 1- and 0-outputs are connected to the bases of
Q751 and Q753 through R750 and R754 respectively.
Q751 and Q753 translate the logic levels at the U735 out­
puts to provide the GATE and GATE outputs to the
Channel A Signal Conditioning circuit through T755. Q751
and Q753 invert the U735 outputs so that the GATE out­
put is HI with respect to GATE when the GATE is "on".
The GATE and GATE signals are also connected to
Q763 and Q758 respectively. Q758 and Q763 invert the
Q751-Q753 outputs to provide logic levels corresponding to
the GATE "on" and "off" states to other Time Base and
Control circuit stages. When the Gate is "on", the collector
of Q758 provides a HI output to the Display Generator
(U729D), and to the Lamp Driver (Q776) to turn on the
GATE indicator light (DS80). When the GATE is "on", the
collector of Q763 is LO. When the GATE is turned off, the
LO
to HI transition at the collector of Q763 is coupled
through C765-R765 to momentarily turn on Q768. The
collector of Q768 goes LO to provide a LO CLEAR output.
Display Enable
The Display Enable stage consists of inverter transistor
U729C, inverted-input NOR gate U731B, and NAND gate
U731C. This stage produces the LO DISPLAY output when
a LO is applied to either input of U731B.
When the INTERNAL input is LO, and the Manual Gate
Storage switch is in the off position, the DISPLAY output
is held LO. When the INTERNAL input is HI, or the
Manual Gate Storage switch is in the on position, the out­
put is determined by the level applied to U731B-pin 5.
Quiescently, +5 volts applied to U731 B-pin 5 through R768
holds
pin 5 HI.
The Gate Generator CLEAR output (at the collector of
Q768) is connected directly to U731 B-pin 5. When CLEAR
goes LO, U731 B-pin 8 goes LO to provide the DISPLAY
output. The Reset Input stage RESET signal is connected
to the base of U729C through R772. When RESET is HI,
the collector of U729C is LO. This results in a LO DIS­
PLAY output.
Display Generator
The Display Generator provides a positive pulse output
to the DCU RESET Driver through R794. This pulse is
generated by relaxation oscillator Q791, a unijunction tran­
sistor. U729D acts as a three-input NOR gate to inhibit
Q791. A HI level is applied to the base of U729D through
CR786 when the DISPLAY TIME control is set to °° or
through R759 when the GATE is on to inhibit Q791. When
the DISPLAY TIME control is not set to °°, the Display
Generator is enabled when the GATE ends and U733A is
cleared (the 1-output is LO). The LO applied to the base of
U729D when all inputs are LO reverse biases U729D to
allow C788 to charge to a positive level sufficient to for­
ward bias Q791. DISPLAY TIME R70 adjusts the RC time­
constant of R70-R789-C788 to set the time required to
charge C788 to a level which will switch on Q791. When
C788 charges positive enough to forward bias Q791, it dis­
charges through Q791, R793, and L793 to generate a posi­
tive pulse output across L793.
DCU RESET Driver
T he DCU RESET Driver, Q796-Q798-U731 A, provides
the DCU RESET output to the First Decade Counter cir­
cuit, Counters and Readout Encoding circuit, and to several
stages within the Time Base and Control Circuit. The
positive-going pulse input from the Display Generator or a
HI level input from the Reset Input stage applied to the
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