Tektronix 7D14, Instruction Manual

Page: 32 / 133

Circuit Description—7D14
decimal input to a BCD output for the corresponding
Storage Register. The operation of each decade is similar.
The counting operation is performed on a HI to LO transi­
tion at the T (trigger) input, pin 8. The DCU RESET input
is connected to the direct-reset input (pin 13) of each
counter. When the DCU RESET input goes LO, the Decade
Counters are reset to the zero-count state. An input/output
table applicable to each decade is given in Fig. 3-10.
The HI to LO transition of the CARRY input triggers
the 101 Decade Counter U440. At the tenth CARRY input,
pin 12 of U440 goes from HI to LO to provide a trigger to
the 102 Decade Counter U442. The operation of the re­
mainder of the decades is similar. The tenth input to the
107 Decade Counter U452 triggers the counter from the
nine-count to the zero-count. The 23 output (pin 12) level
goes from HI to LO to provide the FULL COUNT output
to the Overflow Register (see Fig. 3-10).
Reset
INPUT OUTPUTS
TRIGGER
Pin 8
BCD
2°
Pin 5
21
Pin 9
22
Pin 2
23
Pin 12
0 LO LO LO LO
1
HI
LO LO LO
2
LO HI
LO LO
3 HI HI
LO LO
4 LO
LO
HI
LO
5 HI
LO
HI
LO
6 LO HI HI
LO
7 HI
HI HI LO
8 LO
LO LO HI
9 HI LO
LO HI
Fig. 3-10. Decade Counter input/output table.
Storage Registers
The eight IC Storage Registers store the corresponding
decade counter BCD output. The BCD input is applied to
the D (data) inputs at pins 4, 10, 3, and 11 (2°-21-22-23
bits respectively). The DISPLAŸ input is applied to the
data-strobe input at pin 1 of each Storage Register IC.
When the DISPLAY input goes LO, the logic levels at the D
inputs are transferred to the associated BCD bit output to
provide a BCD output to the Readout Encoding circuit.
Overflow Register
U508B is connected as an inverter. U508B inverts the HI
to LO FULL COUNT input to provide a positive-going out­
put to the T input of U510A. U510A is an edge-triggered,
D-type flip-flop with a direct-clear input. When U510A is
triggered, the HI at the D-input is transferred to the
1-output. A LO applied to the direct-clear input of U510A
clears U510A for a LO output. DCU RESET is applied to
the U510A direct-clear input. DISPLAY is applied to the
base of Q512 through R511. Q512 inverts its input to pro­
vide the DISPLAY output to U504B and U504C.
When the Decade Counters are counting, DCU RESET is
HI and DISPLAY is HI (for most modes of operation).
When the Decade Counters have reached a count of
9999999 9, the next count provides a HI to LO FULL
COUNT output to the input of U508B. U508B inverts the
transition to provide a positive-going trigger to U510A. This
triggers U510A to transfer the HI level at the D-input to the
1-output. When DISPLAY goes LO, Q512 provides a HI to
U504B and U504C. U504B then provides a LÖ to the
direct-clear input of U510B. This clears U510B for a LO
level OVERFLOW output.
When DCU RESET goes LO, U510A is cleared for a LO
1-output. This results in a HI U504B output. This HI
applied to pin 9-U504C, and the HI level DISPLAY applied
to pins 10 and 11 of U504C, results in a U504C LO output.
This LO applied to the direct-set input of U510B at pin 10
sets U510B for a HI output.
Multiplexers
The Multiplexers consist of eight IC's; U520, U524,
U528, U532, U536, U540, U544, and U548. Each multi­
plexer IC is addressed by a particular time-slot input to
provide the BCD data to encode the corresponding readout
display digit. Each IC contains four two-input NAND gates.
The inverted time-slot input is connected to one input of
each NAND gate. A BCD bit input is applied to the
remaining NAND gate input. The NAND gate outputs are
connected to common 2°-21-22-23 output lines to the
Readout Encoding circuit.
The Multiplexers invert the BCD outputs of the Storage
Registers to drive the LO-true inputs of the Readout
Encoding circuit. +5 volts is applied to each output line
through resistor R555, R556, R557,or R558. Quiescently,
this holds the output lines HI. When a HI level inverted
time-slot pulse addresses a Multiplexer, a HI input level will
result in a LO output; a LO input will result in no change or
a HI output. For example, the 10° Storage Register
2°-2*-2 2 -23 outputs for the decimal-digit three will be
HI-HI-LO-LO respectively. These input levels are applied to
Multiplexer U520 at pins 6-12-2-8 respectively. When U520
is addressed by inverted time-slot TS-10, the U520 outputs
will be 2° -LO, 21 -LO, 22 -HI, 23 -HI at pins 4-13-1-10
respectively.
Time-Slot Inverters
The Time-Slot Inverters invert the negative-going time­
slot pulses to provide a Hl-level pulse output for each input
pulse. Each inverter consists of a single-transistor section of
five-transistor arrays U531 or U541. Quiescently, each
transistor is forward biased to saturation to hold the collec­
tor level close to ground. The time-slot pulse is connected
to the inverter-transistor base through a zener diode to drop
the pulse voltage level about 12 volts. This ensures that the
— 15-volt time-slot input pulse almost reaches its negative
extremity before the associated inverter-transistor is reverse
biased. When the inverter transistor is reverse biased, the
3-12
@î