Circuit
Description—
7D14
BINARY
COUNT
CLOCK
INPUT
01
23456789
10
(A)
CLOCK
COUNT
A
OUTPUT
LEVEL
E
B
c
D
Oor 10
+
—
+
0
1
0
—
+
—
+
2
—
0
+
-
+
3
-
+
0
-
+
4
—
+
—
0
+
5
-
+
-
+
0
6
0
+
—
+
—
7
+
0
-
+
-
8
+
-
0
+
-
9
+
-
+
0
-
(B)
Fig. 3-7. (A) Clock count input vs. Quinary Driver Binary Count out
put.
(B)
Quinary Counter output voltage
levels after each clock
count.
sufficiently
negative
that the left transistors
continue to
conduct. The voltage
on the base of the right transistor in
multi E
is
at the 0
level,
and the LO Binary Count input
causes
multi E to change state.
The
change of state of multi E changes the voltage across
load
resistors A and E. The
output
voltage levels are now A,
0;
B, —
; C, +;
D, —;
and E, +. At the next Clock input (2),
the
Binary
Count input goes HI. This tends to forward bias
the left transistor
in each multi, but causes only multi A to
change state. The
left transistors of multis
B and
D are
already
forward
biased, and the right transistors of multis C
and
E
are sufficiently forward biased
to remain
conducting.
This
sequence
of operation continues for the remainder
of
the
Binary Count. The output voltage levels after each
Clock
input are
shown in Fig. 3-7(B). The multi which has
the
0-level
output changes state at the next Clock input,
and conditions
the next multi.
Resistor
networks connected between the
multivibrator
outputs compare
the output voltage
levels of the multis to
provide a HI
level
on
one of five output lines. The output
line
with the HI level indicates the quinary count to the
BCD Encoder.
The resistor network consists of five pairs of
resistors.
Each
pair of resistors compares the state of two
adjacent
multivibrators;
R370-R399 compares
A
and
E,
R367-R371 compares
A
and B,
R373-R379 compares
B
and
C, R381-R387
compares
C and D, and R389-R396
compares
D and E. The outputs to the BCD Encoder are
taken
from
the junction
of each resistor pair. The level of
an
output
line is HI only when the associated multivibrator
output levels are +
and 0
(or 0 and +); other combinations
result
in zero
or a LO output.
BCD
Encoder
BCD
Encoder
U420-U434 translates the Quinary
Counter outputs to encode the
21, 22, and 23 bits of the
BCD output (the 2°
bit is encoded directly from the Binary
Counter
output).
The five
Quinary Counter output lines are connected to
the
bases of
five-transistor 1C array U420. The transistor in
this
array
which
has the most positive base will conduct.
When
the base of U420 B, C, D, or E is HI, the corre
sponding
collector
goes
LO to provide an output to U434.
The collector
of
U420A is grounded. Thus, when
the base
of
U420A is
HI (0-1 count), U420 conducts, but no output
is
provided.
Three inverted-input OR gates within U434
provide
the 21
,22, and 23 bits of the BCD output from the
U420
outputs.
An input/output
table
for U420-U434
is
given
in Fig. 3-8.
Carry
Comparator
The
Carry
Comparator provides
the CARRY
output to
the second
decade counter (101 )
in the Counter and Read
out
Encoding
circuit.
The
CARRY
output is a HI to LO
level
transition
to indicate the tenth Clock input counted
by
the First Decade Counter circuit (see Fig. 3-5, Input/
output
table for the First Decade
Counter circuit).
Emitter-coupled
pair Q405-Q407 compares the voltage
levels
at the
bases of
Q392 and
Q402 to compare the out
put levels
of multivibrators D and E. The transistor with the
more
positive base
controls the conduction of Q405 or
Q407.
For Clock inputs five through nine, the more posi
tive
output level of multivibrator D will cause Q407 to
conduct and Q405 to
be cut off. As a result, the level at the
collector
of Q405 is HI. At the tenth Clock input, the
output level of multivibrator E
becomes more positive to
turn
on Q405. The collector of 0405
goes LO. The HI to
LO level
transition at the collector of
Q405
is applied to
emitter-follower
Q418
to provide
the CARRY output.
Fig.
3-8. BCD Encoder stage input/output table.
Input
Outputs
HI
Level
U'120
U434
Quinary
Counter
B
C
D
E
2
1
22
23
Output
Line
Pin 5
Pin 8 Pin 11 Pin 14 Pin 6
Pin 3
Pin 8
0-1
HI
HI
HI
HI
LO
LO
LO
2-3
HI
LO
HI
HI
HI
LO
LO
4-5
HI
HI
HI
LO
LO
HI
LO
6-7
LO
HI
HI
HI
HI
HI
LO
8-9
HI
HI
LO
HI
LO
LO
HI
3-10
Summary of Contents for 7D14
Page 4: ...7D14 ...
Page 11: ...Operating Instructions 7D14 Fig 2 1 7D14 front panel controls and connectors 2 2 ...
Page 33: ... 3 13 Fig 3 11 Logic diagram for Zero Cancel Logic stage Circuit Description 7D14 ...
Page 38: ...3 18 Fig 3 16 Time Base and Control circuit detailed block diagram Circuit Description 7D14 ...
Page 44: ...NOTES ...
Page 46: ...NJ Fig 4 1 Electrode configuration for semiconductors in this instrument I ...
Page 68: ...NOTES ...
Page 96: ... 7DI 4 DIGITAL COUNTER UNIT ...
Page 98: ...GRS 0371 BLOCK DIAGRAM ...
Page 99: ......
Page 103: ...0 0 I 200 mV 500 µs 0 001 200 mV 500 µs 0 001 MHz 00 mV E 00 µs 0 001 MHz ...
Page 106: ...1 ...
Page 110: ...A2 Logic Circuit Board Assembly jQ798i 798 jc743 CR744t uni R724 R742 JL744S FrR796 ...
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Page 114: ...P 0 A2 LOGIC BOARD ...
Page 121: ... A B D t F H J NPR Tj ZWX V A AC M AEA HUM qAZ DEF HJ N P R S T J V V7X y ABM APAI AA 7DI4 ...
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Page 130: ...4 7D14 DIGITAL COUNTER ...