Tektronix 7D14, Instruction Manual

Page: 27 / 133

Circuit Description—7D14
BINARY COUNTER
VOLTAGE
REGULATOR
10° BCD
TO 10°
STORAGE
REGISTER
Fig. 3-4. First Decade Counter circuit detailed block diagram.
Fig. 3-5. Input/output table for First Decade Counter circuit.
Input
OUTPUTS
Clock
Count
Binary-Cod ed-Decimal
CARRY
2° 21 22
23
0 LO LO LO LO LO
1 HI LO LO LO LO
2 LO HI LO LO LO
3 HI HI LO LO LO
4
LO LO HI LO LO
5 HI
LO HI LO HI
6 LO HI HI LO HI
7 HI
HI HI LO HI
8
LO LO LO
HI
HI
9 HI LO LO HI HI
10 LO LO LO LO LO
level output line indicates a Quinary Count of 0-1, 2-3, 4-5,
6-7, or 8-9. The BCD Encoder translates the Quinary
Counter output to encode the 21, 22, and 23 bits of the
BCD output.
The Carry Comparator detects the tenth Clock input to
the First Decade Counter circuit to provide the CARRY
output (a HI to LO level transition; see Fig. 3-5).
The Reset Driver provides the HI level RESET and
CLEAR outputs on command of the DCU RESET input
from the Time Base and Control circuit. These outputs
reset the Binary and Quinary Counter stages to the zero­
count state.
Register (Counter and Readout Encoding circuit) through
Q339. Also, the Binary Counter output drives the Quinary
Counter through the Quinary Driver stage.
The Quinary Driver shapes the Binary Counter output to
provide a more constant-amplitude output to drive the
Quinary Counter. The Quinary Counter (divide-by-five
counter) counts the Binary Count, and provides a HI level
on one of five output lines to the BCD Encoder. The HI
Binary Counter Voltage Regulator
Negative 15 volts from the oscilloscope power supply is
applied to series Regulator Q317 to provide a —8.5-volt
output. U305A and U305B (U305 is a five-transistor array
IC) are connected as a comparator. Reference voltage for
the comparator is provided by v o 11 a g e divider
R300-R301-R302, which sets the base of U305B at about
—8.5 volts. The comparator output sets the base level of
Series Regulator Q317 through emitter-followers U305D-
U305E.
3-7