Tektronix 7D14, Instruction Manual

Page: 28 / 133

Circuit Description —7D14
A voltage divider consisting of R327 and U305C pro­
vides the Reference Voltage output from — 8.5-volt supply.
R320, Ref Voltage, adjusts the base level of U305C to set
the Reference Voltage output to about —3.5 volts.
Binary Counter
The Binary Counter consists of IC U329 and transistor
Q339. The + and — Clock inputs toggle U329 to provide a
Binary Count output with a repetition rate one-half that of
the Clock input. The U329-0 output drives the Quinary
Counter through the Quinary Driver stage. Q339 isolates
the U329-1 output from the BCD-output 2° bit.
tions the succeeding multi to respond to the next input,
etc. A resistor network between the multi outputs com­
pares the state of each multi to the state of both the pre­
ceding and succeeding multis to provide the output to the
BCD Encoder.
A simplified diagram of the Quinary Counter is shown in
Fig. 3-6(A). Each multi is made up of two transistors. The
multis are identified in Fig. 3-6(A) as multi A, Q362-Q364;
B, Q374-Q376; C, Q382-Q384; D, Q390-Q392; and E,
Q400-Q402. The output load resistor is shown above the
left transistor of each multi. The left transistor in each
multi receives the Binary Count input.
The Reset Driver CLEAR output is applied to U329 pin
1 through CR357. When the CLEAR level is HI, U329 is
cleared for a LO 1 output.
Reset Driver
The Reset Driver stage provides the RESET and CLEAR
outputs to the Binary Counter and Quinary Counter stages
respectively upon command of the Time Base and Control
circuit DCU RESET output.
The quiescently HI level DCU RESET input is applied to
the emitter of Q535 through CR351-R351. When the DCU
RESET input goes LO, the HI to LO level transition
momentarily forward biases Q353. This produces a
negative-going pulse on the collector of Q353. The negative­
going pulse is applied directly to the base of Q356, and
from the emitter of Q356 to the base of Q359 through
C358-R359. As this results in a forward-bias condition for
Q356 and reverse bias for Q359, the collectors of both
transistors momentarily go HI to provide RESET and
CLEAR outputs.
In each multi, the emitter-resistor current (e.g., Ia) will
flow through the transistor which has the more positive
base level. The current through a multi load resistor is
determined by the state of the corresponding multi and the
preceding one. Therefore, the load resistor current can be at
one of three levels; and, this will result in one of three
voltage levels dropped across the load resistor. For example,
the voltage dropped across load resistor B may be due to
one current unit (la or t|j), two current units (la + I^), or
zero. The voltage levels resulting from zero, one, and two
current units through a load resistor are represented in Fig.
3-6(B); and, are la, 0, and — respectively.
The RESET input resets the Quinary Counter to the
zero-count state. The momentary HI RESET level is applied
to the base of the left transistor in each multi through
R361-R348, and to the right transistor in multis A and C
through R365 and R385 respectively. This causes the left
transistor in multis B, D, and E to have the more positive
base and the right transistor in multis A and C to have the
more positive base. As a result, emitter-resistor current
flows through the right transistor in multis A-C, and
through the left transistor in multis B-D-E.
Quinary Driver
Q341-Q345
are connected as an emitter-coupled Schmitt
multivibrator. The 0-output of Binary Counter U329 is con­
nected to the base of Q341 through zener diode VR331 to
trigger the multivibrator. The output is taken from the col­
lector of Q345. When the Binary Counter-0 output is HI,
Q341 conducts and Q345 is turned off. Therefore, the
Quinary Driver Binary Count output is in phase with the
U 329-0 output.
Quinary Counter
The Quinary Counter is made up of five Schmitt multi­
vibrators, connected together to form a ring counter. Each
multivibrator (multi) receives the Binary Count input. How­
ever, the ring counter configuration is such that an input
will change the state of only one multi. In turn, this condi-
The reset, or zero-count, state of each multi is shown in
Fig. 3-6(A) by the direction of the arrow representing
emitter-resistor current. The resultant voltage dropped
across each load resistor is A, +; B, —; C, +; D, —; and E, 0.
The multi output voltage is applied to the base of the right
transistor through a zener diode. The zener diode lowers
the base voltage level; however, the relative voltage level
between the right transistor bases remains the same.
Fig. 3-7(A) shows the Quinary Driver Binary Count out­
put in relation to the Clock input to the Binary Counter. At
the first Clock input, the Binary Count output goes LO.
This pulls the base of each left transistor LO towards a
reverse-bias condition. Since the left transistors in multis A
and C are already non-conducting, the LO input has no
effect. Due to the voltage across the load resistors (— level),
the bases of the right transistors of multis B and D are
3-8