Tektronix 7D14, Instruction Manual

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Circuit Description—7D14
as lc in Fig. 3-14. Resistors R563-R565-R566-R567-R568
between
the I-inputs and —15 volts set the I-input currents
at the levels shown in Fig. 3-14. A LO level applied to a
D-(data) input directs the current set at the corresponding
l-input to pin 15 to provide the lc output (e.g., LO at D°
directs l0 current to pin 15). HI level TS-1 and TS-2 inputs
to the E-input (enable) at pin 8 inhibit an output during
these time-slots.
BCD inputs to U560 enable an lc analog output level
which is 0.1 milliampere (mA) less than necessary to
encode the desired decimal digit. A LO level applied to the
D z-input at pin 1 directs the current set at the lz-input to
pin 15 to add 0.1 mA to the lc output. The Time-Slot
Inverter HI-level outputs during TS-7 through TS-10 are
inverted by Q515 and applied to the Dz-input. These inputs
enable U560 to produce an lc output as encoded by the
BCD inputs at these time-slots. Inputs to the Dz-input
during time-slots TS-3 through TS-6 are determined by the
inputs to the Zero-Cancel Logic stage (see the discussion of
the Zero-Cancel Logic stage under Counter Circuit).
Decimal Logic and Measurement Units Logic
These stages encode the readout system for decimal
point position and measurement units as determined by
MEASUREMENT INTERVAL switch S60.
MEASUREMENT INTERVAL Switch Logic. S60 pro­
vides logic level outputs to indicate the switch setting. The
time-slot TS-1 input is switched through S60 to either the
Decimal Logic or the Measurement Units Logic stage. S60
also provides the INTERNAL output to the Time Base and
Control circuit. When this output is HI, internal gate (1 ms
— 10 s) operation is indicated. When the INTERNAL out­
put is LO, manual or external gate operation is indicated.
(TS-1) to determine placement of the displayed decimal
point. The level of the Column output current is deter­
mined by the inputs from the MEASUREMENT INTER­
VAL Switch Logic. Also, decimal-logic Decimal Position
Five and Decimal Position Six (DP-5 and DP-6) outputs are
provided to the Zero-Cancel Logic stage. Q653, Q658,
Q663, and Q670 are saturated due to the forward bias
levels set at their bases by the resistor voltage dividers. This
stage operates as follows:
When the 100 ms input is LO, the other inputs are HI.
This LO level reverse biases Q653; the collector is HI to
provide the DP-5 output. At the same time, TS-1 interro­
gates R671-R659-R673-R674. The TS-1 current through
R674 encodes the Row Current output for decimals. The
TS-1 current through R673 encodes the Column Current
output for decimal point location 5. The TS-1 current
through R671 and R659 is sinked to ground through satu­
rated transistors Q670 and Q658 respectively.
When the 10 ms or 10 s input is LO, the CR665-CR666
NOR-gate output is LO. This LO level reverse biases Q663
and Q670. The collector of Q663 goes HI to provide the
DP-6 output. Due to reverse bias, Q670 is cut off to allow
the TS-1 current through R671 to be added to the Column
Current output through CR671. This adds 0.1 mA to the
TS-1 current through R673 to encode decimal point loca­
tion 6.
Similarly, a LO 1 ms or 1 s input reverse biases Q658
through diode NOR-gate CR656-CR655 to allow TS-1 cur­
rent through R659 to pass through CR659. This adds 0.2
mA to the TS-1 current through R673 to encode decimal
point location 7.
When one of the S60 internal gate buttons (1 ms — 10 s)
is in, +5 volts applied through R660 provides a HI
INTERNAL output level. A LO level (ground) is provided
on one of five output lines to indicate which internal gate
button is in. For example, if the 1 ms button is in, a LO 1
ms ’ output level is connected to CR655-CR676. TS-1 is
connected through S60 to the Decimal Logic stage under
the internal gate condition.
When one of the MANUAL GATE buttons (ON-OFF) is
in, R660 is connected to ground to hold the INTERNAL
output LO. TS-1 is connected to the Measurement Units
Logic stage to encode a JUMP instruction.
The S60 1 ms, 10 ms, 100 ms, T"s^ and 10 s outputs are
applied to the Decimal Logic and Measurement Units Logic
stages through diode-logic NOR gates. A simplified diagram
of the diode-logic NOR gates, Decimal Logic, and Measure­
ment Units Logic stages is shown in Fig. 3-15.
Decimal Logic. This stage encodes the Channel 1
Column and Row output current levels for time-slot one
Measurement Units Logic. This stage encodes the
Channel 2 Column and Row Current output levels for TS-4,
TS-5, and TS-6. R686-R687 and R688-R689 encode the
Column and Row Current outputs for TS-5 and TS-6
respectively (see Table 3-1, 7D14 Readout Encoding
Format). R683-R684 set the Column and Row Current out­
puts for TS-4 to encode k (kilo- prefix). When the 1 s or TO
s input is LO, Q680 is saturated by the voltage level set at
its base by voltage divider R677-R678-R679. The TS-4
current through
R681 is sinked to ground through Q680.
When the 1 ms, 1Ü ms, or 100 ms input is LO, the output
of diode-logic NOR gate CR676-CR677-CR678 is LO to
reverse biase Q680. This allows the TS-4 current through
R681 to add 0.1 mA to the Column Current output to
encode an M (mega- prefix).
When TS-1 is applied to the Measurement Units Logic
stage through S60 for MANUAL GATE operation (see
MEASUREMENT INTERVAL Switch Logic), R682
encodes the Row Current output for a JUMP instruction
(1.3 mA).
3-16