Tektronix 7D14, Instruction Manual

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Circuit Description —7D14
Fig. 3-9. Counter circuit detailed block diagram.
COUNTER CIRCUIT
General
The Counter circuit consists of the Decade Counters,
Storage Registers, Multiplexers, Overflow Register, Zero­
Cancel Logic, and the Time Slot Inverter stages. A detailed
block diagram of the Counter circuit is shown in Fig. 3-9. A
schematic of this circuit is shown on Diagram 3 in the
Diagrams section.
The Decade Counters count the CARRY output from
the First Decade Counter circuit, and translate this count to
a binary-coded-decimal (BCD) form. This BCD data, along
with the First Decade Counter BCD output, is stored in the
Storage Registers. Upon command of the DISPLAY input,
the stored BCD data is transferred to the Multiplexers.
When the Decade Counters have counted to 99999999, the
counters are full. At the next count, the Decade Counters
provide a HI to LO level transition FULL COUNT output
to the Overflow Register.
circuit to reset the Decade Counters to the zero-count state
and to reset the OVERFLOW output HI.
The time-slot pulses from the oscilloscope readout
system are connected to the Counter circuit and to the
Readout Encoding circuit through the Interface Connector.
The time-slot pulses are inverted by the Time-Slot Inverters
to provide time-slot data to the Multiplexers, Zero-Cancel
Logic, and to the Readout Encoding circuit.
The BCD outputs of the Storage Registers are applied to
the Multiplexers and Zero-Cancel Logic stages. The Multi­
plexers stage sequences the BCD inputs to provide the
Readout Encoding circuit with only four specific BCD bits
at any one time. The sequencing is determined by the out­
puts of the Time-Slot Inverters to ensure proper placement
of each digit in the readout display. The Zero-Cancel Logic
stage provides zero-cancel logic outputs to the Readout
Encoding circuit as determined by inputs from the Storage
Registers, Overflow Register, and Time-Slot Inverter stages.
The Overflow Register stores the FULL COUNT input,
and provides the OVERFLOW output on command of the
DISPLAY input. DCU RESET is applied to the Counter
Decade Counters
The 10 1 through 107 Decade Counters are seven cas­
caded divide-by-ten IC counters. Each decade translates the
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