Circuit
Description
—7D14
The
Display
Enable stage produces
the
LO level
DIS
PLAY
output
as determined by the inputs to this stage. The
INTERNAL input
is applied to this stage in the off position
of
the
Manual Gate Storage switch. When the INTERNAL
input
is
HI,
the setting of the
Manual Gate Storage switch
has
no effect on the operation of this
stage. The Display
Enable stage
will produce the
DISPLAY output on
command
of the Gate Generator CLEAR
output, or on
command
of
the Reset Input stage RESET output.
When
the INTERNAL input
is LO and the Manual Gate
Storage
switch
is in
the off position, the DISPLAY output
is
held LO. When
the INTERNAL input is LO and the
Manua
l Gate Storage
switch is
in the on position, the DIS
PLAY
output is produced on command of the other inputs
as mentioned
previously.
The
Display Generator stage produces an output at a
time
after the end of the GATE "on"
time as determined
by
the
DISPLAY TIME control setting. The Display
Gen
erator
output is amplified by the DCU RESET Driver stage
to
provide the
DCU RESET output. Also, the DCU RESET
Driver
stage
produces the DCU RESET output on
command
of the Reset
Input
stage RESET output signal.
5
MHz
Oscillator
The 5
MHz Oscillator, Y600, provides a precise five-
megahertz
output. An internal adjustment provides a means
of
setting
the oscillator frequency. The five-megahertz out
put is
connected
to the Divide by Five
Counter stage.
Divide
by
Five
Counter
The Divide by
Five
Counter stage consists of
IC U602.
The
five-megahertz input
is applied to the T (trigger) input
at
pin 6.
The counting operation
is performed on
the
negative-going
transition
at the T input. The one-megahertz
output at
pin 12 is provided to
the Reference Frequency
Gate when
the REF FREQ/CH B switch is in the INT 1
MHz position,
and
to the Monitor Buffer stage. In the EXT
IN
position
of
the REF FREQ/CH B switch, a LO
level
(ground)
is applied to
the direct-clear input of U602 at pin
13. This LO holds the output LO.
Monitor
Buffer
The Monitor Buffer
stage consists
of Q606. This
stage
amplifies
the
one-megahertz output of the Divide
by Five
Counter
stage.
The Monitor Buffer output is connected
to
the
REF
FREQ/CH B MONITOR output connector when
the
REF
FREQ/CH B switch is in the INT 1 MHz position.
Channel
B
Input
Shaper
The
Channel B Input Shaper shapes and amplifies signals
connected
to
the REF
FREQ/CH B EXT IN connector
when the EXT IN
button is pressed.
The signal
connected to the EXT IN connector is AC-
coupled
to the base
of Q613 through C610, R610, and
C61
1.
Q613 and Q618 make up an emitter-coupled bistable
multivibrator.
The
multivibrator
shapes the input signal to
provide
a
square-wave
output
to Q623 through
R621-C621.
Q623
amplifies the square-wave signal. The
output
at the
collector
of Q623 is connected
to ground
when the INT 1
MHZ
button
is
in, or connected to U729E
when the EXT
IN
button is in.
Reference Frequency Gate
The
Reference Frequency
Gate stage consists of NAND-
gate U731D and isolation-transistor U729E.
The reference
frequency signal selected by the REF FREQ/CH
B switch is
applied
to one
input of the NAND gate through U729E.
The
INTERNAL input
is connected to the other NAND-
gate
input. When INTERNAL is
HI
(1 ms through 10 s
positions
of
the MEASUREMENT INTERVAL switch), the
reference-frequency signal is
provided from the NAND-gate
output (pin 11)
to theT-input of U735 in the Gate Genera
tor
stage.
Time
Base
Decade Counters
The
Time
Base Decade Counters count the input
selected by
the REF FREQ/CH
B switch, S50, and applied
to
pin 8-U628 (trigger). The counters consist of seven
cascaded divide-by-ten
counters, U628-U630-U632-U634-
U636-U638-U640.
Each decade
is clocked with a negative-going transition
applied
to
the T
input, pin 8. With the exception of U628,
each
decade
is clocked only when
the output of the pre
ceding decade changes from HI
to LO.
The
DCU RESET input to pin 13-U628 and pin 1 of the
remaining
decades reset the counters for an output of
9999990;
i.e.,
pin 12-U640 through U630 is HI, and pin
12-
U628 is
LO.
Reset
Input
The
Reset Input stage provides an input to the Time
Base
and Control circuit from the RESET pushbutton and
pin-jack
connector.
When the RESET button is
pressed in,
or
when
a HI level is applied to the base of Q703 through
the
pin-jack
connector, a HI level RESET output is set at
pin
13-U708D. When
the RESET button is released, or a
LO
level is applied
to the base of Q703, the output at pin
13-
U708D returns LO. Q738 inverts
the HI RESET level to
provide
a LO level to the direct-clear
input of U735 in the
Gate
Generator stage.
Manual/External
Gate
Input
RS flip-flop
U708A-U708B, in
conjunction with
Q714-Q742-U729A-U729B,
provides outputs
to the Gate
3-20
Summary of Contents for 7D14
Page 4: ...7D14 ...
Page 11: ...Operating Instructions 7D14 Fig 2 1 7D14 front panel controls and connectors 2 2 ...
Page 33: ... 3 13 Fig 3 11 Logic diagram for Zero Cancel Logic stage Circuit Description 7D14 ...
Page 38: ...3 18 Fig 3 16 Time Base and Control circuit detailed block diagram Circuit Description 7D14 ...
Page 44: ...NOTES ...
Page 46: ...NJ Fig 4 1 Electrode configuration for semiconductors in this instrument I ...
Page 68: ...NOTES ...
Page 96: ... 7DI 4 DIGITAL COUNTER UNIT ...
Page 98: ...GRS 0371 BLOCK DIAGRAM ...
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Page 103: ...0 0 I 200 mV 500 µs 0 001 200 mV 500 µs 0 001 MHz 00 mV E 00 µs 0 001 MHz ...
Page 106: ...1 ...
Page 110: ...A2 Logic Circuit Board Assembly jQ798i 798 jc743 CR744t uni R724 R742 JL744S FrR796 ...
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Page 114: ...P 0 A2 LOGIC BOARD ...
Page 121: ... A B D t F H J NPR Tj ZWX V A AC M AEA HUM qAZ DEF HJ N P R S T J V V7X y ABM APAI AA 7DI4 ...
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Page 130: ...4 7D14 DIGITAL COUNTER ...