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ST STM32F101xx series Reference Manual Download Page 763

RM0008

Universal synchronous asynchronous receiver transmitter (USART)

Doc ID 13902 Rev 12

763/1096

   

   

   

27.3.1 

USART block diagram

USART character description

Word length may be selected as being either 8 or 9 bits by programming the M bit in the 
USART_CR1 register (see 

Figure 278

).

The TX pin is in low state during the start bit. It is in high state during the stop bit. 

An 

Idle character

 is interpreted as an entire frame of “1”s followed by the start bit of the next 

frame which contains data (The number of “1” ‘s will include the number of stop bits).

WAKE

UP

UNIT

RECEIVER

CONTROL

SR

TRANSMIT

CONTROL

TXE TC RXNE IDLE ORE NE FE

USART

CONTROL

INTERRUPT

CR1

M

WAKE

Receive Data Register (RDR)

Receive Shift Register

Read

Transmit Data Register (TDR)

Transmit Shift Register

Write

SW_RX

TX

(DATA REGISTER) DR

TRANSMITTER

 CLOCK

RECEIVER 

CLOCK

RECEIVER RATE

TRANSMITTER RATE

 

f

PCLKx(x=1,2)

 CONTROL

CONTROL

/16

CONVENTIONAL BAUD RATE GENERATOR

SBK

RWU

RE

TE

IDLE

RXNE

TCIE

TXEIE

CR1

UE

PCE

PS

PEIE

PE

PWDATA

IRLP

SCEN

IREN

DMAR

DMAT

USART Address

CR2

CR3

IrDA
SIR
ENDEC
BLOCK

LINE

CKEN CPOL CPHA LBCL

CK CONTROL

CK

CR2

GT

STOP[1:0]

NACK

DIV_Mantissa

15

0

RE

USART_BRR

/

USARTDIV

TE

HD

(CPU or DMA)

(CPU or DMA)

PRDATA

Hardware
flow
controller

CTS LBD

RX

IRDA_OUT

IRDA_IN

nRTS

nCTS

GTPR

PSC

IE

IE

DIV_Fraction

4

USARTDIV = DIV_Ma (DIV_Fraction / 16)

Summary of Contents for STM32F101xx series

Page 1: ...vice characteristics please refer to the low medium high and XL density STM32F101xx and STM32F103xx datasheets to the low and medium density STM32F102xx datasheets and to the STM32F105xx STM32F107xx connectivity line datasheet For information on programming erasing and protection of the internal Flash memory please refer to RM0042 the Flash programming manual for low medium high density and connec...

Page 2: ...ded Flash memory 54 3 4 Boot configuration 60 4 CRC calculation unit 62 4 1 CRC introduction 62 4 2 CRC main features 62 4 3 CRC functional description 63 4 4 CRC registers 63 4 4 1 Data register CRC_DR 63 4 4 2 Independent data register CRC_IDR 63 4 4 3 Control register CRC_CR 64 4 4 4 CRC register map 64 5 Power control PWR 65 5 1 Power supplies 65 5 1 1 Independent A D and D A converter supply ...

Page 3: ...ster map 78 6 Backup registers BKP 79 6 1 BKP introduction 79 6 2 BKP main features 79 6 3 BKP functional description 80 6 3 1 Tamper detection 80 6 3 2 RTC calibration 80 6 4 BKP registers 81 6 4 1 Backup data register x BKP_DRx x 1 42 81 6 4 2 RTC clock calibration register BKP_RTCCR 81 6 4 3 Backup control register BKP_CR 82 6 4 4 Backup control status register BKP_CSR 82 6 4 5 BKP register map...

Page 4: ...lock enable register RCC_AHBENR 108 7 3 7 APB2 peripheral clock enable register RCC_APB2ENR 109 7 3 8 APB1 peripheral clock enable register RCC_APB1ENR 111 7 3 9 Backup domain control register RCC_BDCR 115 7 3 10 Control status register RCC_CSR 117 7 3 11 RCC register map 119 8 Connectivity line devices reset and clock control RCC 120 8 1 Reset 120 8 1 1 System reset 120 8 1 2 Power reset 121 8 1 ...

Page 5: ...nal description 154 9 1 1 General purpose I O GPIO 156 9 1 2 Atomic bit set or reset 156 9 1 3 External interrupt wakeup lines 157 9 1 4 Alternate functions AF 157 9 1 5 Software remapping of I O alternate functions 157 9 1 6 GPIO locking mechanism 157 9 1 7 Input configuration 158 9 1 8 Output configuration 158 9 1 9 Alternate function configuration 159 9 1 10 Analog configuration 160 9 1 11 GPIO...

Page 6: ...4 External interrupt configuration register 2 AFIO_EXTICR2 184 9 4 5 External interrupt configuration register 3 AFIO_EXTICR3 185 9 4 6 External interrupt configuration register 4 AFIO_EXTICR4 185 9 4 7 AF remap and debug I O configuration register2 AFIO_MAPR2 186 9 5 GPIO and AFIO register maps 187 10 Interrupts and events 189 10 1 Nested vectored interrupt controller NVIC 189 10 1 1 SysTick cali...

Page 7: ...1 3 10 Discontinuous mode 213 11 4 Calibration 213 11 5 Data alignment 214 11 6 Channel by channel programmable sample time 215 11 7 Conversion on external trigger 215 11 8 DMA request 217 11 9 Dual ADC mode 218 11 9 1 Injected simultaneous mode 220 11 9 2 Regular simultaneous mode 220 11 9 3 Fast interleaved mode 221 11 9 4 Slow interleaved mode 221 11 9 5 Alternate trigger mode 222 11 9 6 Indepe...

Page 8: ...DR 241 11 12 15 ADC register map 241 12 Digital to analog converter DAC 243 12 1 DAC introduction 243 12 2 DAC main features 243 12 3 DAC functional description 245 12 3 1 DAC channel enable 245 12 3 2 DAC output buffer enable 245 12 3 3 DAC data format 245 12 3 4 DAC conversion 246 12 3 5 DAC output voltage 247 12 3 6 DAC trigger selection 247 12 3 7 DMA request 248 12 3 8 Noise generation 248 12...

Page 9: ...R12R2 259 12 5 7 DAC channel2 12 bit left aligned data holding register DAC_DHR12L2 259 12 5 8 DAC channel2 8 bit right aligned data holding register DAC_DHR8R2 259 12 5 9 Dual DAC 12 bit right aligned data holding register DAC_DHR12RD 260 12 5 10 DUAL DAC 12 bit left aligned data holding register DAC_DHR12LD 260 12 5 11 DUAL DAC 8 bit right aligned data holding register DAC_DHR8RD 261 12 5 12 DAC...

Page 10: ...troduction 280 14 2 TIM1 TIM8 main features 281 14 3 TIM1 TIM8 functional description 283 14 3 1 Time base unit 283 14 3 2 Counter modes 284 14 3 3 Repetition counter 292 14 3 4 Clock selection 294 14 3 5 Capture compare channels 296 14 3 6 Input capture mode 298 14 3 7 PWM input mode 299 14 3 8 Forced output mode 300 14 3 9 Output compare mode 301 14 3 10 PWM mode 302 14 3 11 Complementary output...

Page 11: ... 13 TIM1 TIM8 repetition counter register TIMx_RCR 339 14 4 14 TIM1 TIM8 capture compare register 1 TIMx_CCR1 339 14 4 15 TIM1 TIM8 capture compare register 2 TIMx_CCR2 340 14 4 16 TIM1 TIM8 capture compare register 3 TIMx_CCR3 340 14 4 17 TIM1 TIM8 capture compare register 4 TIMx_CCR4 341 14 4 18 TIM1 TIM8 break and dead time register TIMx_BDTR 341 14 4 19 TIM1 TIM8 DMA control register TIMx_DCR ...

Page 12: ...ter 2 TIMx_CCMR2 397 15 4 9 TIMx capture compare enable register TIMx_CCER 398 15 4 10 TIMx counter TIMx_CNT 399 15 4 11 TIMx prescaler TIMx_PSC 399 15 4 12 TIMx auto reload register TIMx_ARR 400 15 4 13 TIMx capture compare register 1 TIMx_CCR1 401 15 4 14 TIMx capture compare register 2 TIMx_CCR2 401 15 4 15 TIMx capture compare register 3 TIMx_CCR3 402 15 4 16 TIMx capture compare register 4 TI...

Page 13: ..._CCMR1 435 16 5 8 TIM9 12 capture compare enable register TIMx_CCER 438 16 5 9 TIM9 12 counter TIMx_CNT 439 16 5 10 TIM9 12 prescaler TIMx_PSC 439 16 5 11 TIM9 12 auto reload register TIMx_ARR 439 16 5 12 TIM9 12 capture compare register 1 TIMx_CCR1 440 16 5 13 TIM9 12 capture compare register 2 TIMx_CCR2 440 16 5 14 TIM9 12 register map 441 16 6 TIM10 11 13 14 registers 442 16 6 1 TIM10 11 13 14 ...

Page 14: ...IM6 TIM7 event generation register TIMx_EGR 461 17 4 6 TIM6 TIM7 counter TIMx_CNT 461 17 4 7 TIM6 TIM7 prescaler TIMx_PSC 462 17 4 8 TIM6 TIM7 auto reload register TIMx_ARR 462 17 4 9 TIM6 TIM7 register map 463 18 Real time clock RTC 464 18 1 RTC introduction 464 18 2 RTC main features 465 18 3 RTC functional description 466 18 3 1 Overview 466 18 3 2 Resetting RTC registers 467 18 3 3 Reading RTC...

Page 15: ... 480 19 4 4 Status register IWDG_SR 480 19 4 5 IWDG register map 481 20 Window watchdog WWDG 482 20 1 WWDG introduction 482 20 2 WWDG main features 482 20 3 WWDG functional description 482 20 4 How to program the watchdog timeout 484 20 5 Debug mode 484 20 6 WWDG registers 485 20 6 1 Control register WWDG_CR 485 20 6 2 Configuration register WWDG_CFR 486 20 6 3 Status register WWDG_SR 486 20 6 4 W...

Page 16: ... Flash pre wait functionality 531 21 6 6 Error correction code computation ECC NAND Flash 532 21 6 7 PC Card CompactFlash operations 532 21 6 8 NAND Flash PC Card controller registers 535 21 6 9 FSMC register map 541 22 Secure digital input output interface SDIO 543 22 1 SDIO main features 543 22 2 SDIO bus topology 544 22 3 SDIO functional description 546 22 3 1 SDIO adapter 547 22 3 2 SDIO AHB i...

Page 17: ...n 582 22 6 4 SDIO interrupts 582 22 7 CE ATA specific operations 582 22 7 1 Command completion signal disable 582 22 7 2 Command completion signal enable 582 22 7 3 CE ATA interrupt 583 22 7 4 Aborting CMD61 583 22 8 HW flow control 583 22 9 SDIO registers 583 22 9 1 SDIO power control register SDIO_POWER 584 22 9 2 SDI clock control register SDIO_CLKCR 584 22 9 3 SDIO argument register SDIO_ARG 5...

Page 18: ...programming 602 23 4 2 System and power on reset 603 23 4 3 Double buffered endpoints 608 23 4 4 Isochronous transfers 610 23 4 5 Suspend Resume events 611 23 5 USB registers 613 23 5 1 Common registers 614 23 5 2 Endpoint specific registers 621 23 5 3 Buffer descriptor table 625 23 5 4 USB register map 628 24 Controller area network bxCAN 630 24 1 bxCAN introduction 630 24 2 bxCAN main features 6...

Page 19: ...9 2 CAN control and status registers 650 24 9 3 CAN mailbox registers 660 24 9 4 CAN filter registers 667 24 9 5 bxCAN register map 671 25 Serial peripheral interface SPI 674 25 1 SPI introduction 674 25 2 SPI and I2 S main features 675 25 2 1 SPI features 675 25 2 2 I2 S features 676 25 3 SPI functional description 677 25 3 1 General description 677 25 3 2 Configuring the SPI in slave mode 680 25...

Page 20: ...5 4 SPI data register SPI_DR 721 25 5 5 SPI CRC polynomial register SPI_CRCPR not used in I2 S mode 721 25 5 6 SPI RX CRC register SPI_RXCRCR not used in I2S mode 722 25 5 7 SPI TX CRC register SPI_TXCRCR not used in I2 S mode 722 25 5 8 SPI_I2 S configuration register SPI_I2SCFGR 723 25 5 9 SPI_I2S prescaler register SPI_I2SPR 724 25 5 10 SPI register map 725 26 Inter integrated circuit I2 C inte...

Page 21: ...ART introduction 759 27 2 USART main features 760 27 3 USART functional description 761 27 3 1 USART block diagramUSART character description 763 27 3 2 Transmitter 765 27 3 3 Receiver 768 27 3 4 Fractional baud rate generation 772 27 3 5 USART receiver s tolerance to clock deviation 774 27 3 6 Multiprocessor communication 774 27 3 7 Parity control 776 27 3 8 LIN local interconnection network mode...

Page 22: ...804 28 2 3 Peripheral mode features 804 28 3 OTG_FS functional description 805 28 3 1 OTG full speed core 805 28 3 2 Full speed OTG PHY 805 28 4 OTG dual role device DRD 806 28 4 1 ID line detection 807 28 4 2 HNP dual role device 807 28 4 3 SRP dual role device 807 28 5 USB peripheral 808 28 5 1 SRP capable peripheral 808 28 5 2 Peripheral states 809 28 5 3 Peripheral endpoints 810 28 6 USB host ...

Page 23: ... 16 3 Host mode registers 852 28 16 4 Device mode registers 863 28 16 5 OTG_FS power and clock gating control register OTG_FS_PCGCCTL 885 28 16 6 OTG_FS register map 886 28 17 OTG_FS programming model 892 28 17 1 Core initialization 892 28 17 2 Host initialization 894 28 17 3 Device initialization 894 28 17 4 Host programming model 895 28 17 5 Device programming model 912 28 17 6 Operational model...

Page 24: ... Power management PMT 970 29 5 9 Precision time protocol IEEE1588 PTP 973 29 6 Ethernet functional description DMA controller operation 979 29 6 1 Initialization of a transfer using DMA 980 29 6 2 Host bus burst access 980 29 6 3 Host data buffer alignment 981 29 6 4 Buffer size calculations 981 29 6 5 DMA arbiter 982 29 6 6 Error response to DMA 982 29 6 7 Tx DMA configuration 982 29 6 8 Rx DMA c...

Page 25: ...ocking mechanism 1055 31 6 1 MCU device ID code 1055 31 6 2 Boundary scan TAP 1056 31 6 3 Cortex M3 TAP 1057 31 6 4 Cortex M3 JEDEC 106 ID code 1057 31 7 JTAG debug port 1057 31 8 SW debug port 1059 31 8 1 SW protocol introduction 1059 31 8 2 SW protocol sequence 1059 31 8 3 SW DP state machine reset idle states ID code 1060 31 8 4 DP and AP read write accesses 1060 31 8 5 SW DP registers 1061 31 ...

Page 26: ...chdog bxCAN and I2C 1068 31 16 3 Debug MCU configuration register 1069 31 17 TPIU trace port interface unit 1072 31 17 1 Introduction 1072 31 17 2 TRACE pin assignment 1072 31 17 3 TPUI formatter 1074 31 17 4 TPUI frame synchronization packets 1075 31 17 5 Transmission of the synchronization frame packet 1075 31 17 6 Synchronous mode 1075 31 17 7 Asynchronous mode 1076 31 17 8 TRACECLKIN connectio...

Page 27: ...tion table 156 Table 21 Output MODE bits 156 Table 22 Advanced timers TIM1 TIM8 161 Table 23 General purpose timers TIM2 3 4 5 161 Table 24 USARTs 161 Table 25 SPI 162 Table 26 I2S 162 Table 27 I2C 163 Table 28 BxCAN 163 Table 29 USB 163 Table 30 OTG_FS pin configuration 163 Table 31 SDIO 164 Table 32 FSMC 164 Table 33 Other IOs 164 Table 34 CAN1 alternate function remapping 170 Table 35 CAN2 alte...

Page 28: ...triggers 247 Table 75 DAC register map 262 Table 76 Programmable data width endian behavior when bits PINC MINC 1 268 Table 77 DMA interrupt requests 269 Table 78 Summary of DMA1 requests for each channel 271 Table 79 Summary of DMA2 requests for each channel 272 Table 80 DMA register map and reset values 278 Table 81 Counting direction versus encoder signals 313 Table 82 TIMx Internal trigger con...

Page 29: ... bit fields 510 Table 122 FSMC_BCRx bit fields 512 Table 123 FSMC_BTRx bit fields 512 Table 124 FSMC_BCRx bit fields 517 Table 125 FSMC_BTRx bit fields 518 Table 126 FSMC_BCRx bit fields 520 Table 127 FSMC_BTRx bit fields 520 Table 128 Programmable NAND PC Card access parameters 527 Table 129 8 bit NAND Flash 527 Table 130 16 bit NAND Flash 528 Table 131 16 bit PC Card 528 Table 132 Supported memo...

Page 30: ...ransmit mailbox mapping 645 Table 179 Receive mailbox mapping 645 Table 180 bxCAN register map and reset values 671 Table 181 SPI interrupt requests 696 Table 182 Audio frequency precision using standard 8 MHz HSE high density and XL density devices only 707 Table 183 Audio frequency precision using standard 25 MHz and PLL3 connectivity line devices only 708 Table 184 Audio frequency precision usi...

Page 31: ...ble 214 Ethernet register map and reset values 1042 Table 215 SWJ debug port pins 1052 Table 216 Flexible SWJ DP pin assignment 1053 Table 217 JTAG debug port data registers 1057 Table 218 32 bit debug port registers addressed through the shifted value A 3 2 1058 Table 219 Packet request 8 bits 1059 Table 220 ACK response 3 bits 1060 Table 221 DATA transfer 33 bits 1060 Table 222 SW DP registers 1...

Page 32: ...n latency 212 Figure 26 Calibration timing diagram 214 Figure 27 Right alignment of data 214 Figure 28 Left alignment of data 214 Figure 29 Dual ADC block diagram 1 219 Figure 30 Injected simultaneous mode on 4 channels 220 Figure 31 Regular simultaneous mode on 16 channels 221 Figure 32 Fast interleaved mode on 1 channel in continuous conversion mode 221 Figure 33 Slow interleaved mode on 1 chann...

Page 33: ...re 70 Counter timing diagram update event with ARPE 1 counter underflow 292 Figure 71 Counter timing diagram Update event with ARPE 1 counter overflow 292 Figure 72 Update rate examples depending on mode and TIMx_RCR register settings 293 Figure 73 Control circuit in normal mode internal clock divided by 1 294 Figure 74 TI2 external clock connection example 294 Figure 75 Control circuit in externa...

Page 34: ...igure 120 Control circuit in normal mode internal clock divided by 1 360 Figure 121 TI2 external clock connection example 361 Figure 122 Control circuit in external clock mode 1 361 Figure 123 External trigger input block 362 Figure 124 Control circuit in external clock mode 2 362 Figure 125 Capture compare channel example channel 1 input stage 363 Figure 126 Capture compare channel 1 main circuit...

Page 35: ...om 1 to 2 454 Figure 171 Counter timing diagram with prescaler division change from 1 to 4 454 Figure 172 Counter timing diagram internal clock divided by 1 455 Figure 173 Counter timing diagram internal clock divided by 2 456 Figure 174 Counter timing diagram internal clock divided by 4 456 Figure 175 Counter timing diagram internal clock divided by N 456 Figure 176 Counter timing diagram update ...

Page 36: ...y devices 633 Figure 223 bxCAN operating modes 635 Figure 224 bxCAN in silent mode 636 Figure 225 bxCAN in loop back mode 636 Figure 226 bxCAN in combined mode 637 Figure 227 Transmit mailbox states 638 Figure 228 Receive FIFO states 639 Figure 229 Filter bank scale configuration register organization 642 Figure 230 Example of filter numbering 643 Figure 231 Filtering mechanism example 644 Figure ...

Page 37: ...s protocol 728 Figure 269 I2C block diagram 729 Figure 270 Transfer sequence diagram for slave transmitter 730 Figure 271 Transfer sequence diagram for slave receiver 731 Figure 272 Transfer sequence diagram for master transmitter 734 Figure 273 Method 1 transfer sequence diagram for master receiver 736 Figure 274 Method 2 transfer sequence diagram for master receiver when N 2 737 Figure 275 Metho...

Page 38: ...packet 917 Figure 319 Bulk OUT transaction 923 Figure 320 TRDT max timing case 932 Figure 321 A device SRP 933 Figure 322 B device SRP 934 Figure 323 A device HNP 935 Figure 324 B device HNP 936 Figure 325 ETH block diagram 942 Figure 326 SMI interface signals 943 Figure 327 MDIO timing and frame structure Write cycle 944 Figure 328 MDIO timing and frame structure Read cycle 945 Figure 329 Media i...

Page 39: ...TxDMA operation in OSF mode 986 Figure 354 Transmit descriptor 987 Figure 355 Receive DMA operation 993 Figure 356 Rx DMA descriptor structure 995 Figure 357 Interrupt scheme 1001 Figure 358 Ethernet MAC remote wakeup frame filter register ETH_MACRWUFFR 1011 Figure 359 Block diagram of STM32F10xxx level and Cortex M3 level debug support 1049 Figure 360 SWJ debug port 1050 Figure 361 JTAG TAP conne...

Page 40: ... STM32F103xx Medium density STM32F103xx High and XL density STM32F103xx STM32F105xx STM32F107xx Section 2 Documentation conventions Section 3 Memory and bus architecture Section 4 CRC calculation unit Section 5 Power control PWR Section 6 Backup registers BKP Section 7 Low medium high and XL density reset and clock control RCC Section 8 Connectivity line devices reset and clock control RCC Section...

Page 41: ...atchdog WWDG Section 21 Flexible static memory controller FSMC Section 22 Secure digital input output interface SDIO Section 23 Universal serial bus full speed device interface USB Section 24 Controller area network bxCAN Section 25 Serial peripheral interface SPI Table 1 Sections related to each STM32F10xxx product continued Low density STM32F101xx Medium density STM32F101xx High and XL density S...

Page 42: ...l speed OTG_FS Section 29 Ethernet ETH media access control MAC with DMA controller Section 30 Device electronic signature Section 31 Debug support DBG Table 1 Sections related to each STM32F10xxx product continued Low density STM32F101xx Medium density STM32F101xx High and XL density STM32F101x Low density STM32F102xx Medium density STM32F102xx Low density STM32F103xx Medium density STM32F103xx H...

Page 43: ... time clock RTC Independent watchdog IWDG Window watchdog WWDG Flexible static memory controller FSMC Secure digital input output interface SDIO USB full speed device USB Controller area network bxCAN Serial peripheral interface SPI Inter integrated circuit I2C interface USART USB on the go full speed OTG_FS Ethernet ETH Section 2 Documentation conventions Section 3 Memory and bus architecture Sec...

Page 44: ...IO Section 23 Universal serial bus full speed device interface USB Section 24 Controller area network bxCAN Table 2 Sections related to each peripheral Backup registers BKP General purpose I Os GPIOs Analog to digital converter ADC Digital to analog converter DAC Advanced control timers TIM1 TIM8 General purpose timers TIM2 to TIM5 General purpose timers TIM9 to TIM14 Basic timers TIM6 TIM7 Real t...

Page 45: ...le 2 Sections related to each peripheral Backup registers BKP General purpose I Os GPIOs Analog to digital converter ADC Digital to analog converter DAC Advanced control timers TIM1 TIM8 General purpose timers TIM2 to TIM5 General purpose timers TIM9 to TIM14 Basic timers TIM6 TIM7 Real time clock RTC Independent watchdog IWDG Window watchdog WWDG Flexible static memory controller FSMC Secure digi...

Page 46: ...vailability and number across all STM32F10xxx sales types please refer to the low medium high and XL density STM32F101xx and STM32F103xx datasheets to the low and medium density STM32F102xx datasheets and to the connectivity line devices STM32F105xx STM32F107xx read write rw Software can read and write to these bits read only r Software can only read these bits write only w Software can only write...

Page 47: ...onnect all the APB peripherals These are interconnected using a multilayer AHB bus architecture as shown in Figure 1 Figure 1 System architecture FLITF Ch 1 Ch 2 Ch 7 Cortex M3 DMA1 ICode DCode System AHB system bus DMA Request APB1 Flash Bridge 2 Bridge 1 Ch 1 Ch 2 Ch 5 DMA2 SRAM FSMC SDIO APB2 DMA request ADC3 GPIOC USART1 TIM8 SPI1 TIM1 ADC2 ADC1 GPIOG GPIOF GPIOE GPIOD GPIOB GPIOA EXTI AFIO DA...

Page 48: ...e 2 Figure 2 System architecture in connectivity line devices ICode bus This bus connects the Instruction bus of the Cortex M3 core to the Flash memory instruction interface Prefetching is performed on this bus FLITF Ch 1 Ch 2 Ch 7 Cortex M3 DMA1 ICode DCode System DMA request APB1 Flash Bridge 2 Bridge 1 Ch 1 Ch 2 Ch 5 DMA2 SRAM APB2 GPIOC USART1 SPI1 TIM1 ADC2 ADC1 GPIOE GPIOD GPIOB GPIOA EXTI A...

Page 49: ...APB bridges provide full synchronous connections between the AHB and the 2 APB buses APB1 is limited to 36 MHz APB2 operates at full speed up to 72 MHz depending on the device Refer to Table 3 on page 50 for the address mapping of the peripherals connected to each bridge After each device reset all peripheral clocks are disabled except for the SRAM and FLITF Before using a peripheral you have to e...

Page 50: ...003 FFFF USB OTG FS Section 28 16 6 on page 886 0x4003 0000 0x4FFF FFFF Reserved 0x4002 8000 0x4002 9FFF Ethernet Section 29 8 5 on page 1042 0x4002 3400 0x4002 7FFF Reserved 0x4002 3000 0x4002 33FF CRC Section 4 4 4 on page 64 0x4002 2000 0x4002 23FF Flash memory interface 0x4002 1400 0x4002 1FFF Reserved 0x4002 1000 0x4002 13FF Reset and clock control RCC Section 7 3 11 on page 119 0x4002 0800 0...

Page 51: ...2FFF TIM1 timer Section 14 4 21 on page 344 0x4001 2800 0x4001 2BFF ADC2 Section 11 12 15 on page 241 0x4001 2400 0x4001 27FF ADC1 Section 11 12 15 on page 241 0x4001 2000 0x4001 23FF GPIO Port G Section 9 5 on page 187 0x4001 1C00 0x4001 1FFF GPIO Port F Section 9 5 on page 187 0x4001 1800 0x4001 1BFF GPIO Port E Section 9 5 on page 187 0x4001 1400 0x4001 17FF GPIO Port D Section 9 5 on page 187 ...

Page 52: ... 3C00 0x4000 3FFF SPI3 I2S Section 25 5 on page 716 0x4000 3800 0x4000 3BFF SPI2 I2S Section 25 5 on page 716 0x4000 3400 0x4000 37FF Reserved 0x4000 3000 0x4000 33FF Independent watchdog IWDG Section 19 4 5 on page 481 0x4000 2C00 0x4000 2FFF Window watchdog WWDG Section 20 6 4 on page 487 0x4000 2800 0x4000 2BFF RTC Section 18 4 7 on page 475 0x4000 2400 0x4000 27FF Reserved 0x4000 2000 0x4000 2...

Page 53: ...formula shows how to reference each word in the alias region to a corresponding bit in the bit band region The mapping formula is bit_word_addr bit_band_base byte_offset x 32 bit_number 4 where bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit bit_band_base is the starting address of the alias region byte_offset is the number of the byte in the bit b...

Page 54: ...te each for medium density devices see Table 5 up to 64 Kb 64 bits divided into 256 pages of 2 Kbytes each see Table 6 for high density devices up to 32 Kbit 64 bits divided into 128 pages of 2 Kbytes each see Table 7 for connectivity line devices Information block of size 770 64 bits for XL density devices see Table 8 2360 64 bits for connectivity line devices see Table 7 258 64 bits for other de...

Page 55: ...ytes Main memory Page 0 0x0800 0000 0x0800 03FF 1 Kbyte Page 1 0x0800 0400 0x0800 07FF 1 Kbyte Page 2 0x0800 0800 0x0800 0BFF 1 Kbyte Page 3 0x0800 0C00 0x0800 0FFF 1 Kbyte Page 4 0x0800 1000 0x0800 13FF 1 Kbyte Page 127 0x0801 FC00 0x0801 FFFF 1 Kbyte Information block System memory 0x1FFF F000 0x1FFF F7FF 2 Kbytes Option Bytes 0x1FFF F800 0x1FFF F80F 16 Flash memory interface registers FLASH_ACR...

Page 56: ...FF 2 Kbytes Page 255 0x0807 F800 0x0807 FFFF 2 Kbytes Information block System memory 0x1FFF F000 0x1FFF F7FF 2 Kbytes Option Bytes 0x1FFF F800 0x1FFF F80F 16 Flash memory interface registers FLASH_ACR 0x4002 2000 0x4002 2003 4 FLASH_KEYR 0x4002 2004 0x4002 2007 4 FLASH_OPTKEYR 0x4002 2008 0x4002 200B 4 FLASH_SR 0x4002 200C 0x4002 200F 4 FLASH_CR 0x4002 2010 0x4002 2013 4 FLASH_AR 0x4002 2014 0x40...

Page 57: ...FLASH_KEYR 0x4002 2004 0x4002 2007 4 FLASH_OPTKEYR 0x4002 2008 0x4002 200B 4 FLASH_SR 0x4002 200C 0x4002 200F 4 FLASH_CR 0x4002 2010 0x4002 2013 4 FLASH_AR 0x4002 2014 0x4002 2017 4 Reserved 0x4002 2018 0x4002 201B 4 FLASH_OBR 0x4002 201C 0x4002 201F 4 FLASH_WRPR 0x4002 2020 0x4002 2023 4 Table 8 XL density Flash module organization Block Name Base addresses Size bytes Main memory Bank 1 Page 0 0x...

Page 58: ...lock can be replaced with a single read from the Flash memory as the size of the block matches the bandwidth of the Flash memory Thanks to the prefetch buffer faster CPU execution is possible as the CPU fetches one word at a time with the next word readily available in the prefetch buffer Half cycle for power optimization Flash memory interface registers FLASH_ACR 0x4002 2000 0x4002 2003 4 FLASH_K...

Page 59: ...the DCode bus and has priority over ICode instructions The DMA provides one free cycle after each transfer Some instructions can be performed together with DMA transfer Programming and erasing the Flash memory The Flash memory can be programmed 16 bits half words at a time For write and erase operations on the Flash memory write erase the internal RC oscillator HSI must be ON The Flash memory eras...

Page 60: ... 1 0 Reserved PRFTBS PRFTBE HLFCYA LATENCY r rw rw rw rw rw Bits 31 6 Reserved must be kept cleared Bit 5 PRFTBS Prefetch buffer status This bit provides the status of the prefetch buffer 0 Prefetch buffer is disabled 1 Prefetch buffer is enabled Bit 4 PRFTBE Prefetch buffer enable 0 Prefetch is disabled 1 Prefetch is enabled Bit 3 HLFCYA Flash half cycle access enable 0 Half cycle is disabled 1 H...

Page 61: ...have to relocate the vector table in SRAM using the NVIC exception table and offset register For XL density devices when booting from the main Flash memory you have an option to boot from any of two memory banks By default boot from Flash memory bank 1 is selected You can choose to boot from Flash memory bank 2 by clearing the BFB2 bit in the user option bytes When this bit is cleared and the boot...

Page 62: ...ction The CRC cyclic redundancy check calculation unit is used to get a CRC code from a 32 bit data word and a fixed generator polynomial Among other applications CRC based techniques are used to verify data transmission or storage integrity In the scope of the EN IEC 60335 1 standard they offer a means of verifying the Flash memory integrity The CRC calculation unit helps compute a signature of t...

Page 63: ...ses The CRC calculator can be reset to FFFF FFFFh with the RESET control bit in the CRC_CR register This operation does not affect the contents of the CRC_IDR register 4 4 CRC registers The CRC calculation unit contains two data registers and a control register 4 4 1 Data register CRC_DR Address offset 0x00 Reset value 0xFFFF FFFF 4 4 2 Independent data register CRC_IDR Address offset 0x04 Reset v...

Page 64: ...the RESET bit in the CRC_CR register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RESET w Bits 31 1 Reserved Bit 0 RESET bit Resets the CRC calculation unit and sets the data register to FFFF FFFFh This bit can only be set it is automatically cleared by hardware Table 10 CRC calculation unit register map and reset values Offset Register 31...

Page 65: ... where the Flash memory density ranges between 256 and 512 Kbytes XL density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers This section applies to the whole STM32F101xx family unless otherwise specified 5 1 Power supplies The device requires a 2...

Page 66: ... To ensure a better accuracy on low voltage inputs and outputs the user can connect a separate external reference voltage on VREF VREF is the highest voltage represented by the full scale value for an analog input ADC or output DAC signal The voltage on VREF can range from 2 4 V to VDDA On 64 pin packages and packages with less pins The VREF and VREF pins are not available they are internally conn...

Page 67: ...t injection it is strongly recommended to connect an external low drop diode between this power supply and the VBAT pin If no external battery is used in the application it is recommended to connect VBAT externally to VDD with a 100 nF external ceramic decoupling capacitor for more details refer to AN2586 When the backup domain is supplied by VDD analog switch connected to VDD the following functi...

Page 68: ...ation starting from down to 2 V The device remains in Reset mode when VDD VDDA is below a specified threshold VPOR PDR without the need for an external reset circuit For more details concerning the power on power down reset threshold refer to the electrical characteristics of the datasheet Figure 5 Power on reset power down reset waveform 5 2 2 Programmable voltage detector PVD You can use the PVD...

Page 69: ...VDD VDDA drops below the PVD threshold and or when VDD VDDA rises above the PVD threshold depending on EXTI line16 rising falling edge configuration As an example the service routine could perform emergency shutdown tasks Figure 6 PVD thresholds VDD VDDA PVD output 100 mV hysteresis PVD threshold ...

Page 70: ...em clocks Gating the clocks to the APB and AHB peripherals when they are unused 5 3 1 Slowing down system clocks In Run mode the speed of the system clocks SYSCLK HCLK PCLK1 PCLK2 can be reduced by programming the prescaler registers These prescalers can also be used to slow down peripherals before entering Sleep mode For more details refer to Section 7 3 2 Clock configuration register RCC_CFGR Ta...

Page 71: ...priority ISR In the Sleep mode all I O pins keep the same state as in the Run mode Refer to Table 12 and Table 13 for details on how to enter Sleep mode Exiting Sleep mode If the WFI instruction is used to enter Sleep mode any peripheral interrupt acknowledged by the nested vectored interrupt controller NVIC can wake up the device from Sleep mode If the WFE instruction is used to enter Sleep mode ...

Page 72: ...going The Stop mode entry is delayed until the APB access is finished In Stop mode the following features can be selected by programming individual control bits Independent watchdog IWDG the IWDG is started by writing to its Key register or by hardware option Once started it cannot be stopped except by a Reset See Section 19 3 IWDG functional description in Section 19 Independent watchdog IWDG Tab...

Page 73: ...e Standby mode allows to achieve the lowest power consumption It is based on the Cortex M3 deepsleep mode with the voltage regulator disabled The 1 8 V domain is consequently powered off The PLL the HSI oscillator and the HSE oscillator are also switched off SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry see Figure 4 Table 14 Stop mode Stop mode...

Page 74: ... reset a rising edge on the WKUP pin or the rising edge of an RTC alarm occurs see Figure 179 RTC simplified block diagram All registers are reset after wakeup from Standby except for Power control status register PWR_CSR After waking up from Standby mode program execution restarts in the same way as after a Reset boot pins sampling vector reset is fetched etc The SBF status flag in the Power cont...

Page 75: ... control register RCC_BDCR Low power 32 768 kHz external crystal oscillator LSE OSC This clock source provides a precise time base with very low power consumption less than 1µA added consumption in typical conditions Low power internal RC Oscillator LSI RC This clock source has the advantage of saving the cost of the 32 768 kHz crystal This internal RC Oscillator is designed to add minimum power c...

Page 76: ...e electrical characteristics of the datasheet for more details Bit 4 PVDE Power voltage detector enable This bit is set and cleared by software 0 PVD disabled 1 PVD enabled Bit 3 CSBF Clear standby flag This bit is always read as 0 0 No effect 1 Clear the SBF Standby Flag write Bit 2 CWUF Clear wakeup flag This bit is always read as 0 0 No effect 1 Clear the WUF Wakeup Flag after 2 System clock cy...

Page 77: ... Bit 2 PVDO PVD output This bit is set and cleared by hardware It is valid only if PVD is enabled by the PVDE bit 0 VDD VDDA is higher than the PVD threshold selected with the PLS 2 0 bits 1 VDD VDDA is lower than the PVD threshold selected with the PLS 2 0 bits Note The PVD is stopped by Standby mode For this reason this bit is equal to 0 after Standby or reset until the PVDE bit is set Bit 1 SBF...

Page 78: ...page 50 for the register boundary addresses Table 16 PWR register map and reset values Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x000 PWR_CR Reserved DBP PLS 2 0 PVDE CSBF CWUF PDDS LPDS Reset value 0 0 0 0 0 0 0 0 0 0x004 PWR_CSR Reserved EWUP Reserved PVDO SBF WUF Reset value 0 0 0 0 ...

Page 79: ...domain that remains powered on by VBAT when the VDD power is switched off They are not reset when the device wakes up from Standby mode or by a system reset or power reset In addition the BKP control registers are used to manage the Tamper detection feature and RTC calibration After reset access to the Backup registers and RTC is disabled and the Backup domain BKP is protected against possible par...

Page 80: ...dge on the TAMPER pin after TPE was set By setting the TPIE bit in the BKP_CSR register an interrupt is generated when a Tamper detection event occurs After a Tamper event has been detected and cleared the TAMPER pin should be disabled and then re enabled with TPE before writing to the backup data registers BKP_DRx again This prevents software from writing to the backup data registers BKP_DRx whil...

Page 81: ...2 1 0 Reserved ASOS ASOE CCO CAL 6 0 rw rw rw rw rw rw rw rw rw rw Bits 15 10 Reserved always read as 0 Bit 9 ASOS Alarm or second output selection When the ASOE bit is set the ASOS bit can be used to select whether the signal output on the TAMPER pin is the RTC Second pulse signal or the Alarm pulse signal 0 RTC Alarm pulse output selected 1 RTC Second pulse output selected Note This bit is reset...

Page 82: ...from 0 to 121PPM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TPAL TPE rw rw Bits 15 2 Reserved always read as 0 Bit 1 TPAL TAMPER pin active level 0 A high level on the TAMPER pin resets all data backup registers if TPE bit is set 1 A low level on the TAMPER pin resets all data backup registers if TPE bit is set Bit 0 TPE TAMPER pin enable 0 The TAMPER pin is free for general purpose I O 1 Tamp...

Page 83: ... low power modes 2 This bit is reset only by a system reset and wakeup from Standby mode Bit 1 CTI Clear tamper interrupt This bit is write only and is always read as 0 0 No effect 1 Clear the Tamper interrupt and the TIF Tamper interrupt flag Bit 0 CTE Clear tamper event This bit is write only and is always read as 0 0 No effect 1 Reset the TEF Tamper event flag and the Tamper detector Table 17 B...

Page 84: ... D 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x44 BKP_DR12 Reserved D 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x48 BKP_DR13 Reserved D 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x4C BKP_DR14 Reserved D 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x50 BKP_DR15 Reserved D 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x54 BKP_DR16 Reserved D 15 0 Reset value 0 0 0 0 0 ...

Page 85: ... 0 0 0 0 0 0 0 0x84 BKP_DR28 Reserved D 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x88 BKP_DR29 Reserved D 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x8C BKP_DR30 Reserved D 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x90 BKP_DR31 Reserved D 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x94 BKP_DR32 Reserved D 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x98 BKP_DR33 R...

Page 86: ...0 0 0 0 0 0xB0 BKP_DR39 Reserved D 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xB4 BKP_DR40 Reserved D 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xB8 BKP_DR41 Reserved D 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xBC BKP_DR42 Reserved D 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 17 BKP register map and reset values continued Offset Register 31 30 29 28 27 26 25 24 2...

Page 87: ...e devices reset and clock control RCC on page 120 7 1 Reset There are three types of reset defined as system reset power reset and backup domain reset 7 1 1 System reset A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain see Figure 4 A system reset is generated when one of the following events o...

Page 88: ...rs to their reset values except the Backup domain see Figure 4 These sources act on the NRST pin and it is always kept low during the delay phase The RESET service routine vector is fixed at address 0x0000_0004 in the memory map The system reset signal provided to the device is output on the NRST pin The pulse generator guarantees a minimum reset pulse duration of 20 µs for each reset source exter...

Page 89: ...ck PLL clock The devices have the following two secondary clock sources 40 kHz low speed internal RC LSI RC which drives the independent watchdog and optionally the RTC used for Auto wakeup from Stop Standby mode 32 768 kHz low speed external crystal LSE crystal which optionally drives the real time clock RTCCLK Each clock source can be switched on or off independently when it is not used to optim...

Page 90: ... SysTick Control and Status Register The ADCs are clocked by the clock of the High Speed domain APB2 divided by 2 4 6 or 8 The Flash memory programming interface clock FLITFCLK is always the HSI clock 3 3 Z 3 3 54 3 3 54 3 3 K Z 3 2 Z 3 2 K Z TO NDEPENDENT 7ATCHDOG 7 0 X X X 0 5 3 IGH SPEED EXTERNAL CLOCK SIGNAL 3 OW SPEED EXTERNAL CLOCK SIGNAL 3 OW SPEED INTERNAL CLOCK SIGNAL 3 IGH SPEED INTERNAL...

Page 91: ...more details refer to the ARM Cortex M3 r1p1 Technical Reference Manual TRM 7 2 1 HSE clock The high speed external clock signal HSE can be generated from two possible clock sources HSE external crystal ceramic resonator HSE user external clock The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stab...

Page 92: ... clock or divided by 2 to be used as PLL input The HSI RC oscillator has the advantage of providing a clock source at low cost no external components It also has a faster startup time than the HSE crystal oscillator however even with calibration the frequency is less accurate than an external crystal oscillator or ceramic resonator Calibration RC oscillator frequencies can vary from one chip to an...

Page 93: ... can have a frequency of up to 1 MHz You select this mode by setting the LSEBYP and LSEON bits in the Backup domain control register RCC_BDCR The external clock signal square sinus or triangle with 50 duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left Hi Z See Figure 9 7 2 5 LSI clock The LSI RC acts as an low power clock source that can be kept running in Stop and Sta...

Page 94: ...tivated by software In this case the clock detector is enabled after the HSE oscillator startup delay and disabled when this oscillator is stopped If a failure is detected on the HSE oscillator clock this oscillator is automatically disabled a clock failure event is sent to the break input of the advanced control timers TIM1 and TIM8 and an interrupt is generated to inform the software about the f...

Page 95: ...tor is powered off removing power from the 1 8 V domain The DPB bit disable backup domain write protection in the Power controller register must be set to 1 refer to Section 5 4 1 Power control register PWR_CR 7 2 9 Watchdog clock If the Independent watchdog IWDG is started by either hardware option or software access the LSI oscillator is forced ON and cannot be disabled After the LSI oscillator ...

Page 96: ...e PLL Cleared by hardware when entering Stop or Standby mode This bit can not be reset if the PLL clock is used as system clock or is selected to become the system clock 0 PLL OFF 1 PLL ON Bits 23 20 Reserved always read as 0 Bit 19 CSSON Clock security system enable Set and cleared by software to enable clock detector 0 Clock detector OFF 1 Clock detector ON if external 4 16 MHz oscillator is rea...

Page 97: ...e the frequency of the internal HSI RC The default value is 16 which when added to the HSICAL value should trim the HSI to 8 MHz 1 The trimming step Fhsitrim is around 40 kHz between two consecutive HSICAL steps Bit 2 Reserved always read as 0 Bit 1 HSIRDY Internal high speed clock ready flag Set by hardware to indicate that internal 8 MHz RC oscillator is stable After the HSION bit is cleared HSI...

Page 98: ...rw rw rw rw rw r r rw rw Bits 31 27 Reserved always read as 0 Bits 26 24 MCO Microcontroller clock output Set and cleared by software 0xx No clock 100 System clock SYSCLK selected 101 HSI clock selected 110 HSE clock selected 111 PLL clock divided by 2 selected Note This clock output may have some truncated cycles at startup or during MCO clock source switching When the System Clock is selected to...

Page 99: ...L input clock x 16 Bit 17 PLLXTPRE HSE divider for PLL entry Set and cleared by software to divide HSE before PLL entry This bit can be written only when PLL is disabled 0 HSE clock not divided 1 HSE clock divided by 2 Bit 16 PLLSRC PLL entry clock source Set and cleared by software to select PLL clock source This bit can be written only when PLL is disabled 0 HSI oscillator clock 2 selected as PL...

Page 100: ...01 SYSCLK divided by 128 1110 SYSCLK divided by 256 1111 SYSCLK divided by 512 Note The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB clock Refer to Reading the Flash memory on page 58 section for more details Bits 3 2 SWS System clock switch status Set and cleared by hardware to indicate which clock source is used as system clock 00 HSI oscillator used as syst...

Page 101: ...ity system interrupt clear This bit is set by software to clear the CSSF flag 0 No effect 1 Clear CSSF flag Bits 22 21 Reserved always read as 0 Bit 20 PLLRDYC PLL ready interrupt clear This bit is set by software to clear the PLLRDYF flag 0 No effect 1 PLLRDYF cleared Bit 19 HSERDYC HSE ready interrupt clear This bit is set by software to clear the HSERDYF flag 0 No effect 1 HSERDYF cleared Bit 1...

Page 102: ...0 kHz oscillator stabilization 0 LSI ready interrupt disabled 1 LSI ready interrupt enabled Bit 7 CSSF Clock security system interrupt flag Set by hardware when a failure is detected in the external 4 16 MHz oscillator Cleared by software setting the CSSC bit 0 No clock security interrupt caused by HSE clock failure 1 Clock security interrupt caused by HSE clock failure Bits 6 5 Reserved always re...

Page 103: ... clock ready interrupt caused by the internal RC 40 kHz oscillator 1 Clock ready interrupt caused by the internal RC 40 kHz oscillator 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TIM11 RST TIM10 RST TIM9 RST Reserved rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADC3 RST USART1 RST TIM8 RST SPI1 RST TIM1 RST ADC2 RST ADC1 RST IOPG RST IOPF RST IOPE RST IOPD RST IOPC RST IOPB RST IOPA...

Page 104: ...Bit 11 TIM1RST TIM1 timer reset Set and cleared by software 0 No effect 1 Reset TIM1 timer Bit 10 ADC2RST ADC 2 interface reset Set and cleared by software 0 No effect 1 Reset ADC 2 interface Bit 9 ADC1RST ADC 1 interface reset Set and cleared by software 0 No effect 1 Reset ADC 1 interface Bit 8 IOPGRST IO port G reset Set and cleared by software 0 No effect 1 Reset IO port G Bit 7 IOPFRST IO por...

Page 105: ...are 0 No effect 1 Reset IO port C Bit 3 IOPBRST IO port B reset Set and cleared by software 0 No effect 1 Reset IO port B Bit 2 IOPARST IO port A reset Set and cleared by software 0 No effect 1 Reset IO port A Bit 1 Reserved always read as 0 Bit 0 AFIORST Alternate function IO reset Set and cleared by software 0 No effect 1 Reset Alternate Function ...

Page 106: ...TIM13 RST TIM12 RST TIM7 RST TIM6 RST TIM5 RST TIM4 RST TIM3 RST TIM2 RST rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 30 Reserved always read as 0 Bit 29 DACRST DAC interface reset Set and cleared by software 0 No effect 1 Reset DAC interface Bit 28 PWRRST Power interface reset Set and cleared by software 0 No effect 1 Reset power interface Bit 27 BKPRST Backup interface reset Set and cleared by s...

Page 107: ...T3 Bit 17 USART2RST USART2 reset Set and cleared by software 0 No effect 1 Reset USART2 Bit 16 Reserved always read as 0 Bit 15 SPI3RST SPI3 reset Set and cleared by software 0 No effect 1 Reset SPI3 Bit 14 SPI2RST SPI2 reset Set and cleared by software 0 No effect 1 Reset SPI2 Bits 13 12 Reserved always read as 0 Bit 11 WWDGRST Window watchdog reset Set and cleared by software 0 No effect 1 Reset...

Page 108: ...t Set and cleared by software 0 No effect 1 Reset TIM7 Bit 4 TIM6RST TIM6 timer reset Set and cleared by software 0 No effect 1 Reset TIM6 Bit 3 TIM5RST TIM5 timer reset Set and cleared by software 0 No effect 1 Reset TIM5 Bit 2 TIM4RST TIM4 timer reset Set and cleared by software 0 No effect 1 Reset TIM4 Bit 1 TIM3RST TIM3 timer reset Set and cleared by software 0 No effect 1 Reset TIM3 Bit 0 TIM...

Page 109: ...SMCEN FSMC clock enable Set and cleared by software 0 FSMC clock disabled 1 FSMC clock enabled Bit 7 Reserved always read as 0 Bit 6 CRCEN CRC clock enable Set and cleared by software 0 CRC clock disabled 1 CRC clock enabled Bit 5 Reserved always read as 0 Bit 4 FLITFEN FLITF clock enable Set and cleared by software to disable enable FLITF clock during Sleep mode 0 FLITF clock disabled during Slee...

Page 110: ...ared by software 0 TIM10 timer clock disabled 1 TIM10 timer clock enabled Bit 19 TIM9EN TIM9 timer clock enable Set and cleared by software 0 TIM9 timer clock disabled 1 TIM9 timer clock enabled Bits 18 16 Reserved always read as 0 Bit 15 ADC3EN ADC3 interface clock enable Set and cleared by software 0 ADC3 interface clock disabled 1 ADC3 interface clock enabled Bit 14 USART1EN USART1 clock enable...

Page 111: ...ftware 0 IO port F clock disabled 1 IO port F clock enabled Bit 6 IOPEEN IO port E clock enable Set and cleared by software 0 IO port E clock disabled 1 IO port E clock enabled Bit 5 IOPDEN IO port D clock enable Set and cleared by software 0 IO port D clock disabled 1 IO port D clock enabled Bit 4 IOPCEN IO port C clock enable Set and cleared by software 0 IO port C clock disabled 1 IO port C clo...

Page 112: ...EN Reserved TIM14 EN TIM13 EN TIM12 EN TIM7 EN TIM6 EN TIM5 EN TIM4 EN TIM3 EN TIM2 EN rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 30 Reserved always read as 0 Bit 29 DACEN DAC interface clock enable Set and cleared by software 0 DAC interface clock disabled 1 DAC interface clock enable Bit 28 PWREN Power interface clock enable Set and cleared by software 0 Power interface clock disabled 1 Power i...

Page 113: ... enable Set and cleared by software 0 USART2 clock disabled 1 USART2 clock enabled Bits 16 Reserved always read as 0 Bit 15 SPI3EN SPI 3 clock enable Set and cleared by software 0 SPI 3 clock disabled 1 SPI 3 clock enabled Bit 14 SPI2EN SPI2 clock enable Set and cleared by software 0 SPI2 clock disabled 1 SPI2 clock enabled Bits 13 12 Reserved always read as 0 Bit 11 WWDGEN Window watchdog clock e...

Page 114: ...N TIM6 timer clock enable Set and cleared by software 0 TIM6 clock disabled 1 TIM6 clock enabled Bit 3 TIM5EN TIM5 timer clock enable Set and cleared by software 0 TIM5 clock disabled 1 TIM5 clock enabled Bit 2 TIM4EN TIM4 timer clock enable Set and cleared by software 0 TIM4 clock disabled 1 TIM4 clock enabled Bit 1 TIM3EN TIM3 timer clock enable Set and cleared by software 0 TIM3 clock disabled ...

Page 115: ...5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC EN Reserved RTCSEL 1 0 Reserved LSE BYP LSE RDY LSEON rw rw rw rw r rw Bits 31 17 Reserved always read as 0 Bit 16 BDRST Backup domain software reset Set and cleared by software 0 Reset not activated 1 Resets the entire Backup domain Bit 15 RTCEN RTC clock enable Set and cleared by software 0 RTC clock disabled 1 RTC clock enabled Bits 14 10 Reserved always...

Page 116: ... to indicate when the external 32 kHz oscillator is stable After the LSEON bit is cleared LSERDY goes low after 6 external low speed oscillator clock cycles 0 External 32 kHz oscillator not ready 1 External 32 kHz oscillator ready Bit 0 LSEON External low speed oscillator enable Set and cleared by software 0 External 32 kHz oscillator OFF 1 External 32 kHz oscillator ON ...

Page 117: ... power management reset occurred 1 Low power management reset occurred For further information on Low power management reset refer to Low power management reset Bit 30 WWDGRSTF Window watchdog reset flag Set by hardware when a window watchdog reset occurs Cleared by writing to the RMVF bit 0 No window watchdog reset occurred 1 Window watchdog reset occurred Bit 29 IWDGRSTF Independent watchdog res...

Page 118: ...to clear the reset flags 0 No effect 1 Clear the reset flags Bits 23 2 Reserved always read as 0 Bit 1 LSIRDY Internal low speed oscillator ready Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable After the LSION bit is cleared LSIRDY goes low after 3 internal RC 40 kHz oscillator clock cycles 0 Internal RC 40 kHz oscillator not ready 1 Internal RC 40 kHz osci...

Page 119: ...PFRST IOPERST IOPDRST IOPCRST IOPBRST IOPARST Reserved AFIORST Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x010 RCC_APB1RSTR Reserved DACRST PWRRST BKPRST Reserved CANRST Reserved USBRST I2C2RST I2C1RST UART5RST UART4RST USART3RST USART2RST Reserved SPI3RST SPI2RST Reserved WWDGRST Reser ved TIM14RST TIM13RST TIM12RST TM7RST TM6RST TM5RST TIM4RST TIM3RST TIM2RST Reset value 0 0 0 0 0 0 0 0 0 ...

Page 120: ...ss otherwise specified 8 1 Reset There are three types of reset defined as system reset power reset and backup domain reset 8 1 1 System reset A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain see Figure 4 A system reset is generated when one of the following events occurs 1 A low level on the ...

Page 121: ...wer reset A power reset is generated when one of the following events occurs 1 Power on power down reset POR PDR reset 2 When exiting Standby mode A power reset sets all registers to their reset values except the Backup domain see Figure 4 These sources act on the NRST pin and it is always kept low during the delay phase The RESET service routine vector is fixed at address 0x0000_0004 in the memor...

Page 122: ... on if both supplies have previously been powered off 8 2 Clocks Three different clock sources can be used to drive the system clock SYSCLK HSI oscillator clock HSE oscillator clock PLL clock The devices have the following two secondary clock sources 40 kHz low speed internal RC LSI RC which drives the independent watchdog and optionally the RTC used for Auto wakeup from Stop Standby mode 32 768 k...

Page 123: ...endix A Applicative block diagrams in your connectivity line device datasheet PLLMUL PLL2MUL PLL3MUL PLLCLK PLL2CLK PLL3CLK to MCO PREDIV1SCR PREDIV2 x4 x5 x9 x6 5 x8 x9 x14 x16 x20 x8 x9 x14 x16 x20 1 2 3 15 16 1 2 3 15 16 HSE OSC 8 MHz HSI RC 2 HSI HSE SW SYSCLK 128 PREDIV1 PLLSCR CSS LSE OSC LSI RC 2 3 USB prescaler RTCSEL 1 0 LSE LSI IWDGCLK to independent watchdog to RTC RTCCLK OTGFSCLK 48 MH...

Page 124: ...ernal PHY For further information on the Ethernet configuration please refer to Section 29 4 4 MII RMII selection When the Ethernet is used the AHB clock frequency must be at least 25 MHz The RCC feeds the Cortex System Timer SysTick external clock with the AHB clock HCLK divided by 8 The SysTick can work either with this clock or with the Cortex clock HCLK configurable in the SysTick Control and ...

Page 125: ...Clock control register RCC_CR indicates if the high speed external oscillator is stable or not At startup the clock is not released until this bit is set by hardware An interrupt can be generated if enabled in the Clock interrupt register RCC_CIR The HSE crystal can be switched on and off using the HSEON bit in the Clock control register RCC_CR 8 2 2 HSI clock The HSI clock signal is generated fro...

Page 126: ...r Refer to Figure 11 and Clock control register RCC_CR PLL2 and PLL3 are clocked by HSE through a specific configurable divider Refer to Figure 11 and Clock configuration register2 RCC_CFGR2 The configuration of each PLL selection of clock source predivision factor and multiplication factor must be done before enabling the PLL Each PLL should be enabled after its input clock becomes stable ready f...

Page 127: ... IWDG timeout when LSI is used as clock source for these peripherals with an acceptable accuracy This calibration is performed by measuring the LSI clock frequency with respect to TIM5 input clock TIM5CLK According to this measurement done at the precision of the HSE oscillator the software can adjust the programmable 20 bit prescaler of the RTC to get an accurate time base or can compute accurate...

Page 128: ... the HSI oscillator and the disabling of the external HSE oscillator If the HSE oscillator clock is the clock entry of the PLL directly or through PLL2 used as system clock when the failure occurs the PLL is disabled too 8 2 8 RTC clock The RTCCLK clock source can be either the HSE 128 LSE or LSI clocks This is selected by programming the RTCSEL 1 0 bits in the Backup domain control register RCC_B...

Page 129: ...CO 3 0 bits of the Clock configuration register RCC_CFGR 8 3 RCC registers Refer to Section 2 1 on page 46 for a list of abbreviations used in register descriptions 8 3 1 Clock control register RCC_CR Address offset 0x00 Reset value 0x0000 XX83 where X is undefined Access no wait state word half word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PLL3 RDY PLL3 ON PLL2 RDY...

Page 130: ...et and cleared by software to enable clock detector 0 Clock detector OFF 1 Clock detector ON if external 3 25 MHz oscillator is ready Bit 18 HSEBYP External high speed clock bypass Set and cleared by software for bypassing the oscillator with an external clock This bit can be written only if the external 3 25 MHz oscillator is disabled 0 external 3 25 MHz oscillator not bypassed 1 external 3 25 MH...

Page 131: ...lag Set by hardware to indicate that internal 8 MHz RC oscillator is stable After the HSION bit is cleared HSIRDY goes low after 6 internal 8 MHz RC oscillator clock cycles 0 Internal 8 MHz RC oscillator not ready 1 Internal 8 MHz RC oscillator ready Bit 0 HSION Internal high speed clock enable Set and cleared by software Set by hardware to force the internal 8 MHz RC oscillator ON when leaving St...

Page 132: ...L 3 0 PLL multiplication factor These bits are written by software to define the PLL multiplication factor They can be written only when PLL is disabled 000x Reserved 0010 PLL input clock x 4 0011 PLL input clock x 5 0100 PLL input clock x 6 0101 PLL input clock x 7 0110 PLL input clock x 8 0111 PLL input clock x 9 10xx Reserved 1100 Reserved 1101 PLL input clock x 6 5 111x Reserved Caution The PL...

Page 133: ... by 8 111 HCLK divided by 16 Caution Software must configure these bits ensure that the frequency in this domain does not exceed 36 MHz Bits 7 4 HPRE 3 0 AHB prescaler Set and cleared by software to control AHB clock division factor 0xxx SYSCLK not divided 1000 SYSCLK divided by 2 1001 SYSCLK divided by 4 1010 SYSCLK divided by 8 1011 SYSCLK divided by 16 1100 SYSCLK divided by 64 1101 SYSCLK divi...

Page 134: ... RDYC LSI RDYC w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res PLL3 RDYIE PLL2 RDYIE PLL RDYIE HSE RDYIE HSI RDYIE LSE RDYIE LSI RDYIE CSSF PLL3 RDYF PLL2 RDYF PLL RDYF HSE RDYF HSI RDYF LSE RDYF LSI RDYF rw rw rw rw rw rw rw r r r r r r r r Bits 31 24 Reserved always read as 0 Bit 23 CSSC Clock security system interrupt clear This bit is set by software to clear the CSSF flag 0 No effec...

Page 135: ...interrupt enabled Bit 12 PLLRDYIE PLL ready interrupt enable Set and cleared by software to enable disable interrupt caused by PLL lock 0 PLL lock interrupt disabled 1 PLL lock interrupt enabled Bit 11 HSERDYIE HSE ready interrupt enable Set and cleared by software to enable disable interrupt caused by the external 3 25 MHz oscillator stabilization 0 HSE ready interrupt disabled 1 HSE ready interr...

Page 136: ... interrupt caused by PLL lock Bit3 HSERDYF HSE ready interrupt flag Set by hardware when External Low Speed clock becomes stable and HSERDYIE is set It is cleared by software setting the HSERDYC bit 0 No clock ready interrupt caused by the external 3 25 MHz oscillator 1 Clock ready interrupt caused by the external 3 25 MHz oscillator Bit 2 HSIRDYF HSI ready interrupt flag Set by hardware when the ...

Page 137: ...read as 0 Bit 14 USART1RST USART1 reset Set and cleared by software 0 No effect 1 Reset USART1 Bit 13 Reserved always read as 0 Bit 12 SPI1RST SPI 1 reset Set and cleared by software 0 No effect 1 Reset SPI 1 Bit 11 TIM1RST TIM1 timer reset Set and cleared by software 0 No effect 1 Reset TIM1 timer Bit 10 ADC2RST ADC 2 interface reset Set and cleared by software 0 No effect 1 Reset ADC 2 interface...

Page 138: ... read as 0 Bit 0 AFIORST Alternate function I O reset Set and cleared by software 0 No effect 1 Reset Alternate Function 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved DAC RST PWR RST BKP RST CAN2 RST CAN1 RST Reserved I2C2 RST I2C1 RST UART 5 RST UART 4 RST USART 3 RST USART 2 RST Res rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPI3 RST SPI2 RST Reserved WWD G...

Page 139: ...0 No effect 1 Reset I2C 2 Bit 21 I2C1RST I2C1 reset Set and cleared by software 0 No effect 1 Reset I2C 1 Bit 20 UART5RST USART 5 reset Set and cleared by software 0 No effect 1 Reset USART 5 Bit 19 UART4RST USART 4 reset Set and cleared by software 0 No effect 1 Reset USART 4 Bit 18 USART3RST USART 3 reset Set and cleared by software 0 No effect 1 Reset USART 3 Bit 17 USART2RST USART 2 reset Set ...

Page 140: ... 7 reset Set and cleared by software 0 No effect 1 Reset timer 7 Bit 4 TIM6RST Timer 6 reset Set and cleared by software 0 No effect 1 Reset timer 6 Bit 3 TIM5RST Timer 5 reset Set and cleared by software 0 No effect 1 Reset timer 5 Bit 2 TIM4RST Timer 4 reset Set and cleared by software 0 No effect 1 Reset timer 4 Bit 1 TIM3RST Timer 3 reset Set and cleared by software 0 No effect 1 Reset timer 3...

Page 141: ...Note In the RMII mode if this clock is enabled the RMII clock of the MAC is also enabled Bit 15 ETHMACTXEN Ethernet MAC TX clock enable Set and cleared by software 0 Ethernet MAC TX clock disabled 1 Ethernet MAC TX clock enabled Note In the RMII mode if this clock is enabled the RMII clock of the MAC is also enabled Bit 14 ETHMACEN Ethernet MAC clock enable Set and cleared by software Selection of...

Page 142: ... software to disable enable SRAM interface clock during Sleep mode 0 SRAM interface clock disabled during Sleep mode 1 SRAM interface clock enabled during Sleep mode Bit 1 DMA2EN DMA2 clock enable Set and cleared by software 0 DMA2 clock disabled 1 DMA2 clock enabled Bit 0 DMA1EN DMA1 clock enable Set and cleared by software 0 DMA1 clock disabled 1 DMA1 clock enabled 31 30 29 28 27 26 25 24 23 22 ...

Page 143: ...Set and cleared by software 0 I O port E clock disabled 1 I O port E clock enabled Bit 5 IOPDEN I O port D clock enable Set and cleared by software 0 I O port D clock disabled 1 I O port D clock enabled Bit 4 IOPCEN I O port C clock enable Set and cleared by software 0 I O port C clock disabled 1 I O port C clock enabled Bit 3 IOPBEN I O port B clock enable Set and cleared by software 0 I O port B...

Page 144: ...EN Reserved TIM7 EN TIM6 EN TIM5 EN TIM4 EN TIM3 EN TIM2 EN rw rw rw rw rw rw rw rw rw Bits 31 30 Reserved always read as 0 Bit 29 DACEN DAC interface clock enable Set and cleared by software 0 DAC interface clock disabled 1 DAC interface clock enable Bit 28 PWREN Power interface clock enable Set and cleared by software 0 Power interface clock disabled 1 Power interface clock enable Bit 27 BKPEN B...

Page 145: ...ock enable Set and cleared by software 0 USART 2 clock disabled 1 USART 2 clock enabled Bits 16 Reserved always read as 0 Bit 15 SPI3EN SPI 3 clock enable Set and cleared by software 0 SPI 3 clock disabled 1 SPI 3 clock enabled Bit 14 SPI2EN SPI 2 clock enable Set and cleared by software 0 SPI 2 clock disabled 1 SPI 2 clock enabled Bits 13 12 Reserved always read as 0 Bit 11 WWDGEN Window watchdog...

Page 146: ...Reset see Section 8 1 3 Backup domain reset Any internal or external Reset will not have any effect on these bits Bit 3 TIM5EN Timer 5 clock enable Set and cleared by software 0 Timer 5 clock disabled 1 Timer 5 clock enabled Bit 2 TIM4EN Timer 4 clock enable Set and cleared by software 0 Timer 4 clock disabled 1 Timer 4 clock enabled Bit 1 TIM3EN Timer 3 clock enable Set and cleared by software 0 ...

Page 147: ... 11 HSE oscillator clock divided by 128 used as RTC clock Bits 7 3 Reserved always read as 0 Bit 2 LSEBYP External Low Speed oscillator bypass Set and cleared by software to bypass oscillator in debug mode This bit can be written only when the external 32 kHz oscillator is disabled 0 LSE oscillator not bypassed 1 LSE oscillator bypassed Bit 1 LSERDY External Low Speed oscillator ready Set and clea...

Page 148: ...refer to Section Low power management reset Bit 30 WWDGRSTF Window watchdog reset flag Set by hardware when a window watchdog reset occurs It is cleared by writing to the RMVF bit 0 No window watchdog reset occurred 1 Window watchdog reset occurred Bit 29 IWDGRSTF Independent watchdog reset flag Set by hardware when an independent watchdog reset from VDD domain occurs It is cleared by writing to t...

Page 149: ...t is cleared LSIRDY goes low after 3 internal 40 kHz RC oscillator clock cycles 0 Internal RC 40 kHz oscillator not ready 1 Internal RC 40 kHz oscillator ready Bit 0 LSION Internal low speed oscillator enable Set and cleared by software 0 Internal RC 40 kHz oscillator OFF 1 Internal RC 40 kHz oscillator ON 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 150: ...y Bit 17 I2S2SRC I2S2 clock source Set and cleared by software to select I2S2 clock source This bit must be valid before enabling I2S2 clock 0 System clock SYSCLK selected as I2S2 clock entry 1 PLL3 VCO clock selected as I2S2 clock entry Bit 16 PREDIV1SRC PREDIV1 entry clock source Set and cleared by software to select PREDIV1 clock source This bit can be written only when PLL is disabled 0 HSE os...

Page 151: ...EDIV2 division factor Set and cleared by software to select PREDIV2 division factor These bits can be written only when both PLL2 and PLL3 are disabled 0000 PREDIV2 input clock not divided 0001 PREDIV2 input clock divided by 2 0010 PREDIV2 input clock divided by 3 0011 PREDIV2 input clock divided by 4 0100 PREDIV2 input clock divided by 5 0101 PREDIV2 input clock divided by 6 0110 PREDIV2 input cl...

Page 152: ... RCC register map and reset values Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x000 RCC_CR Reser ved PLL3 RDY PLL3 ON PLL2 RDY PLL2 ON PLL RDY PLLON Reserved CSSON HSEBYP HSERDY HSEON HSICAL 7 0 HSITRIM 4 0 Reserved HSIRDY HSION Reset value 0 0 0 0 0 0 0 0 0 0 x x x x x x x x 1 0 0 0 0 1 1 0x004 RCC_CFGR Reserved MCO 3 0 Reserved OTGFSPRE ...

Page 153: ...RT4EN USART3EN USART2EN Reserved SPI3EN SPI2EN Reserved WWDGEN Reserved TIM7EN TIM6EN TIM5EN TIM4EN TIM3EN TIM2EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x020 RCC_BDCR Reserved BDRST RTCEN Reserved RTC SEL 1 0 Reserved LSEBYP LSERDY LSEON Reset value 0 0 0 0 0 0 0 0x024 RCC_CSR LPWRSTF WWDGRSTF IWDGRSTF SFTRSTF PORRSTF PINRSTF Reserved RMVF Reserved LSIRDY LSION Reset value 0 0 0 0 1 ...

Page 154: ...wise specified 9 1 GPIO functional description Each of the general purpose I O ports has two 32 bit configuration registers GPIOx_CRL GPIOx_CRH two 32 bit data registers GPIOx_IDR GPIOx_ODR a 32 bit set reset register GPIOx_BSRR a 16 bit reset register GPIOx_BRR and a 32 bit locking register GPIOx_LCKR Subject to the specific hardware characteristics of each I O port listed in the datasheet each p...

Page 155: ...chip peripheral To on chip peripheral Output control Analog Input on off on off I O pin VDD VDD VSS VSS TTL Schmitt trigger VSS VDD Protection diode Protection diode on off Input driver Output driver P MOS N MOS Read Bit set reset registers Write ai14781 Alternate Function Output Alternate Function Input Push pull open drain or disabled Input data register Output data register Read write From on c...

Page 156: ...clock cycle All GPIO pins have an internal weak pull up and weak pull down which can be activated or not when configured as input 9 1 2 Atomic bit set or reset There is no need for the software to disable interrupts when programming the GPIOx_ODR at bit level it is possible to modify only one or several bits in a single atomic APB2 write access This is achieved by programming to 1 the Bit Set Rese...

Page 157: ...be driven by the software using the GPIO controller For alternate function outputs the port must be configured in Alternate Function Output mode Push Pull or Open Drain For bidirectional Alternate Functions the port bit must be configured in Alternate Function Output mode Push Pull or Open Drain In this case the input driver is configured in input floating mode If you configure a port bit as Alter...

Page 158: ...Output configuration When the I O Port is programmed as Output The Output Buffer is enabled Open Drain Mode A 0 in the Output register activates the N MOS while a 1 in the Output register leaves the port in Hi Z the P MOS is never activated Push Pull Mode A 0 in the Output register activates the N MOS while a 1 in the Output register activates the P MOS The Schmitt Trigger Input is activated The w...

Page 159: ...rs are disabled The data present on the I O pin is sampled into the Input Data Register every APB2 clock cycle A read access to the Input Data Register gets the I O state in open drain mode A read access to the Output Data register gets the last written value in Push Pull mode The Figure 17 on page 160 shows the Alternate Function Configuration of the I O Port bit Also refer to Section 9 4 AFIO re...

Page 160: ... O pin The output of the Schmitt Trigger is forced to a constant value 0 The weak pull up and pull down resistors are disabled Read access to the Input Data Register gets the value 0 The Figure 18 on page 161 shows the high impedance analog configuration of the I O Port bit Alternate Function Output Alternate Function Input push pull or open drain From on chip peripheral To on chip peripheral Outp...

Page 161: ... TIM8 TIM1 8 pinout Configuration GPIO configuration TIM1 8_CHx Input capture channel x Input floating Output compare channel x Alternate function push pull TIM1 8_CHxN Complementary output channel x Alternate function push pull TIM1 8_BKIN Break input Input floating TIM1 8_ETR External trigger timer input Input floating Table 23 General purpose timers TIM2 3 4 5 TIM2 3 4 5 pinout Configuration GP...

Page 162: ...data wire slave Not used Can be used as a GPIO SPIx_MISO Full duplex master Input floating Input pull up Full duplex slave Alternate function push pull Simplex bidirectional data wire master Not used Can be used as a GPIO Simplex bidirectional data wire slave Alternate function push pull SPIx_NSS Hardware master slave Input floating Input pull up Input pull down Hardware master NSS output enabled ...

Page 163: ...Configuration GPIO configuration OTG_FS_SOF Host AF push pull if used Device AF push pull if used OTG AF push pull if used OTG_FS_VBUS 2 2 For the OTG_FS_VBUS pin PA9 to be used by another shared peripheral or as a general purpose IO the PHY Power down mode has to be active clear bit 16 in the OTG_FS_GCCFG register Host Input floating Device Input floating OTG Input floating OTG_FS_ID Host No need...

Page 164: ...MC_CK Alternate function push pull FSMC_NOE FSMC_NWE Alternate function push pull FSMC_NE 4 1 FSMC_NCE 3 2 FSMC_NCE4_1 FSMC_NCE4_2 Alternate function push pull FSMC_NWAIT FSMC_CD Input floating Input pull up FSMC_NIOS16 FSMC_INTR FSMC_INT 3 2 Input floating FSMC_NL FSMC_NBL 1 0 Alternate function push pull FSMC_NIORD FSMC_NIOWR FSMC_NREG Alternate function push pull Table 33 Other IOs Pins Alterna...

Page 165: ...rw rw rw rw rw rw rw rw Bits 31 30 27 26 23 22 19 18 15 14 11 10 7 6 3 2 CNFy 1 0 Port x configuration bits y 0 7 These bits are written by software to configure the corresponding I O port Refer to Table 20 Port bit configuration table on page 156 In input mode MODE 1 0 00 00 Analog mode 01 Floating input reset state 10 Input with pull up pull down 11 Reserved In output mode MODE 1 0 00 00 General...

Page 166: ...age 156 In input mode MODE 1 0 00 00 Analog mode 01 Floating input reset state 10 Input with pull up pull down 11 Reserved In output mode MODE 1 0 00 00 General purpose output push pull 01 General purpose output Open drain 10 Alternate function output Push pull 11 Alternate function output Open drain Bits 29 28 25 24 21 20 17 16 13 12 9 8 5 4 1 0 MODEy 1 0 Port x mode bits y 8 15 These bits are wr...

Page 167: ...e accessed in Word mode only Note For atomic bit set reset the ODR bits can be individually set and cleared by writing to the GPIOx_BSRR register x A G 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS...

Page 168: ...ort bit until the next reset Each lock bit freezes the corresponding 4 bits of the control register CRL CRH Address offset 0x18 Reset value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 w w w w w w w w w w w w w w w w Bits 31 16 Reserved Bits 15 0 BRy Port x Reset bit ...

Page 169: ...tions in Section 5 1 2 on page 67 9 3 2 Using OSC_IN OSC_OUT pins as GPIO ports PD0 PD1 The HSE oscillator pins OSC_IN OSC_OUT can be used as general purpose I O PD0 PD1 by programming the PD01_REMAP bit in the AF remap and debug I O configuration register AFIO_MAPR This remap is available only on 36 48 and 64 pin packages PD0 and PD1 are available on 100 pin and 144 pin packages no need for remap...

Page 170: ...6 Table 34 CAN1 alternate function remapping Alternate function 1 1 CAN1_RX and CAN1_TX in connectivity line devices CAN_RX and CAN_TX in other devices with a single CAN interface CAN_REMAP 1 0 00 CAN_REMAP 1 0 10 2 2 Remap not available on 36 pin package CAN_REMAP 1 0 11 3 3 This remapping is available only on 100 pin and 144 pin packages when PD0 and PD1 are not remapped on OSC IN and OSC OUT CA...

Page 171: ...injected conversion alternate function remapping 1 1 Remap available only for high density and XL density devices Alternate function ADC1_ETRGINJ_REMAP 0 ADC1_ETRGINJ_REMAP 1 ADC1 external trigger injected conversion ADC1 external trigger injected conversion is connected to EXTI15 ADC1 external trigger injected conversion is connected to TIM8_CH4 Table 39 ADC1 external trigger regular conversion a...

Page 172: ...igger regular conversion is connected to TIM8_TRGO Table 42 TIM5 alternate function remapping 1 1 Remap available only for high density XL density and connectivity line devices Alternate function TIM5CH4_IREMAP 0 TIM5CH4_IREMAP 1 TIM5_CH4 TIM5 Channel4 is connected to PA3 LSI internal clock is connected to TIM5_CH4 input for calibration purpose Table 43 TIM4 alternate function remapping Alternate ...

Page 173: ...0 00 no remap TIM1_REMAP 1 0 01 partial remap TIM1_REMAP 1 0 11 full remap 1 1 Remap available only for 100 pin and 144 pin packages TIM1_ETR PA12 PE7 TIM1_CH1 PA8 PE9 TIM1_CH2 PA9 PE11 TIM1_CH3 PA10 PE13 TIM1_CH4 PA11 PE14 TIM1_BKIN PB12 2 2 Remap not available on 36 pin package PA6 PE15 TIM1_CH1N PB13 PA7 PE8 TIM1_CH2N PB14 2 PB0 PE10 TIM1_CH3N PB15 2 PB1 PE12 Table 47 TIM9 remapping 1 1 Refer t...

Page 174: ..._CH1 PA6 PF8 Table 51 TIM14 remapping 1 1 Refer to the AF remap and debug I O configuration register Section 9 4 7 AF remap and debug I O configuration register2 AFIO_MAPR2 Alternate function TIM14_REMAP 0 TIM14_REMAP 1 TIM14_CH1 PA7 PF9 Table 52 USART3 remapping Alternate function USART3_REMAP 1 0 00 no remap USART3_REMAP 1 0 01 partial remap 1 1 Remap available only for 64 pin 100 pin and 144 pi...

Page 175: ...nction remapping Refer to AF remap and debug I O configuration register AFIO_MAPR Ethernet is available only in connectivity line devices Table 54 USART1 remapping Alternate function USART1_REMAP 0 USART1_REMAP 1 USART1_TX PA9 PB6 USART1_RX PA10 PB7 Table 55 I2C1 remapping Alternate function I2C1_REMAP 0 I2C1_REMAP 1 1 1 Remap not available on 36 pin package I2C1_SCL PB6 PB8 I2C1_SDA PB7 PB9 Table...

Page 176: ...scriptions Note To read write the AFIO_EVCR AFIO_MAPR and AFIO_EXTICRX registers the AFIO clock should first be enabled Refer to Section 7 3 7 APB2 peripheral clock enable register RCC_APB2ENR The peripheral registers have to be accessed by words 32 bit Table 58 ETH remapping Alternate function ETH_REMAP 0 ETH_REMAP 1 RX_DV CRS_DV PA7 PD8 RXD0 PC4 PD9 RXD1 PC5 PD10 RXD2 PB0 PD11 RXD3 PB1 PD12 ...

Page 177: ...software When set the EVENTOUT Cortex output is connected to the I O selected by the PORT 2 0 and PIN 3 0 bits Bits 6 4 PORT 2 0 Port selection Set and cleared by software Select the port used to output the Cortex EVENTOUT signal Note The EVENTOUT signal output capability is not extended to ports PF and PG 000 PA selected 001 PB selected 010 PC selected 011 PD selected 100 PE selected Bits 3 0 PIN...

Page 178: ...JTCK pin 000 Full SWJ JTAG DP SW DP Reset State 001 Full SWJ JTAG DP SW DP but without NJTRST 010 JTAG DP Disabled and SW DP Enabled 100 JTAG DP Disabled and SW DP Disabled Other combinations no effect Bits 23 21 Reserved Bits 20 ADC2_ETRGREG_REMAP ADC 2 external trigger regular conversion remapping Set and cleared by software This bit controls the trigger input connected to ADC2 external trigger ...

Page 179: ... OSC_IN PD1 remapped on OSC_OUT Bits 14 13 CAN_REMAP 1 0 CAN alternate function remapping These bits are set and cleared by software They control the mapping of alternate functions CAN_RX and CAN_TX in devices with a single CAN interface 00 CAN_RX mapped to PA11 CAN_TX mapped to PA12 01 Not used 10 CAN_RX mapped to PB8 CAN_TX mapped to PB9 not available on 36 pin package 11 CAN_RX mapped to PD0 CA...

Page 180: ...ial remap TX PC10 RX PC11 CK PC12 CTS PB13 RTS PB14 10 not used 11 Full remap TX PD8 RX PD9 CK PD10 CTS PD11 RTS PD12 Bit 3 USART2_REMAP USART2 remapping This bit is set and cleared by software It controls the mapping of USART2 CTS RTS CK TX and RX alternate functions on the GPIO ports 0 No remap CTS PA0 RTS PA1 TX PA2 RX PA3 CK PA4 1 Remap CTS PD3 RTS PD4 TX PD5 RX PD6 CK PD7 Bit 2 USART1_REMAP U...

Page 181: ...ices and is reserved otherwise Bit 28 SPI3_REMAP SPI3 I2S3 remapping This bit is set and cleared by software It controls the mapping of SPI3_NSS I2S3_WS SPI3_SCK I2S3_CK SPI3_MISO SPI3_MOSI I2S3_SD alternate functions on the GPIO ports 0 No remap SPI_NSS I2S3_WS PA15 SPI3_SCK I2S3_CK PB3 SPI3_MISO PB4 SPI3_MOSI I2S3_SD PB5 1 Remap SPI3_NSS I2S3_WS PA4 SPI3_SCK I2S3_CK PC10 SPI3_MISO PC11 SPI3_MOSI...

Page 182: ...nctionality When the HSE oscillator is not used application running on internal 8 MHz RC PD0 and PD1 can be mapped on OSC_IN and OSC_OUT This is available only on 36 48 and 64 pin packages PD0 and PD1 are available on 100 pin and 144 pin packages no need for remapping 0 No remapping of PD0 and PD1 1 PD0 remapped on OSC_IN PD1 remapped on OSC_OUT Bits 14 13 CAN1_REMAP 1 0 CAN1 alternate function re...

Page 183: ...bits are set and cleared by software They control the mapping of USART3 CTS RTS CK TX and RX alternate functions on the GPIO ports 00 No remap TX PB10 RX PB11 CK PB12 CTS PB13 RTS PB14 01 Partial remap TX PC10 RX PC11 CK PC12 CTS PB13 RTS PB14 10 not used 11 Full remap TX PD8 RX PD9 CK PD10 CTS PD11 RTS PD12 Bit 3 USART2_REMAP USART2 remapping This bit is set and cleared by software It controls th...

Page 184: ...x configuration x 0 to 3 These bits are written by software to select the source input for EXTIx external interrupt Refer to Section 10 2 5 External interrupt event line mapping on page 199 0000 PA x pin 0001 PB x pin 0010 PC x pin 0011 PD x pin 0100 PE x pin 0101 PF x pin 0110 PG x pin 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI7 3 0 EXTI6 3...

Page 185: ... Reserved Bits 15 0 EXTIx 3 0 EXTI x configuration x 8 to 11 These bits are written by software to select the source input for EXTIx external interrupt 0000 PA x pin 0001 PB x pin 0010 PC x pin 0011 PD x pin 0100 PE x pin 0101 PF x pin 0110 PG x pin 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI15 3 0 EXTI14 3 0 EXTI13 3 0 EXTI12 3 0 rw rw rw rw...

Page 186: ... and cleared by software It controls the mapping of the TIM14_CH1 alternate function onto the GPIO ports 0 No remap PA7 1 Remap PF9 Bit 8 TIM13_REMAP TIM13 remapping This bit is set and cleared by software It controls the mapping of the TIM13_CH1 alternate function onto the GPIO ports 0 No remap PA6 1 Remap PF8 Bit 7 TIM11_REMAP TIM11 remapping This bit is set and cleared by software It controls t...

Page 187: ...0 0 0 0 0 0x18 GPIOx_LCKR Reserved LCKK LCK 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 60 AFIO register map and reset values Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 AFIO_EVCR Reserved EVOE PORT 2 0 PIN 3 0 Reset value 0 0 0 0 0 0 0 0x04 AFIO_MAPR low medium high and XL density devices Reserved SWJ_CFG 2 SWJ_CFG 1 SWJ_...

Page 188: ... value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x14 AFIO_EXTICR4 Reserved EXTI15 3 0 EXTI14 3 0 EXTI13 3 0 EXTI12 3 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x1C AFIO_MAPR2 Reserved FSMC_NADV TIM14_REMAP TIM13_REMAP TIM11_REMAP TIM10_REMAP TIM9_REMAP Reserved Reset value 0 0 0 0 0 0 Table 60 AFIO register map and reset values continued Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1...

Page 189: ...e sixteen Cortex M3 interrupt lines 16 programmable priority levels 4 bits of interrupt priority are used Low latency exception and interrupt handling Power management control Implementation of System Control Registers The NVIC and the processor core interface are closely coupled which enables low latency interrupt processing and efficient processing of late arriving interrupts All interrupts incl...

Page 190: ...C global interrupt 0x0000_004C 4 11 settable FLASH Flash global interrupt 0x0000_0050 5 12 settable RCC RCC global interrupt 0x0000_0054 6 13 settable EXTI0 EXTI Line0 interrupt 0x0000_0058 7 14 settable EXTI1 EXTI Line1 interrupt 0x0000_005C 8 15 settable EXTI2 EXTI Line2 interrupt 0x0000_0060 9 16 settable EXTI3 EXTI Line3 interrupt 0x0000_0064 10 17 settable EXTI4 EXTI Line4 interrupt 0x0000_00...

Page 191: ...C2_EV I2 C2 event interrupt 0x0000_00C4 34 41 settable I2C2_ER I2 C2 error interrupt 0x0000_00C8 35 42 settable SPI1 SPI1 global interrupt 0x0000_00CC 36 43 settable SPI2 SPI2 global interrupt 0x0000_00D0 37 44 settable USART1 USART1 global interrupt 0x0000_00D4 38 45 settable USART2 USART2 global interrupt 0x0000_00D8 39 46 settable USART3 USART3 global interrupt 0x0000_00DC 40 47 settable EXTI15...

Page 192: ...Go FS global interrupt 0x0000_014C Table 62 Vector table for XL density devices Position Priority Typeof priority Acronym Description Address Reserved 0x0000_0000 3 fixed Reset Reset 0x0000_0004 2 fixed NMI Nonmaskable interrupt The RCC Clock Security System CSS is linked to the NMI vector 0x0000_0008 1 fixed HardFault All class of fault 0x0000_000C 0 settable MemManage Memory management 0x0000_00...

Page 193: ...3 settable DMA1_Channel6 DMA1 Channel6 global interrupt 0x0000_0080 17 24 settable DMA1_Channel7 DMA1 Channel7 global interrupt 0x0000_0084 18 25 settable ADC1_2 ADC1 and ADC2 global interrupt 0x0000_0088 19 26 settable USB_HP_CAN_TX USB high priority or CAN TX interrupts 0x0000_008C 20 27 settable USB_LP_CAN_RX0 USB low priority or CAN RX0 interrupts 0x0000_0090 21 28 settable CAN_RX1 CAN RX1 int...

Page 194: ...and TIM13 global interrupt 0x0000_00F0 45 52 settable TIM8_TRG_COM_TIM14 TIM8 Trigger and Commutation interrupts and TIM14 global interrupt 0x0000_00F4 46 53 settable TIM8_CC TIM8 Capture Compare interrupt 0x0000_00F8 47 54 settable ADC3 ADC3 global interrupt 0x0000_00FC 48 55 settable FSMC FSMC global interrupt 0x0000_0100 49 56 settable SDIO SDIO global interrupt 0x0000_0104 50 57 settable TIM5 ...

Page 195: ...timer 0x0000_003C 0 7 settable WWDG Window watchdog interrupt 0x0000_0040 1 8 settable PVD PVD through EXTI Line detection interrupt 0x0000_0044 2 9 settable TAMPER Tamper interrupt 0x0000_0048 3 10 settable RTC RTC global interrupt 0x0000_004C 4 11 settable FLASH Flash global interrupt 0x0000_0050 5 12 settable RCC RCC global interrupt 0x0000_0054 6 13 settable EXTI0 EXTI Line0 interrupt 0x0000_0...

Page 196: ... 0x0000_00B8 31 38 settable I2C1_EV I2 C1 event interrupt 0x0000_00BC 32 39 settable I2C1_ER I2 C1 error interrupt 0x0000_00C0 33 40 settable I2C2_EV I2 C2 event interrupt 0x0000_00C4 34 41 settable I2C2_ER I2 C2 error interrupt 0x0000_00C8 35 42 settable SPI1 SPI1 global interrupt 0x0000_00CC 36 43 settable SPI2 SPI2 global interrupt 0x0000_00D0 37 44 settable USART1 USART1 global interrupt 0x000...

Page 197: ...electrical characteristics section of the datasheet for details on this parameter 10 2 2 Block diagram The block diagram is shown in Figure 20 47 54 settable ADC3 ADC3 global interrupt 0x0000_00FC 48 55 settable FSMC FSMC global interrupt 0x0000_0100 49 56 settable SDIO SDIO global interrupt 0x0000_0104 50 57 settable TIM5 TIM5 global interrupt 0x0000_0108 51 58 settable SPI3 SPI3 global interrupt...

Page 198: ... wakeup capability To use an external line as a wakeup event refer to Section 10 2 4 Functional description 10 2 4 Functional description To generate the interrupt the interrupt line should be configured and enabled This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a 1 to the corresponding bit in the interrupt mas...

Page 199: ...ble and mask bits that control the NVIC IRQ channel mapped to the External Interrupt Controller EXTI so that an interrupt coming from one of the 20 lines can be correctly acknowledged Hardware event selection To configure the 20 lines as event sources use the following procedure Configure the mask bits of the 20 Event lines EXTI_EMR Configure the Trigger Selection bits of the Event lines EXTI_RTSR...

Page 200: ...al clock enable register RCC_APB2ENR for connectivity line devices The four other EXTI lines are connected as follows EXTI line 16 is connected to the PVD output EXTI line 17 is connected to the RTC Alarm event EXTI line 18 is connected to the USB Wakeup event EXTI line 19 is connected to the Ethernet Wakeup event available only in connectivity line devices EXTI0 PA0 PB0 PC0 PD0 PE0 EXTI0 3 0 bits...

Page 201: ...w rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 20 Reserved must be kept at reset value 0 Bits 19 0 MRx Interrupt Mask on line x 0 Interrupt request from Line x is masked 1 Interrupt request from Line x is not masked Note Bit 19 is used in connectivity line devices only and is reserved otherwise 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved MR19 MR18 MR17 MR16 rw rw rw rw 15 14 1...

Page 202: ...tion 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TR19 TR18 TR17 TR16 rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 20 Reserved must be kept at reset value 0 Bits 19 0 TRx Rising trigger event configuration bit of line x 0 Rising trigger disabled for Event a...

Page 203: ...nabled on this line on the EXTI_IMR and EXTI_EMR an interrupt request is generated This bit is cleared by clearing the corresponding bit of EXTI_PR by writing a 1 into the bit Note Bit 19 used in connectivity line devices and is reserved otherwise 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PR19 PR18 PR17 PR16 rc_w1 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PR15 PR14 PR1...

Page 204: ...ter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 EXTI_IMR Reserved MR 19 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x04 EXTI_EMR Reserved MR 19 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x08 EXTI_RTSR Reserved TR 19 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0C EXTI_FTSR Reserved TR 19 0 Reset value 0 0 0 0 0 0 0 0 ...

Page 205: ...are STM32F105xx and STM32F107xx microcontrollers This Section applies to the whole STM32F10xxx family unless otherwise specified 11 1 ADC introduction The 12 bit ADC is a successive approximation analog to digital converter It has up to 18 multiplexed channels allowing it measure signals from 16 external and two internal sources A D conversion of the various channels can be performed in single con...

Page 206: ...nuous mode Dual mode on devices with 2 ADCs or more ADC conversion time STM32F103xx performance line devices 1 µs at 56 MHz 1 17 µs at 72 MHz STM32F101xx access line devices 1 µs at 28 MHz 1 55 µs at 36 MHz STM32F102xx USB access line devices 1 2 µs at 48 MHz STM32F105xx and STM32F107xx devices 1 µs at 56 MHz 1 17 µs at 72 MHz ADC supply requirement 2 4 V to 3 6 V ADC input range VREF VIN VREF DMA...

Page 207: ... TIM2_CH2 TIM3_CH4 From ADC prescaler 16 bits End of conversion channels Injected channels End of injected conversion JEOC EOCIE AWDIE JEOCIE up to 4 up to 16 Regular data register 4 x 16 bits Injected data registers Regular Start trigger regular group EXTSEL 2 0 bits EXTRIG TIM1_CH1 TIM4_TRGO EXTI_15 TIM1_CH4 TIM2_TRGO TIM2_CH1 TIM3_TRGO Start trigger injected group JEXTSEL 2 0 bits TIM1_TRGO TIM...

Page 208: ...DD and VSS respectively Input analog supply Analog power supply equal to VDD and 2 4 V VDDA 3 6 V VREF Input analog reference negative The lower negative reference voltage for the ADC VREF VSSA VSSA 1 Input analog supply ground Ground for analog power supply equal to VSS ADCx_IN 15 0 Analog signals Up to 21 analog channels 2 2 For full details about the ADC I O pins please refer to the Pinouts and...

Page 209: ...gular group is composed of up to 16 conversions The regular channels and their order in the conversion sequence must be selected in the ADC_SQRx registers The total number of conversions in the regular group must be written in the L 3 0 bits in the ADC_SQR1 register The injected group is composed of up to 4 conversions The injected channels and their order in the conversion sequence must be select...

Page 210: ...t in the ADC_CR2 register while the CONT bit is 1 After each conversion If a regular channel was converted The converted data is stored in the 16 bit ADC_DR register The EOC End Of Conversion flag is set An interrupt is generated if the EOCIE is set If an injected channel was converted The converted data is stored in the 16 bit ADC_DRJ1 register The JEOC End Of Conversion Injected flag is set An i...

Page 211: ...scans all the channels selected in the ADC_SQRx registers for regular channels or in the ADC_JSQR for injected channels A single conversion is performed for each channel of the group After each end of conversion the next channel of the group is converted automatically If the CONT bit is set conversion does not stop at the last selected group channel but continues again from the first selected grou...

Page 212: ... if the sequence length is 28 ADC clock cycles that is two conversions with a 1 5 clock period sampling time the minimum interval between triggers must be 29 ADC clock cycles Auto injection If the JAUTO bit is set then the injected group channels are automatically converted after the regular group channels This can be used to convert a sequence of up to 20 conversions programmed in the ADC_SQRx an...

Page 213: ...e JDISCEN bit in the ADC_CR1 register It can be used to convert the sequence selected in the ADC_JSQR register channel by channel after an external trigger event When an external trigger occurs it starts the next channel conversions selected in the ADC_JSQR registers until all the conversions in the sequence are done The total sequence length is defined by the JL 1 0 bits in the ADC_JSQR register ...

Page 214: ...2 register selects the alignment of data stored after conversion Data can be left or right aligned as shown in Figure 27 and Figure 28 The injected group channels converted data value is decreased by the user defined offset written in the ADC_JOFRx registers so the result can be a negative value The SEXT bit is the extended sign value For regular group channels no offset is subtracted so only twel...

Page 215: ...EXTSEL 2 0 control bits allow the application to select decide which out of 8 possible events can trigger conversion for the regular and injected groups Note When an external trigger is selected for ADC regular or injected conversion only the rising edge of the signal can start the conversion Table 67 External trigger for regular channels for ADC1 and ADC2 Source Type EXTSEL 2 0 TIM1_CC1 event Int...

Page 216: ...ts ADC1_ETRGINJ_REMAP and ADC2_ETRGINJ_REMAP for ADC1 and ADC2 respectively External pin Internal signal from on chip timers 110 JSWSTART Software control bit 111 Table 69 External trigger for regular channels for ADC3 Source Connection type EXTSEL 2 0 TIM3_CC1 event Internal signal from on chip timers 000 TIM2_CC3 event 001 TIM1_CC3 event 010 TIM8_CC1 event 011 TIM8_TRGO event 100 TIM5_CC1 event ...

Page 217: ...are stored in a unique data register it is necessary to use DMA for conversion of more than one regular channel This avoids the loss of data already stored in the ADC_DR register Only the end of conversion of a regular channel generates a DMA request which allows the transfer of its converted data from the ADC_DR register to the destination location selected by the user Note Only ADC1 and ADC3 hav...

Page 218: ...e slave to prevent spurious triggers to start unwanted slave conversion However external triggers must be enabled on both master and slave ADCs The following six possible modes are implemented Injected simultaneous mode Regular simultaneous mode Fast interleaved mode Slow interleaved mode Alternate trigger mode Independent mode It is also possible to use the previous modes combined in the followin...

Page 219: ...C2 regular converted data over the entire 32 bits ADCx_IN0 ADCx_IN1 ADCx_IN15 GPIO Ports Address data bus EXTI_11 EXTI_15 Injected data registers 4 x 16 bits Regular channels Injected channels ADC2 Slave 12 bits Injected data registers 4 x 16 bits Regular channels injected channels ADC1 Master Dual mode internal triggers Start trigger mux regular group injected group Start trigger mux control Temp...

Page 220: ...aneous mode on 4 channels 11 9 2 Regular simultaneous mode This mode is performed on a regular channel group The source of the external trigger comes from the regular group mux of ADC1 selected by the EXTSEL 2 0 bits in the ADC1_CR2 register A simultaneous trigger is provided to the ADC2 Note Do not convert the same channel on the two ADCs no overlapping sampling times for the two ADCs when conver...

Page 221: ...nd the ADC1 converted data in the lower halfword Note The maximum sampling time allowed is 7 ADCCLK cycles to avoid the overlap between ADC1 and ADC2 sampling phases in the event that they convert the same channel Figure 32 Fast interleaved mode on 1 channel in continuous conversion mode 11 9 4 Slow interleaved mode This mode can be started only on a regular channel group only one channel The sour...

Page 222: ...p The source of external trigger comes from the injected group mux of ADC1 When the 1st trigger occurs all injected group channels in ADC1 are converted When the 2nd trigger arrives all injected group channels in ADC2 are converted and so on A JEOC interrupt if enabled is generated after all injected group channels of ADC1 are converted A JEOC interrupt if enabled is generated after all injected g...

Page 223: ...ure that the interval between triggers is longer than the longest of the 2 sequences Otherwise the ADC with the shortest sequence may restart while the ADC with the longest sequence is completing the previous conversions 11 9 8 Combined regular simultaneous alternate trigger mode It is possible to interrupt regular group simultaneous conversion to start alternate trigger conversion of an injected ...

Page 224: ...d sequence the interleaved conversion is resumed Figure 38 shows the behavior using an example Note When the ADC clock prescaler is set to 4 the interleaved mode does not recover with evenly spaced sampling periods the sampling interval is 8 ADC clock periods followed by 6 ADC clock periods instead of 7 clock periods followed by 7 clock periods Figure 38 Interleaved single channel with injected se...

Page 225: ...e The TSVREFE bit must be set to enable both internal channels ADCx_IN16 temperature sensor and ADCx_IN17 VREFINT conversion The temperature sensor output voltage changes linearly with temperature The offset of this line varies from chip to chip due to process variation up to 45 C from one chip to another The internal temperature sensor is more suited to applications that detect temperature variat...

Page 226: ... time after waking from power down mode before it can output VSENSE at the correct level The ADC also has a startup time after power on so to minimize the delay the ADON and TSVREFE bits should be set at the same time 11 11 ADC interrupts An interrupt can be produced on end of conversion for regular and injected groups and when the analog watchdog status bit is set Separate interrupt enable bits a...

Page 227: ...nversion has started Bit 3 JSTRT Injected channel Start flag This bit is set by hardware when injected channel group conversion starts It is cleared by software 0 No injected group conversion started 1 Injected group conversion has started Bit 2 JEOC Injected channel end of conversion This bit is set by hardware at the end of all injected group channel conversion It is cleared by software 0 Conver...

Page 228: ...20 Reserved must be kept cleared Bits 19 16 DUALMOD 3 0 Dual mode selection These bits are written by software to select the operating mode 0000 Independent mode 0001 Combined regular simultaneous injected simultaneous mode 0010 Combined regular simultaneous alternate trigger mode 0011 Combined injected simultaneous fast interleaved mode 0100 Combined injected simultaneous slow Interleaved mode 01...

Page 229: ...watchdog enabled on all channels 1 Analog watchdog enabled on a single channel Bit 8 SCAN Scan mode This bit is set and cleared by software to enable disable Scan mode In Scan mode the inputs selected through the ADC_SQRx or ADC_JSQRx registers are converted 0 Scan mode disabled 1 Scan mode enabled Note An EOC or JEOC interrupt is generated only on the end of conversion of the last channel if the ...

Page 230: ... 3 2 1 0 JEXTT RIG JEXTSEL 2 0 ALIGN Reserved DMA Reserved RST CAL CAL CONT ADON rw rw rw rw rw Res rw rw rw rw rw Bits 31 24 Reserved must be kept cleared Bit 23 TSVREFE Temperature sensor and VREFINT enable This bit is set and cleared by software to enable disable the temperature sensor and VREFINT channel In devices with dual ADCs this bit is present only in ADC1 0 Temperature sensor and VREFIN...

Page 231: ...r 1 CC1 event 001 Timer 1 CC2 event 010 Timer 1 CC3 event 011 Timer 2 CC2 event 100 Timer 3 TRGO event 101 Timer 4 CC4 event 110 EXTI line 11 TIM8_TRGO event TIM8_TRGO is available only in high density and XL density devices 111 SWSTART For ADC3 the assigned triggers are 000 Timer 3 CC1 event 001 Timer 2 CC3 event 010 Timer 1 CC3 event 011 Timer 8 CC1 event 100 Timer 8 TRGO event 101 Timer 5 CC1 e...

Page 232: ...1 ALIGN Data alignment This bit is set and cleared by software Refer to Figure 27 and Figure 28 0 Right Alignment 1 Left Alignment Bits 10 9 Reserved must be kept cleared Bit 8 DMA Direct memory access mode This bit is set and cleared by software Refer to the DMA controller chapter for more details 0 DMA mode disabled 1 DMA mode enabled Only ADC1 and ADC3 can generate a DMA request Bits 7 4 Reserv...

Page 233: ... holds a value of zero and a 1 is written to it then it wakes up the ADC from Power Down state Conversion starts when this bit holds a value of 1 and a 1 is written to it The application should allow a delay of tSTAB between power up and start of conversion Refer to Figure 23 0 Disable ADC conversion calibration and go to power down mode 1 Enable ADC and to start conversion Note If any other bit i...

Page 234: ...must be kept cleared Bits 23 0 SMPx 2 0 Channel x Sample time selection These bits are written by software to select the sample time individually for each channel During sample cycles channel selection bits must remain unchanged 000 1 5 cycles 001 7 5 cycles 010 13 5 cycles 011 28 5 cycles 100 41 5 cycles 101 55 5 cycles 110 71 5 cycles 111 239 5 cycles Note ADC1 analog Channel16 and Channel 17 ar...

Page 235: ... Channel x Sample time selection These bits are written by software to select the sample time individually for each channel During sample cycles channel selection bits must remain unchanged 000 1 5 cycles 001 7 5 cycles 010 13 5 cycles 011 28 5 cycles 100 41 5 cycles 101 55 5 cycles 110 71 5 cycles 111 239 5 cycles Note ADC3 analog input Channel9 is connected to VSS 31 30 29 28 27 26 25 24 23 22 2...

Page 236: ...0 Reserved HT 11 0 rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 12 Reserved must be kept cleared Bits 11 0 HT 11 0 Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LT 11 0 rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 12 Reserved...

Page 237: ... Reserved must be kept cleared Bits 23 20 L 3 0 Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence 0000 1 conversion 0001 2 conversions 1111 16 conversions Bits 19 15 SQ16 4 0 16th conversion in regular sequence These bits are written by software with the channel number 0 17 assigned as the 16th in...

Page 238: ...8 4 0 SQ7 4 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 30 Reserved must be kept cleared Bits 29 26 SQ12 4 0 12th conversion in regular sequence These bits are written by software with the channel number 0 17 assigned as the 12th in the sequence to be converted Bits 24 20 SQ11 4 0 11th conversion in regular sequence Bits 19 15 SQ10 4 0 10th conversion in regular sequence Bits 14 10 S...

Page 239: ...Q2 4 0 SQ1 4 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 30 Reserved must be kept cleared Bits 29 25 SQ6 4 0 6th conversion in regular sequence These bits are written by software with the channel number 0 17 assigned as the 6th in the sequence to be converted Bits 24 20 SQ5 4 0 5th conversion in regular sequence Bits 19 15 SQ4 4 0 4th conversion in regular sequence Bits 14 10 SQ3 4 0...

Page 240: ...in the sequence to be converted Note Unlike a regular conversion sequence if JL 1 0 length is less than four the channels are converted in a sequence starting from 4 JL Example ADC_JSQR 21 0 10 00011 00011 00111 00010 means that a scan conversion will convert the following channel sequence 7 3 3 not 2 7 3 Bits 14 10 JSQ3 4 0 3rd conversion in injected sequence when JL 1 0 3 Bits 9 5 JSQ2 4 0 2nd c...

Page 241: ... Bits 15 0 DATA 15 0 Regular data These bits are read only They contain the conversion result from the regular channels The data is left or right aligned as shown in Figure 27 and Figure 28 Table 72 ADC register map and reset values Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 ADC_SR Reserved STRT JSTRT JEOC EOC AWD Reset value 0 0 0 0 ...

Page 242: ...regular sequence bits Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x34 ADC_SQR3 Reserved SQ6 4 0 6th conversion in regular sequence bits SQ5 4 0 5th conversion in regular sequence bits SQ4 4 0 4th conversion in regular sequence bits SQ3 4 0 3rd conversion in regular sequence bits SQ2 4 0 2nd conversion in regular sequence bits SQ1 4 0 1st conversion in regular sequence ...

Page 243: ...101xx and STM32F103xx devices only 12 1 DAC introduction The DAC module is a 12 bit voltage output digital to analog converter The DAC can be configured in 8 or 12 bit mode and may be used in conjunction with the DMA controller In 12 bit mode the data could be left or right aligned The DAC has two output channels each with its own converter In dual DAC channel mode conversions could be done indepe...

Page 244: ...able 73 DAC pins Name Signal type Remarks VREF Input analog reference positive The higher positive reference voltage for the DAC 2 4 V VREF VDDA 3 3 V VDDA Input analog supply Analog power supply VSSA Input analog supply ground Ground for analog power supply DAC_OUTx Analog output signal DAC channelx analog output VDDA VSSA VREF DAC_OUTx Control logicx DHRx 12 bit 12 bit LFSRx trianglex DM A reque...

Page 245: ...bled and disabled using the corresponding BOFFx bit in the DAC_CR register 12 3 3 DAC data format Depending on the selected configuration mode the data has to be written in the specified register as described below Single DAC channelx there are three possibilities 8 bit right alignment user has to load data into DAC_DHR8Rx 7 0 bits stored into DHRx 11 4 bits 12 bit left alignment user has to load ...

Page 246: ...registers The DHR1 and DHR2 registers will then be loaded into the DOR1 and DOR2 registers respectively either automatically by software trigger or by an external event trigger Figure 42 Data registers in dual DAC channel mode 12 3 4 DAC conversion The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must be performed by loading the DAC_DHRx register write on DAC_DHR8R...

Page 247: ...output or on the selected external interrupt line 9 the last data stored into the DAC_DHRx register is transferred into the DAC_DORx register The DAC_DORx register is updated three APB1 cycles after the trigger occurs If the software trigger is selected the conversion starts once the SWTRIG bit is set SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the DAC_DHRx register...

Page 248: ...e DMA channel The DAC DMA request is not queued so that if a second external trigger arrives before the acknowledgement of the last request then the new request will not be serviced and no error is reported 12 3 8 Noise generation In order to generate a variable amplitude pseudonoise a Linear Feedback Shift Register is available The DAC noise generation is selected by setting WAVEx 1 0 to 01 The p...

Page 249: ...An internal triangle counter is incremented three APB1 clock cycles after each trigger event The value of this counter is then added to the DAC_DHRx register without overflow and the sum is stored into the DAC_DORx register The triangle counter is incremented while it is less than the maximum amplitude defined by the MAMPx 3 0 bits Once the configured amplitude is reached the counter is decremente...

Page 250: ...ible using the two DAC channels and these dual registers All the conversion modes can nevertheless be obtained using separate DHRx registers if needed All modes are described in the paragraphs below 12 4 1 Independent trigger without wave generation To configure the DAC in this conversion mode the following sequence is required Set the two DAC channel trigger enable bits TEN1 and TEN2 Configure di...

Page 251: ...tting different values in the TSEL1 2 0 and TSEL2 2 0 bits Configure the two DAC channel WAVEx 1 0 bits as 01 and set different LFSR masks values in the MAMP1 3 0 and MAMP2 3 0 bits Load the dual DAC channel data into the desired DHR register DAC_DHR12RD DAC_DHR12LD or DAC_DHR8RD When a DAC channel1 trigger arrives the LFSR1 counter with the mask configured by MAMP1 3 0 is added to the DHR1 regist...

Page 252: ...ter and the sum is transferred into DAC_DOR1 three APB1 clock cycles later The DAC channel1 triangle counter is then updated When a DAC channel2 trigger arrives the DAC channel2 triangle counter with a triangle amplitude configured by MAMP2 3 0 is added to the DHR2 register part and the sum is transferred into DAC_DOR2 three APB1 clock cycles later The DAC channel2 triangle counter is then updated...

Page 253: ...DAC channel WAVEx 1 0 bits as 01 and set different LFSR masks values using the MAMP1 3 0 and MAMP2 3 0 bits Load the dual DAC channel data into the desired DHR register DAC_DHR12RD DAC_DHR12LD or DAC_DHR8RD When a trigger arrives the LFSR1 counter with the mask configured by MAMP1 3 0 is added to the DHR1 register and the sum is transferred into DAC_DOR1 three APB1 clock cycles later The LFSR1 cou...

Page 254: ...litude configured by MAMP1 3 0 is added to the DHR1 register and the sum is transferred into DAC_DOR1 three APB1 clock cycles later Then the DAC channel1 triangle counter is updated At the same time the DAC channel2 triangle counter with a triangle amplitude configured by MAMP2 3 0 is added to the DHR2 register and the sum is transferred into DAC_DOR2 three APB1 clock cycles later Then the DAC cha...

Page 255: ...nabled Note only used if bit TEN2 1 DAC channel2 trigger enabled Bits 21 19 TSEL2 2 0 DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 000 Timer 6 TRGO event 001 Timer 3 TRGO event in connectivity line devices Timer 8 TRGO in high density and XL density devices 010 Timer 7 TRGO event 011 Timer 5 TRGO event 100 Timer 2 TRGO event 101 Timer 4 TRGO even...

Page 256: ...11 Unmask bits 11 0 of LFSR Triangle Amplitude equal to 4095 Bits 7 6 WAVE1 1 0 DAC channel1 noise triangle wave generation enable These bits are set reset by software 00 wave generation disabled 01 Noise wave generation enabled 1x Triangle wave generation enabled Note only used if bit TEN1 1 DAC channel1 trigger enabled Bits 5 3 TSEL1 2 0 DAC channel1 trigger selection These bits select the exter...

Page 257: ...23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SWTRI G2 SWTRI G1 w w Bits 31 2 Reserved Bit 1 SWTRIG2 DAC channel2 software trigger This bit is set and cleared by software to enable disable the software trigger 0 Software trigger disabled 1 Software trigger enabled Note This bit is reset by hardware one APB1 clock cycle later once the DAC_DHR2 register value is loa...

Page 258: ...31 12 Reserved Bit 11 0 DACC1DHR 11 0 DAC channel1 12 bit right aligned data These bits are written by software which specify 12 bit data for DAC channel1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DACC1DHR 11 0 Reserved rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 16 Reserved Bit 15 4 DACC1DHR 11 0 DAC channel1 12 bit left aligned data These bits...

Page 259: ...1 12 Reserved Bits 11 0 DACC2DHR 11 0 DAC channel2 12 bit right aligned data These bits are written by software which specify 12 bit data for DAC channel2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DACC2DHR 11 0 Reserved rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 16 Reserved Bits 15 4 DACC2DHR 11 0 DAC channel2 12 bit left aligned data These bit...

Page 260: ...aligned data These bits are written by software which specify 12 bit data for DAC channel2 Bits 15 12 Reserved Bits 11 0 DACC1DHR 11 0 DAC channel1 12 bit right aligned data These bits are written by software which specify 12 bit data for DAC channel1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DACC2DHR 11 0 Reserved rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DAC...

Page 261: ...l2 8 bit right aligned data These bits are written by software which specify 8 bit data for DAC channel2 Bits 7 0 DACC1DHR 7 0 DAC channel1 8 bit right aligned data These bits are written by software which specify 8 bit data for DAC channel1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DACC1DOR 11 0 r r r r r r r r r r r r Bits 31 12 Reser...

Page 262: ...0 0 0 0 0 0 0 0 0 0x0C DAC_DHR12L 1 Reserved DACC1DHR 11 0 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0x10 DAC_DHR8R1 Reserved DACC1DHR 7 0 Reset value 0 0 0 0 0 0 0 0 0x14 DAC_DHR12R 2 Reserved DACC2DHR 11 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0x18 DAC_DHR12L 2 Reserved DACC2DHR 11 0 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0x1C DAC_DHR8R2 Reserved DACC2DHR 7 0 0x20 DAC_DHR12R D Reserved DA...

Page 263: ...o DMA controllers have 12 channels in total 7 for DMA1 and 5 for DMA2 each dedicated to managing memory access requests from one or more peripherals It has an arbiter for handling the priority between DMA requests 13 2 DMA main features 12 independently configurable channels requests 7 for DMA1 and 5 for DMA2 Each of the 12 channels is connected to dedicated hardware DMA requests software trigger ...

Page 264: ...48 Figure 48 DMA block diagram in connectivity line devices 4 H H H RBITER ORTEX 32 3LAVE ODE ODE 3YSTEM REQUEST 0 LASH RIDGE RIDGE H H H RBITER 3LAVE 0 AI B REQUEST US MATRIX 2ESET CLOCK CONTROL 2 0 53 24 30 4 0 0 0 0 84 30 3 4 072 0 5 24 5 24 53 24 53 24 30 3 7 77 24 4 4 4 4 4 53 4 3 THERNET ...

Page 265: ... for the CPU 13 3 1 DMA transactions After an event the peripheral sends a request signal to the DMA Controller The DMA controller serves the request depending on the channel priorities As soon as the DMA Controller accesses the peripheral an Acknowledge is sent to the peripheral by the DMA Controller The peripheral releases its request as soon as it gets the Acknowledge from the DMA Controller On...

Page 266: ...w priority Hardware if 2 requests have the same software priority level the channel with the lowest number will get priority versus the channel with the highest number For example channel 2 gets priority over channel 4 Note In high density XL density and connectivity line devices the DMA1 controller has priority over the DMA2 controller 13 3 3 DMA channels Each channel can handle DMA transfer betw...

Page 267: ...ed in the DMA_CNDTRx register After each peripheral event this value will be decremented 4 Configure the channel priority using the PL 1 0 bits in the DMA_CCRx register 5 Configure data transfer direction circular mode peripheral memory incremented mode peripheral memory data size and interrupt after half and or full transfer in the DMA_CCRx register 6 Activate the channel by setting the ENABLE bi...

Page 268: ...00B2 31 0 0x8 4 READ B4 7 0 0x3 then WRITE 000000B3 31 0 0xC 0x0 000000B0 0x4 000000B1 0x8 000000B2 0xC 000000B3 16 8 4 0x0 B1B0 0x2 B3B2 0x4 B5B4 0x6 B7B6 1 READ B1B0 15 0 0x0 then WRITE B0 7 0 0x0 2 READ B3B2 15 0 0x2 then WRITE B2 7 0 0x1 3 READ B5B4 15 0 0x4 then WRITE B4 7 0 0x2 4 READ B7B6 15 0 0x6 then WRITE B6 7 0 0x3 0x0 B0 0x1 B2 0x2 B4 0x3 B6 16 16 4 0x0 B1B0 0x2 B3B2 0x4 B5B4 0x6 B7B6 ...

Page 269: ...and the peripheral destination size PSIZE to 32 bit 13 3 5 Error management A DMA transfer error can be generated by reading from or writing to a reserved address space When a DMA transfer error occurs during a DMA read or a write access the faulty channel is automatically disabled through a hardware clear of its EN bit in the corresponding Channel configuration register DMA_CCRx The channel s tra...

Page 270: ...ty Low priority Peripheral Channel 2 HW request 2 Channel 1 SW trigger MEM2MEM bit Channel 1 EN bit HW request 1 Channel 4 HW request 4 DMA1 Channel 5 HW request 5 Channel 6 HW REQUEST 6 Channel 7 HW request 7 request ADC1 USART1_TX TIM1_CH4 SPI1_TX USART3_TX USART1_RX TIM1_UP I2C1_TX TIM3_CH1 I2C1_RX TIM2_CH2 SPI1_RX TIM1_CH2 TIM4_CH3 TIM2_CH1 SPI I2S2_TX I2C2_RX USART2_RX TIM3_TRIG TIM1_CH3 USAR...

Page 271: ...he registers of the corresponding peripheral Note The DMA2 controller and its relative requests are available only in high density XL density and connectivity line devices Table 78 Summary of DMA1 requests for each channel Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 ADC1 ADC1 SPI I2 S SPI1_RX SPI1_TX SPI2 I2S2_R X SPI2 I2S2_T X USART USART3_TX USART3_RX USART1...

Page 272: ...TIM5_CH1 TIM6 DAC_Channel1 TIM6_UP DAC_Channel1 Fixed hardware priority Channel 3 internal HW request 3 HIGH PRIORITY LOW PRIORITY Peripheral request signals Channel 2 HW request 2 Channel 1 SW trigger MEM2MEM bit Channel 1 EN bit HW request 1 Channel 4 HW request 4 DMA2 Channel 5 HW request 5 request TIM5_CH2 SDIO TIM5_CH4 TIM8_UP TIM7_UP DAC_Channel2 TIM8_CH3 TIM5_TRIG Channel 2 EN bit Channel 3...

Page 273: ... TEIFx Channel x transfer error flag x 1 7 This bit is set by hardware It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register 0 No transfer error TE on channel x 1 A transfer error TE occurred on channel x Bits 26 22 18 14 10 6 2 HTIFx Channel x half transfer flag x 1 7 This bit is set by hardware It is cleared by software writing 1 to the corresponding bit in the DM...

Page 274: ...its 27 23 19 15 11 7 3 CTEIFx Channel x transfer error clear x 1 7 This bit is set and cleared by software 0 No effect 1 Clears the corresponding TEIF flag in the DMA_ISR register Bits 26 22 18 14 10 6 2 CHTIFx Channel x half transfer clear x 1 7 This bit is set and cleared by software 0 No effect 1 Clears the corresponding HTIF flag in the DMA_ISR register Bits 25 21 17 13 9 5 1 CTCIFx Channel x ...

Page 275: ...mory mode enabled Bits 13 12 PL 1 0 Channel priority level These bits are set and cleared by software 00 Low 01 Medium 10 High 11 Very high Bits 11 10 MSIZE 1 0 Memory size These bits are set and cleared by software 00 8 bits 01 16 bits 10 32 bits 11 Reserved Bits 9 8 PSIZE 1 0 Peripheral size These bits are set and cleared by software 00 8 bits 01 16 bits 10 32 bits 11 Reserved Bit 7 MINC Memory ...

Page 276: ... 1 TC interrupt enabled Bit 0 EN Channel enable This bit is set and cleared by software 0 Channel disabled 1 Channel enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NDT rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 16 Reserved always read as 0 Bits 15 0 NDT 15 0 Number of data to transfer Number of data to be transferred 0 up to 6553...

Page 277: ...w rw rw rw rw rw rw rw rw rw Bits 31 0 PA 31 0 Peripheral address Base address of the peripheral data register from to which the data will be read written When PSIZE is 01 16 bit the PA 0 bit is ignored Access is automatically aligned to a half word address When PSIZE is 10 32 bit PA 1 0 are ignored Access is automatically aligned to a word address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1...

Page 278: ...et value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x014 DMA_CMAR1 MA 31 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x018 Reserved 0x01C DMA_CCR2 Reserved MEM2MEM PL 1 0 M SIZE 1 0 PSIZE 1 0 MINC PINC CIRC DIR TEIE HTIE TCIE EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x020 DMA_CNDTR2 Reserved NDT 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 279: ...M2MEM PL 1 0 M SIZE 1 0 PSIZE 1 0 MINC PINC CIRC DIR TEIE HTIE TCIE EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x070 DMA_CNDTR6 Reserved NDT 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x074 DMA_CPAR6 PA 31 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x078 DMA_CMAR6 MA 31 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x07C Re...

Page 280: ...rs Low and medium density STM32F103xx devices and the STM32F105xx STM32F107xx connectivity line devices contain one advanced control timer TIM1 whereas high density and XL density STM32F103xx devices feature two advance control timers TIM1 and TIM8 14 1 TIM1 TIM8 introduction The advanced control timers TIM1 TIM8 consist of a 16 bit auto reload counter driven by a programmable prescaler It may be ...

Page 281: ...cuit to control the timer with external signals and to interconnect several timers together Repetition counter to update the timer registers only after a given number of cycles of the counter Break input to put the timer s output signals in reset state or in a known state Interrupt DMA generation on the following events Update counter overflow underflow counter initialization by software or intern...

Page 282: ...ector IC2PS IC1PS TI1FP1 output control DTG output control DTG output control Reg event Notes Preload registers transferred to active registers on U event according to control bit interrupt DMA output Input Filter Polarity Selection Edge Detector Prescaler ETRP TGI TRC TRC IC3 IC4 ITR ETRF TRC TI1F_ED Input Filter Edge detector Input Filter Edge detector Input Filter Edge detector CC1I CC2I CC3I C...

Page 283: ...oad preload enable bit ARPE in TIMx_CR1 register The update event is sent when the counter reaches the overflow or underflow when downcounting and if the UDIS bit equals 0 in the TIMx_CR1 register It can also be generated by software The generation of the update event is described in detailed for each configuration The counter is clocked by the prescaler output CK_CNT which is enabled only when th...

Page 284: ...ster TIMx_RCR Else the update event is generated at each counter overflow Setting the UG bit in the TIMx_EGR register by software or by using the slave mode controller also generates an update event The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register This is to avoid updating the shadow registers while writing new values in the CK_PSC 00 CEN Timer clock CK_CN...

Page 285: ... update flag UIF bit in TIMx_SR register is set depending on the URS bit The repetition counter is reloaded with the content of TIMx_RCR register The auto reload shadow register is updated with the preload value TIMx_ARR The buffer of the prescaler is reloaded with the preload value content of the TIMx_PSC register The following figures show some examples of the counter behavior for different cloc...

Page 286: ...not preloaded CK_PSC 0000 0001 CNT_EN Timer clock CK_CNT Counter register Update interrupt flag UIF 0035 0036 Counter overflow Update event UEV Timer clock CK_CNT Counter register 00 1F 20 Update interrupt flag UIF Counter overflow Update event UEV CK_PSC CK_PSC 00 CEN Timer clock CK_CNT Counter register Update interrupt flag UIF Counter overflow Update event UEV 01 02 03 04 05 06 07 32 33 34 35 3...

Page 287: ...s from the current auto reload value whereas the counter of the prescaler restarts from 0 but the prescale rate doesn t change In addition if the URS bit update request selection in TIMx_CR1 register is set setting the UG bit generates an update event UEV but without setting the UIF flag thus no interrupt or DMA request is sent This is to avoid generating both update and capture interrupts when cl...

Page 288: ... by 2 Figure 63 Counter timing diagram internal clock divided by 4 CK_PSC 36 CNT_EN Timer clock CK_CNT Counter register Update interrupt flag UIF Counter underflow cnt_udf Update event UEV 35 34 33 32 31 30 2F 04 03 02 01 00 05 CK_PSC 0001 0036 0035 0034 0033 CNT_EN Timer clock CK_CNT Counter register Update interrupt flag UIF 0002 0000 Counter underflow Update event UEV CK_PSC 0036 0035 CNT_EN Ti...

Page 289: ...aligned mode 1 CMS 01 the counter counts up Center aligned mode 2 CMS 10 the counter counts up and down Center aligned mode 3 CMS 11 In this mode the DIR direction bit in the TIMx_CR1 register cannot be written It is updated by hardware and gives the current direction of the counter The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in...

Page 290: ...and the update flag UIF bit in TIMx_SR register is set depending on the URS bit The repetition counter is reloaded with the content of TIMx_RCR register The buffer of the prescaler is reloaded with the preload value content of the TIMx_PSC register The auto reload active register is updated with the preload value content of the TIMx_ARR register Note that if the update source is a counter overflow...

Page 291: ...verflow Figure 69 Counter timing diagram internal clock divided by N CK_PSC 0002 0000 0001 0002 0003 CNT_EN Timer clock CK_CNT Counter register Update interrupt flag UIF 0003 0001 Counter underflow Update event UEV CK_PSC 0036 0035 CNT_EN Timer clock CK_CNT Counter register Update interrupt flag UIF 0034 0035 Counter overflow Update event UEV Timer clock CK_CNT Counter register 00 20 1F Update int...

Page 292: ...egisters to the shadow registers TIMx_ARR auto reload register TIMx_PSC prescaler register but also TIMx_CCRx capture compare registers in compare mode every N counter overflows or underflows where N is the value in the TIMx_RCR repetition counter register CK_PSC 00 CEN Timer clock CK_CNT Counter register Update interrupt flag UIF Counter underflow Update event UEV 01 02 03 04 05 06 07 05 04 03 02...

Page 293: ...ined as defined by the TIMx_RCR register value refer to Figure 72 When the update event is generated by software by setting the UG bit in TIMx_EGR register or by hardware through the slave mode controller it occurs immediately whatever the value of the repetition counter is and the repetition counter is reloaded with the content of the TIMx_RCR register Figure 72 Update rate examples depending on ...

Page 294: ...ed automatically As soon as the CEN bit is written to 1 the prescaler is clocked by the internal clock CK_INT Figure 73 shows the behavior of the control circuit and the upcounter in normal mode without prescaler Figure 73 Control circuit in normal mode internal clock divided by 1 External clock source mode 1 This mode is selected when SMS 111 in the TIMx_SMCR register The counter can count at eac...

Page 295: ...scaler is not used for triggering so you don t need to configure it When a rising edge occurs on TI2 the counter counts once and the TIF flag is set The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input Figure 75 Control circuit in external clock mode 1 External clock source mode 2 This mode is selected by writing ECE 1 in...

Page 296: ... actual clock of the counter is due to the resynchronization circuit on the ETRP signal Figure 77 Control circuit in external clock mode 2 14 3 5 Capture compare channels Each Capture Compare channel is built around a capture compare register including a shadow register a input stage for capture with digital filter multiplexing and prescaler and an output stage with comparator and output control F...

Page 297: ...or TI1F_Rising TI1F_Falling to the slave mode controller TI1FP1 11 01 TIMx_CCMR1 CC1S 1 0 IC1 TI2FP1 TRC from channel 2 from slave mode controller 10 fDTS TIMx_CCER CC1E IC1PS TI1F 0 1 TI2F_rising TI2F_falling from channel 2 CC1E Capture compare shadow register comparator Capture compare preload register Counter IC1PS CC1S 0 CC1S 1 capture input mode S R read CCR1H read CCR1L read_in_progress capt...

Page 298: ...ng ICx signal When a capture occurs the corresponding CCXIF flag TIMx_SR register is set and an interrupt or a DMA request can be sent if they are enabled If a capture occurs while the CCxIF flag was already high then the over capture flag CCxOF TIMx_SR register is set CCxIF can be cleared by software by writing it to 0 or by reading the captured data stored in the TIMx_CCRx register CCxOF is clea...

Page 299: ...alid transition so the prescaler is disabled write IC1PS bits to 00 in the TIMx_CCMR1 register Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register If needed enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register and or the DMA request by setting the CC1DE bit in the TIMx_DIER register When an input capture occ...

Page 300: ...the captures write the CC1E and CC2E bits to 1 in the TIMx_CCER register Figure 82 PWM input mode timing 1 The PWM input mode can be used only with the TIMx_CH1 TIMx_CH2 signals due to the fact that only TI1FP1 and TI2FP2 are connected to the slave mode controller 14 3 8 Forced output mode In output mode CCxS bits 00 in the TIMx_CCMRx register each output compare signal OCxREF and then OCx OCxN ca...

Page 301: ...ends a DMA request if the corresponding enable bit is set CCxDE bit in the TIMx_DIER register CCDS bit in the TIMx_CR2 register for the DMA request selection The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register In output compare mode the update event UEV has no effect on OCxREF and OCx output The timing resolution is one count o...

Page 302: ...gisters are transferred to the shadow registers only when an update event occurs before starting the counter you have to initialize all the registers by setting the UG bit in the TIMx_EGR register OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register It can be programmed as active high or active low OCx output is enabled by a combination of the CCxE CCxNE MOE OSSI and ...

Page 303: ...CNT TIMx_CCRx else it becomes high If the compare value in TIMx_CCRx is greater than the auto reload value in TIMx_ARR then OCxREF is held at 1 0 PWM is not possible in this mode PWM center aligned mode Center aligned mode is active when the CMS bits in TIMx_CR1 register are different from 00 all the remaining configurations having the same effect on the OCxRef OCx signals The compare flag is set ...

Page 304: ...s not recommended as it can lead to unexpected results In particular The direction is not updated if you write a value in the counter that is greater than the auto reload value TIMx_CNT TIMx_ARR For example if the counter was counting up it continues to count up The direction is updated if you write 0 or write the TIMx_ARR value in the counter but no Update Event UEV is generated The safest way to...

Page 305: ...ak feature on page 337 for more details In particular the dead time is activated when switching to the IDLE state MOE falling down to 0 Dead time insertion is enabled by setting both CCxE and CCxNE bits and the MOE bit if the break circuit is present There is one 10 bit dead time generator for each channel From a reference waveform OCxREF it generates 2 outputs OCx and OCxN If OCx and OCxN are act...

Page 306: ...dified according to additional control bits MOE OSSI and OSSR bits in the TIMx_BDTR register OISx and OISxN bits in the TIMx_CR2 register In any case the OCx and OCxN outputs cannot be set both to active level at a given time Refer to Table 83 Output control bits for complementary OCx and OCxN channels with break feature on page 337 for more details The break source can be either the break input p...

Page 307: ...e CCxE or CCxNE bits is high The break status flag BIF bit in the TIMx_SR register is set An interrupt can be generated if the BIE bit in the TIMx_DIER register is set A DMA request can be sent if the BDE bit in the TIMx_DIER register is set If the AOE bit in the TIMx_BDTR register is set the MOE bit is automatically set again at the next update event UEV This can be used to perform a regulation f...

Page 308: ...0 OISx 0 OCx OCxN not implemented CCxP 1 OISx 1 OCx OCxN not implemented CCxP 1 OISx 0 OCx OCxN CCxE 1 CCxP 0 OISx 0 CCxNE 1 CCxNP 0 OISxN 1 delay delay delay OCx OCxN CCxE 1 CCxP 0 OISx 1 CCxNE 1 CCxNP 1 OISxN 1 delay delay delay OCx OCxN CCxE 1 CCxP 0 OISx 0 CCxNE 0 CCxNP 0 OISxN 1 delay OCx OCxN CCxE 1 CCxP 0 OISx 1 CCxNE 0 CCxNP 0 OISxN 0 OCx OCxN CCxE 1 CCxP 0 CCxNE 0 CCxNP 0 OISx OISxN 0 or ...

Page 309: ...put of a comparator to be used for current handling In this case the ETR must be configured as follow 1 The External Trigger Prescaler should be kept off bits ETPS 1 0 of the TIMx_SMCR register set to 00 2 The external clock mode 2 must be disabled bit ECE of the TIMx_SMCR register set to 0 3 The External Trigger Polarity ETP and the External Trigger Filter ETF can be configured according to the u...

Page 310: ...nt occurs COMIF bit in the TIMx_SR register which can generate an interrupt if the COMIE bit is set in the TIMx_DIER register or a DMA request if the COMDE bit is set in the TIMx_DIER register The Figure 91 describes the behavior of the OCx and OCxN outputs when a COM event occurs in 3 different examples of programmed configurations Figure 91 6 step generation COM example OSSR 1 CCRx OCx OCxN Writ...

Page 311: ...lue is different from the counter initial value Before starting when the timer is waiting for the trigger the configuration must be In upcounting CNT CCRx ARR in particular 0 CCRx In downcounting CNT CCRx Figure 92 Example of one pulse mode For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the ...

Page 312: ... tDELAY min we can get If you want to output a waveform with the minimum delay you can set the OCxFE bit in the TIMx_CCMRx register Then OCxRef and OCx are forced in response to the stimulus without taking in account the comparison Its new level is the same as if a compare match had occurred OCxFE acts only if the channel is configured in PWM1 or PWM2 mode 14 3 16 Encoder interface mode To select ...

Page 313: ...to an external interrupt input and trigger a counter reset The Figure 93 gives an example of counter operation showing count signal generation and direction control It also shows how input jitter is compensated where both edges are selected This might occur if the sensor is positioned near to one of the switching points For this example we assume that the configuration is the following CC1S 01 TIM...

Page 314: ...eration by measuring the period between two encoder events using a second timer configured in capture mode The output of the encoder which indicates the mechanical zero can be used for this purpose Depending on the time between two events the counter can also be read at regular times You can do this by latching the counter value into a third input capture register if available then the capture sig...

Page 315: ...generate a pulse which changes the configuration of the channels of the advanced control timer TIM1 or TIM8 by triggering a COM event The TIM1 timer is used to generate PWM signals to drive the motor To do this the interfacing timer channel must be programmed so that a positive pulse is generated after a programmed delay in output compare or PWM mode This pulse is sent to the advanced control time...

Page 316: ...rupt subroutine generated by the rising edge of OC2REF The Figure 95 describes this example Figure 95 Example of hall sensor interface counter CNT TRGO OC2REF CCR2 OC1 OC1N COM Write CCxE CCxNE TIH1 TIH2 TIH3 CCR1 OC2 OC2N OC3 OC3N C7A3 C7A8 C794 C7A5 C7AB C796 and OCxM for next step Interfacing timer advanced control timers TIM1 TIM8 ai17335 ...

Page 317: ...e input capture source only CC1S 01 in the TIMx_CCMR1 register Write CC1P 0 in TIMx_CCER register to validate the polarity and detect rising edges only Configure the timer in reset mode by writing SMS 100 in TIMx_SMCR register Select TI1 as the input source by writing TS 101 in TIMx_SMCR register Start the counter by writing CEN 1 in the TIMx_CR1 register The counter starts counting on the interna...

Page 318: ...ate the polarity and detect low level only Configure the timer in gated mode by writing SMS 101 in TIMx_SMCR register Select TI1 as the input source by writing TS 101 in TIMx_SMCR register Enable the counter by writing CEN 1 in the TIMx_CR1 register in gated mode the counter doesn t start if CEN 0 whatever is the trigger input level The counter starts counting on the internal clock as long as TI1 ...

Page 319: ...arts counting on the internal clock and the TIF flag is set The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input Figure 98 Control circuit in trigger mode Slave mode external clock mode 2 trigger mode The external clock mode 2 can be used in addition to another slave mode except external clock mode 1 and encoder mode In t...

Page 320: ... The counter then counts on ETR rising edges The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input Figure 99 Control circuit in external clock mode 2 trigger mode 14 3 20 Timer synchronization The TIM timers are linked together internally for timer synchronization or chaining Refer to Section 15 3 15 Timer sync...

Page 321: ...election 00 Edge aligned mode The counter counts up or down depending on the direction bit DIR 01 Center aligned mode 1 The counter counts up and down alternatively Output compare interrupt flags of channels configured in output CCxS 00 in TIMx_CCMRx register are set only when the counter is counting down 10 Center aligned mode 2 The counter counts up and down alternatively Output compare interrup...

Page 322: ...ffered registers are then loaded with their preload values 1 UEV disabled The Update event is not generated shadow registers keep their value ARR PSC CCRx However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller Bit 0 CEN Counter enable 0 Counter disabled 1 Counter enabled Note External clock gated mode and encod...

Page 323: ...een CEN control bit and the trigger input when configured in gated mode When the Counter Enable signal is controlled by the trigger input there is a delay on TRGO except if the master slave mode is selected see the MSM bit description in TIMx_SMCR register 010 Update The update event is selected as trigger output TRGO For instance a master timer can then be used as a prescaler for a slave timer 01...

Page 324: ...e counter is clocked by any active edge on the ETRF signal Note 1 Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF SMS 111 and TS 111 2 It is possible to simultaneously use external clock mode 2 with the following slave modes reset mode gated mode and trigger mode Nevertheless TRGI must not be connected to ETRF in this case TS bits must not be ...

Page 325: ... fSAMPLING fDTS 32 N 6 1111 fSAMPLING fDTS 32 N 8 Bit 7 MSM Master slave mode 0 No action 1 The effect of an event on the trigger input TRGI is delayed to allow a perfect synchronization between the current timer and its slaves through TRGO It is useful if we want to synchronize several timers on a single external event Bits 6 4 TS 2 0 Trigger selection This bit field selects the trigger input to ...

Page 326: ...he counter stops but is not reset as soon as the trigger becomes low Both start and stop of the counter are controlled 110 Trigger Mode The counter starts at a rising edge of the trigger TRGI but it is not reset Only the start of the counter is controlled 111 External Clock Mode 1 Rising edges of the selected trigger TRGI clock the counter Note The gated mode must not be used if TI1F_ED is selecte...

Page 327: ...te DMA request enabled Bit 7 BIE Break interrupt enable 0 Break interrupt disabled 1 Break interrupt enabled Bit 6 TIE Trigger interrupt enable 0 Trigger interrupt disabled 1 Trigger interrupt enabled Bit 5 COMIE COM interrupt enable 0 COM interrupt disabled 1 COM interrupt enabled Bit 4 CC4IE Capture Compare 4 interrupt enable 0 CC4 interrupt disabled 1 CC4 interrupt enabled Bit 3 CC3IE Capture C...

Page 328: ...1 The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set Bit 8 Reserved always read as 0 Bit 7 BIF Break interrupt flag This flag is set by hardware as soon as the break input goes active It can be cleared by software if the break input is not active 0 No break event occurred 1 An active level has been detected on the break input Bit 6 TIF Trigger interrupt flag...

Page 329: ...ure occurred 1 The counter value has been captured in TIMx_CCR1 register An edge has been detected on IC1 which matches the selected polarity Bit 0 UIF Update interrupt flag This bit is set by hardware on an update event It is cleared by software 0 No update occurred 1 Update interrupt pending This bit is set by hardware when the registers are updated At overflow or underflow regarding the repetit...

Page 330: ...1 CC1G Capture Compare 1 generation This bit is set by software in order to generate an event it is automatically cleared by hardware 0 No action 1 A capture compare event is generated on channel 1 If channel CC1 is configured as output CC1IF flag is set Corresponding interrupt or DMA request is sent if enabled If channel CC1 is configured as input The current value of the counter is captured in T...

Page 331: ...OC1 FE CC1S 1 0 IC2F 3 0 IC2PSC 1 0 IC1F 3 0 IC1PSC 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 15 OC2CE Output Compare 2 clear enable Bits 14 12 OC2M 2 0 Output Compare 2 mode Bit 11 OC2PE Output Compare 2 preload enable Bit 10 OC2FE Output Compare 2 fast enable Bits 9 8 CC2S 1 0 Capture Compare 2 selection This bit field defines the direction of the channel input output as well as th...

Page 332: ...rammed LOCK bits in TIMx_BDTR register and CC1S 00 the channel is configured in output 2 In PWM mode 1 or 2 the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from frozen mode to PWM mode Bit 3 OC1PE Output Compare 1 preload enable 0 Preload register on TIMx_CCR1 disabled TIMx_CCR1 can be written at anytime the new value is taken in acco...

Page 333: ... mode is working only if an internal trigger input is selected through TS bit TIMx_SMCR register Note CC2S bits are writable only when the channel is OFF CC2E 0 in TIMx_CCER Bits 7 4 IC1F 3 0 Input capture 1 filter This bit field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1 The digital filter is made of an event counter in which N events are ne...

Page 334: ... 4 preload enable Bit 10 OC4FE Output compare 4 fast enable Bits 9 8 CC4S Capture Compare 4 selection This bit field defines the direction of the channel input output as well as the used input 00 CC4 channel is configured as output 01 CC4 channel is configured as input IC4 is mapped on TI4 10 CC4 channel is configured as input IC4 is mapped on TI3 11 CC4 channel is configured as input IC4 is mappe...

Page 335: ...eld defines the direction of the channel input output as well as the used input 00 CC3 channel is configured as output 01 CC3 channel is configured as input IC3 is mapped on TI3 10 CC3 channel is configured as input IC3 is mapped on TI4 11 CC3 channel is configured as input IC3 is mapped on TRC This mode is working only if an internal trigger input is selected through TS bit TIMx_SMCR register Not...

Page 336: ...on MOE OSSI OSSR OIS1 OIS1N and CC1E bits Bit 1 CC1P Capture Compare 1 output polarity CC1 channel configured as output 0 OC1 active high 1 OC1 active low CC1 channel configured as input This bit selects whether IC1 or IC1 is used for trigger or capture operations 0 non inverted capture is done on a rising edge of IC1 When used as external trigger IC1 is non inverted 1 inverted capture is done on ...

Page 337: ...larity dead time OCx_EN 1 Complementary to OCREF not OCREF Polarity dead time OCxN_EN 1 1 0 0 Output Disabled not driven by the timer OCx CCxP OCx_EN 0 Output Disabled not driven by the timer OCxN CCxNP OCxN_EN 0 1 0 1 Off State output enabled with inactive state OCx CCxP OCx_EN 1 OCxREF Polarity OCxN OCxREF xor CCxNP OCxN_EN 1 1 1 0 OCxREF Polarity OCx OCxREF xor CCxP OCx_EN 1 Off State output en...

Page 338: ...w rw rw rw rw rw rw rw rw Bits 15 0 PSC 15 0 Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC PSC 15 0 1 PSC contains the value to be loaded in the active prescaler register at each update event including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in reset mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARR 15 0 rw...

Page 339: ...ded with REP value only at the repetition update event U_RC any write to the TIMx_RCR register is not taken in account until the next repetition update event It means in PWM mode REP 1 corresponds to the number of PWM periods in edge aligned mode the number of half PWM period in center aligned mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR1 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits...

Page 340: ...ctive capture compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output If channel CC2 is configured as input CCR2 is the counter value transferred by the last input capture 2 event IC2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR3 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 CCR3 15 0 Capture Compare value If channel CC3 is configured as...

Page 341: ...re register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output If channel CC4 is configured as input CCR4 is the counter value transferred by the last input capture 4 event IC4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOE AOE BKP BKE OSSR OSSI LOCK 1 0 DTG 7 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 15 MOE Main output enable This bit is cleared asynchron...

Page 342: ...fied as soon as the LOCK level 2 has been programmed LOCK bits in TIMx_BDTR register Bit 10 OSSI Off state selection for Idle mode This bit is used when MOE 0 on channels configured as outputs See OC OCN enable description for more details Section 14 4 9 TIM1 TIM8 capture compare enable register TIMx_CCER on page 335 0 When inactive OC OCN outputs are disabled OC OCN enable output signal 0 1 When ...

Page 343: ... are 0 to 15875 ns by 125 ns steps 16 us to 31750 ns by 250 ns steps 32 us to 63us by 1 us steps 64 us to 126 us by 2 us steps Note This bit field can not be modified as long as LOCK level 1 2 or 3 has been programmed LOCK bits in TIMx_BDTR register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DBL 4 0 Reserved DBA 4 0 rw rw rw rw rw rw rw rw rw rw Bits 15 13 Reserved always read as 0 Bits 12 8 D...

Page 344: ... registers starting from the following address TIMx_CR1 address DBA According to the configuration of the DMA Data Size several cases may occur If you configure the DMA Data Size in half words 16 bit data will be transferred to each of the 7 registers If you configure the DMA Data Size in bytes the data will aslo be transferred to 7 registers the first register will contain the first MSB byte the ...

Page 345: ...ue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x1C TIMx_CCMR2 Output Compare mode Reserved O24CE OC4M 2 0 OC4PE OC4FE CC4S 1 0 OC3CE OC3M 2 0 OC3PE OC3FE CC3S 1 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_CCMR2 Input Capture mode Reserved IC4F 3 0 IC4 PSC 1 0 CC4S 1 0 IC3F 3 0 IC3 PSC 1 0 CC3S 1 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x20 TIMx_CCER Reserved CC4P CC4E CC3NP CC3NE CC3P CC3E CC2NP...

Page 346: ...Mx_BDTR Reserved MOE AOE BKP BKE OSSR OSSI LOCK 1 0 DT 7 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x48 TIMx_DCR Reserved DBL 4 0 Reserved DBA 4 0 Reset value 0 0 0 0 0 0 0 0 0 0 0x4C TIMx_DMAR Reserved DMAB 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 84 TIM1 TIM8 register map and reset values continued Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 1...

Page 347: ...e Flash memory density ranges between 768 Kbytes and 1 Mbyte Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers This Section applies to the whole STM32F10xxx family unless otherwise specified 15 1 TIM2 to TIM5 introduction The general purpose timers consist of a 16 bit auto reload counter driven by a programmable prescaler They may be used for a variety of purposes includin...

Page 348: ...ion Edge and Center aligned modes One pulse mode output Synchronization circuit to control the timer with external signals and to interconnect several timers Interrupt DMA generation on the following events Update counter overflow underflow counter initialization by software or internal external trigger Trigger event counter start stop initialization or count by internal external trigger Input cap...

Page 349: ...R0 ITR1 ITR2 ITR3 TRGI Encoder Interface Capture compare 3 register U CC3I output control OC1 TRGO OC1REF OC2REF OC3REF U UI Reset enable up down count Capture compare 4 register U CC4I OC4REF Prescaler Prescaler IC4PS IC3PS IC1 IC2 Prescaler Prescaler Input filter edge detector IC2PS IC1PS TI1FP1 OC2 OC3 OC4 Reg event Notes Preload registers transferred to active registers on U event according to...

Page 350: ... CEN in TIMx_CR1 register is set refer also to the slave mode controller description to get more details on counter enabling Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536 It is based on a 16 bit counter controlled through a 16 bit register in the TIMx_PSC ...

Page 351: ...e counter of the prescaler but the prescale rate does not change In addition if the URS bit update request selection in TIMx_CR1 register is set setting the UG bit generates an update event UEV but without setting the UIF flag thus no interrupt or DMA request is sent This is to avoid generating both update and capture interrupts when clearing the counter on the capture event When an update event o...

Page 352: ...ock divided by 4 CK_INT 00 CNT_EN Timer clock CK_CNT Counter register Update interrupt flag UIF Counter overflow Update event UEV 01 02 03 04 05 06 07 32 33 34 35 36 31 CK_INT 0035 0000 0001 0002 0003 CNT_EN Timer clock CK_CNT Counter register Update interrupt flag UIF 0034 0036 Counter overflow Update event UEV 0000 0001 CNT_EN TImer clock CK_CNT Counter register Update interrupt flag UIF 0035 00...

Page 353: ... Update event when ARPE 0 TIMx_ARR not preloaded Timer clock CK_CNT Counter register 00 1F 20 Update interrupt flag UIF Counter overflow Update event UEV CK_INT 00 CNT_EN Timer clock CK_CNT Counter register Update interrupt flag UIF Counter overflow Update event UEV 01 02 03 04 05 06 07 32 33 34 35 36 31 Auto reload register FF 36 Write a new value in TIMx_ARR CK_INT ...

Page 354: ...e In addition if the URS bit update request selection in TIMx_CR1 register is set setting the UG bit generates an update event UEV but without setting the UIF flag thus no interrupt or DMA request is sent This is to avoid generating both update and capture interrupts when clearing the counter on the capture event When an update event occurs all the registers are updated and the update flag UIF bit...

Page 355: ...vided by 4 CK_INT 36 CNT_EN Timer clock CK_CNT Counter register Update interrupt flag UIF Counter underflow cnt_udf Update event UEV 35 34 33 32 31 30 2F 04 03 02 01 00 05 CK_INT 0001 0036 0035 0034 0033 CNT_EN Timer clock CK_CNT Counter register Update interrupt flag UIF 0002 0000 Counter underflow Update event UEV 0036 0035 CNT_EN Timer clock CK_CNT Counter register Update interrupt flag UIF 000...

Page 356: ... aligned mode 1 CMS 01 the counter counts up Center aligned mode 2 CMS 10 the counter counts up and down Center aligned mode 3 CMS 11 In this mode the direction bit DIR from TIMx_CR1 register cannot be written It is updated by hardware and gives the current direction of the counter The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in ...

Page 357: ...ll the registers are updated and the update flag UIF bit in TIMx_SR register is set depending on the URS bit The buffer of the prescaler is reloaded with the preload value content of the TIMx_PSC register The auto reload active register is updated with the preload value content of the TIMx_ARR register Note that if the update source is a counter overflow the auto reload is updated before the count...

Page 358: ...rflow Figure 117 Counter timing diagram internal clock divided by N 0002 0000 0001 0002 0003 CNT_EN TImer clock CK_CNT Counter register Update interrupt flag UIF 0003 0001 Counter underflow Update event UEV CK_INT CK_INT 0036 0035 CNT_EN Timer clock CK_CNT Counter register Update interrupt flag UIF 0034 0035 Counter overflow cnt_ovf Update event UEV Timer clock CK_CNT Counter register 00 20 1F Upd...

Page 359: ...egister Update interrupt flag UIF Counter underflow Update event UEV 01 02 03 04 05 06 07 05 04 03 02 01 06 Auto reload preload register FD 36 Write a new value in TIMx_ARR Auto reload active register FD 36 CK_INT 36 CNT_EN Timer clock CK_CNT Counter register Update interrupt flag UIF Counter overflow Update event UEV 35 34 33 32 31 30 2F F8 F9 FA FB FC F7 Auto reload preload register FD 36 Write ...

Page 360: ...led SMS 000 in the TIMx_SMCR register then the CEN DIR in the TIMx_CR1 register and UG bits in the TIMx_EGR register are actual control bits and can be changed only by software except UG which remains cleared automatically As soon as the CEN bit is written to 1 the prescaler is clocked by the internal clock CK_INT Figure 120 shows the behavior of the control circuit and the upcounter in normal mod...

Page 361: ...riting CC2P 0 in the TIMx_CCER register 4 Configure the timer in external clock mode 1 by writing SMS 111 in the TIMx_SMCR register 5 Select TI2 as the input source by writing TS 110 in the TIMx_SMCR register 6 Enable the counter by writing CEN 1 in the TIMx_CR1 register When a rising edge occurs on TI2 the counter counts once and the TIF flag is set The delay between the rising edge on TI2 and th...

Page 362: ...er 3 Select rising edge detection on the ETR pin by writing ETP 0 in the TIMx_SMCR register 4 Enable external clock mode 2 by writing ECE 1 in the TIMx_SMCR register 5 Enable the counter by writing CEN 1 in the TIMx_CR1 register The counter counts once each 2 ETR rising edges The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the...

Page 363: ... 1 input stage The output stage generates an intermediate waveform which is then used for reference OCxRef active high The polarity acts at the end of the chain Figure 126 Capture compare channel 1 main circuit TI1 0 1 TIMx_CCER CC1P divider 1 2 4 8 ICPS 1 0 TI1F_ED filter ICF 3 0 downcounter TIMx_CCMR1 Edge Detector TI1F_Rising TI1F_Falling to the slave mode controller TI1FP1 11 01 TIMx_CCMR1 CC1...

Page 364: ...ad always access the preload register In capture mode captures are actually done in the shadow register which is copied into the preload register In compare mode the content of the preload register is copied into the shadow register which is compared to the counter Output mode CNT CCR1 CNT CCR1 controller TIMx_CCMR1 OC1M 2 0 oc1ref 0 1 CC1P TIMx_CCER Output Enable Circuit OC1 CC1E TIMx_CCER To the...

Page 365: ...st program a filter duration longer than these 5 clock cycles We can validate a transition on TI1 when 8 consecutive samples with the new level have been detected sampled at fDTS frequency Then write IC1F bits to 0011 in the TIMx_CCMR1 register Select the edge of the active transition on the TI1 channel by writing the CC1P bit to 0 in the TIMx_CCER register rising edge in this case Program the inp...

Page 366: ... for capture in TIMx_CCR1 and counter clear write the CC1P to 0 active on rising edge Select the active input for TIMx_CCR2 write the CC2S bits to 10 in the TIMx_CCMR1 register TI1 selected Select the active polarity for TI1FP2 used for capture in TIMx_CCR2 write the CC2P bit to 1 active on falling edge Select the valid trigger input write the TS bits to 101 in the TIMx_SMCR register TI1FP1 select...

Page 367: ...t pin to a programmable value defined by the output compare mode OCxM bits in the TIMx_CCMRx register and the output polarity CCxP bit in the TIMx_CCER register The output pin can keep its level OCXM 000 be set active OCxM 001 be set inactive OCxM 010 or can toggle OCxM 011 on match Sets a flag in the interrupt status register CCxIF bit in the TIMx_SR register Generates an interrupt if the corresp...

Page 368: ...1 register As the preload registers are transferred to the shadow registers only when an update event occurs before starting the counter you have to initialize all the registers by setting the UG bit in the TIMx_EGR register OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register It can be programmed as active high or active low OCx output is enabled by the CCxE bit in t...

Page 369: ... PWM waveforms ARR 8 Downcounting configuration Downcounting is active when DIR bit in TIMx_CR1 register is high Refer to Downcounting mode on page 354 In PWM mode 1 the reference signal ocxref is low as long as TIMx_CNT TIMx_CCRx else it becomes high If the compare value in TIMx_CCRx is greater than the auto reload value in TIMx_ARR then ocxref is held at 1 0 PWM is not possible in this mode PWM ...

Page 370: ...n configuration is used It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register Moreover the DIR and CMS bits must not be changed at the same time by the software Writing to the counter while running in center aligned mode is not recommended as it can lead to unexpected results In particular The direction is not updated if you write a valu...

Page 371: ...e OPM bit in the TIMx_CR1 register This makes the counter stop automatically at the next update event UEV A pulse can be correctly generated only if the compare value is different from the counter initial value Before starting when the timer is waiting for the trigger the configuration must be In upcounting CNT CCRx ARR in particular 0 CCRx In downcounting CNT CCRx Figure 132 Example of one pulse ...

Page 372: ...n on TIx input set the CEN bit which enables the counter Then the comparison between the counter and the compare value makes the output toggle But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get If you want to output a waveform with the minimum delay you can set the OCxFE bit in the TIMx_CCMRx register Then OCxRef and OCx is forced in resp...

Page 373: ...lses as well as the direction signal Depending on the sequence the counter counts up or down the DIR bit in the TIMx_CR1 register is modified by hardware accordingly The DIR bit is calculated at each transition on any input TI1 or TI2 whatever the counter is counting on TI1 only TI2 only or both TI1 and TI2 Encoder interface mode acts simply as an external clock with direction selection This means...

Page 374: ...his example we assume that the configuration is the following CC1S 01 TIMx_CCMR1 register TI1FP1 mapped on TI1 CC2S 01 TIMx_CCMR2 register TI2FP2 mapped on TI2 CC1P 0 TIMx_CCER register TI1FP1 noninverted TI1FP1 TI1 CC2P 0 TIMx_CCER register TI2FP2 noninverted TI2FP2 TI2 SMS 011 TIMx_SMCR register both inputs are active on both rising and falling edges CEN 1 TIMx_CR1 register Counter is enabled Fi...

Page 375: ...by a Real Time clock 15 3 13 Timer input XOR function The TI1S bit in the TIM1_CR2 register allows the input filter of channel 1 to be connected to the output of a XOR gate combining the three input pins TIMx_CH1 to TIMx_CH3 The XOR output can be used with all the timer input functions such as trigger or input capture An example of this feature used to interface Hall sensors is given in Section 14...

Page 376: ...l circuit in reset mode Slave mode Gated mode The counter can be enabled depending on the level of a selected input In the following example the upcounter counts only when TI1 input is low Configure the channel 1 to detect low levels on TI1 Configure the input filter duration in this example we don t need any filter so we keep IC1F 0000 The capture prescaler is not used for triggering so you don t...

Page 377: ...Mx_SMCR register Select TI2 as the input source by writing TS 110 in TIMx_SMCR register When a rising edge occurs on TI2 the counter starts counting on the internal clock and the TIF flag is set The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input Figure 138 Control circuit in trigger mode Slave mode External Clock mode 2...

Page 378: ...etect rising edge only 3 Configure the timer in trigger mode by writing SMS 110 in TIMx_SMCR register Select TI1 as the input source by writing TS 101 in TIMx_SMCR register A rising edge on TI1 enables the counter and sets the TIF flag The counter then counts on ETR rising edges The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization ...

Page 379: ...1 register Note If OCx is selected on Timer 1 as trigger output MMS 1xx its rising edge is used to clock the counter of timer 2 Using one timer to enable another timer In this example we control the enable of Timer 2 with the output compare 1 of Timer 1 Refer to Figure 140 for connections Timer 2 counts on the divided internal clock only when OC1REF of Timer 1 is high Both counter clock frequencie...

Page 380: ...r 2 stops when Timer 1 is disabled by writing 0 to the CEN bit in the TIM1_CR1 register Configure Timer 1 master mode to send its Output Compare 1 Reference OC1REF signal as trigger output MMS 100 in the TIM1_CR2 register Configure the Timer 1 OC1REF waveform TIM1_CCMR1 register Configure Timer 2 to get the input trigger from Timer 1 TS 000 in the TIM2_SMCR register Configure Timer 2 in gated mode...

Page 381: ...th counter clock frequencies are divided by 3 by the prescaler compared to CK_INT fCK_CNT fCK_INT 3 Configure Timer 1 master mode to send its Update Event UEV as trigger output MMS 010 in the TIM1_CR2 register Configure the Timer 1 period TIM1_ARR registers Configure Timer 2 to get the input trigger from Timer 1 TS 000 in the TIM2_SMCR register Configure Timer 2 in trigger mode SMS 110 in TIM2_SMC...

Page 382: ... 010 in the TIM1_CR2 register then it outputs a periodic signal on each counter overflow Configure the Timer 1 period TIM1_ARR registers Configure Timer 2 to get the input trigger from Timer 1 TS 000 in the TIM2_SMCR register Configure Timer 2 in external clock mode 1 SMS 111 in TIM2_SMCR register Start Timer 2 by writing 1 in the CEN bit TIM2_CR1 register Start Timer 1 by writing 1 in the CEN bit...

Page 383: ...unters starts counting synchronously on the internal clock and both TIF flags are set Note In this example both timers are initialized before starting by setting their respective UG bits Both counters starts from 0 but you can easily insert an offset between them by writing any of the counter registers TIMx_CNT You can see that the master slave mode insert a delay between CNT_EN and CK_PSC on time...

Page 384: ...nts up or down depending on the direction bit DIR 01 Center aligned mode 1 The counter counts up and down alternatively Output compare interrupt flags of channels configured in output CCxS 00 in TIMx_CCMRx register are set only when the counter is counting down 10 Center aligned mode 2 The counter counts up and down alternatively Output compare interrupt flags of channels configured in output CCxS...

Page 385: ...bled The Update UEV event is generated by one of the following events Counter overflow underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values 1 UEV disabled The Update event is not generated shadow registers keep their value ARR PSC CCRx However the counter and the prescaler are reinitialized if the UG bit is se...

Page 386: ...s trigger output TRGO It is useful to start several timers at the same time or to control a window in which a slave timer is enabled The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode When the Counter Enable signal is controlled by the trigger input there is a delay on TRGO except if the master slave mode is selected see...

Page 387: ...TRF in this case TS bits must not be 111 3 If external clock mode 1 and external clock mode 2 are enabled at the same time the external clock input is ETRF Bits 13 12 ETPS External trigger prescaler External trigger signal ETRP frequency must be at most 1 4 of CK_INT frequency A prescaler can be enabled to reduce ETRP frequency It is useful when inputting fast external clocks 00 Prescaler OFF 01 E...

Page 388: ...Control register and Control Register description 000 Slave mode disabled if CEN 1 then the prescaler is clocked directly by the internal clock 001 Encoder mode 1 Counter counts up down on TI2FP2 edge depending on TI1FP1 level 010 Encoder mode 2 Counter counts up down on TI1FP1 edge depending on TI2FP2 level 011 Encoder mode 3 Counter counts up down on both TI1FP1 and TI2FP2 edges depending on the...

Page 389: ...ev 12 389 1096 TIM4 TIM1 TIM2 TIM3 TIM8 TIM5 TIM2 TIM3 TIM4 TIM8 1 When a timer is not present in the product the corresponding trigger ITRx is not available Table 86 TIMx Internal trigger connection 1 Slave TIM ITR0 TS 000 ITR1 TS 001 ITR2 TS 010 ITR3 TS 011 ...

Page 390: ...A request enabled Bit 11 CC3DE Capture Compare 3 DMA request enable 0 CC3 DMA request disabled 1 CC3 DMA request enabled Bit 10 CC2DE Capture Compare 2 DMA request enable 0 CC2 DMA request disabled 1 CC2 DMA request enabled Bit 9 CC1DE Capture Compare 1 DMA request enable 0 CC1 DMA request disabled 1 CC1 DMA request enabled Bit 8 UDE Update DMA request enable 0 Update DMA request disabled 1 Update...

Page 391: ...on Bit 10 CC2OF Capture compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF Capture Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode It is cleared by software by writing it to 0 0 No overcapture has been detected 1 The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set B...

Page 392: ...x_CCR1 register 0 No input capture occurred 1 The counter value has been captured in TIMx_CCR1 register An edge has been detected on IC1 which matches the selected polarity Bit 0 UIF Update interrupt flag This bit is set by hardware on an update event It is cleared by software 0 No update occurred 1 Update interrupt pending This bit is set by hardware when the registers are updated At overflow or ...

Page 393: ...e compare 1 generation This bit is set by software in order to generate an event it is automatically cleared by hardware 0 No action 1 A capture compare event is generated on channel 1 If channel CC1 is configured as output CC1IF flag is set Corresponding interrupt or DMA request is sent if enabled If channel CC1 is configured as input The current value of the counter is captured in TIMx_CCR1 regi...

Page 394: ...FE CC1S 1 0 IC2F 3 0 IC2PSC 1 0 IC1F 3 0 IC1PSC 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 15 OC2CE Output compare 2 clear enable Bits 14 12 OC2M 2 0 Output compare 2 mode Bit 11 OC2PE Output compare 2 preload enable Bit 10 OC2FE Output compare 2 fast enable Bits 9 8 CC2S 1 0 Capture Compare 2 selection This bit field defines the direction of the channel input output as well as the us...

Page 395: ...tput compare 1 preload enable 0 Preload register on TIMx_CCR1 disabled TIMx_CCR1 can be written at anytime the new value is taken in account immediately 1 Preload register on TIMx_CCR1 enabled Read Write operations access the preload register TIMx_CCR1 preload value is loaded in the active register at each update event Note 1 These bits can not be modified as long as LOCK level 3 has been programm...

Page 396: ...NG fDTS 2 N 6 0101 fSAMPLING fDTS 2 N 8 0110 fSAMPLING fDTS 4 N 6 0111 fSAMPLING fDTS 4 N 8 1000 fSAMPLING fDTS 8 N 6 1001 fSAMPLING fDTS 8 N 8 1010 fSAMPLING fDTS 16 N 5 1011 fSAMPLING fDTS 16 N 6 1100 fSAMPLING fDTS 16 N 8 1101 fSAMPLING fDTS 32 N 5 1110 fSAMPLING fDTS 32 N 6 1111 fSAMPLING fDTS 32 N 8 Note In current silicon revision fDTS is replaced in the formula by CK_INT when ICxF 3 0 1 2 o...

Page 397: ...t IC4 is mapped on TI4 10 CC4 channel is configured as input IC4 is mapped on TI3 11 CC4 channel is configured as input IC4 is mapped on TRC This mode is working only if an internal trigger input is selected through TS bit TIMx_SMCR register Note CC4S bits are writable only when the channel is OFF CC4E 0 in TIMx_CCER Bit 7 OC3CE Output compare 3 clear enable Bits 6 4 OC3M Output compare 3 mode Bit...

Page 398: ...are 3 selection This bit field defines the direction of the channel input output as well as the used input 00 CC3 channel is configured as output 01 CC3 channel is configured as input IC3 is mapped on TI3 10 CC3 channel is configured as input IC3 is mapped on TI4 11 CC3 channel is configured as input IC3 is mapped on TRC This mode is working only if an internal trigger input is selected through TS...

Page 399: ...ure operations 0 non inverted capture is done on a rising edge of IC1 When used as external trigger IC1 is non inverted 1 inverted capture is done on a falling edge of IC1 When used as external trigger IC1 is inverted Bit 0 CC1E Capture Compare 1 output enable CC1 channel configured as output 0 Off OC1 is not active 1 On OC1 signal is output on the corresponding output pin CC1 channel configured a...

Page 400: ... counter clock frequency CK_CNT is equal to fCK_PSC PSC 15 0 1 PSC contains the value to be loaded in the active prescaler register at each update event 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARR 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 ARR 15 0 Prescaler value ARR is the value to be loaded in the actual auto reload register Refer to the Section 15 3 1 Time base unit on page 3...

Page 401: ...e capture compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output If channel CC1is configured as input CCR1 is the counter value transferred by the last input capture 1 event IC1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR2 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 CCR2 15 0 Capture Compare 2 value If channel CC2 is configured as out...

Page 402: ...er contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output If channel CC3is configured as input CCR3 is the counter value transferred by the last input capture 3 event IC3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR4 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 CCR4 15 0 Capture Compare value 1 if CC4 channel is configured as output CC4S bits CCR4 is t...

Page 403: ...x_CR2 00010 TIMx_SMCR Example Let us consider the following transfer DBL 7 bytes DBA TIMx_CR1 In this case the transfer is done to from 7 registers starting from the TIMx_CR1 address If DBL 7 bytes and DBA TIM2_CR1 represents the address of the byte to be transferred the address of the transfer should be given by the following equation TIMx_CR1 address DBA DMA index where DMA index DBL In this exa...

Page 404: ...MAR register accesses the register located at the address TIMx_CR1 address DBA DMA index in which TIMx_CR1 address is the address of the control register 1 DBA is the DMA base address configured in the TIMx_DCR register DMA index is the offset automatically controlled by the DMA transfer depending on the length of the transfer DBL in the TIMx_DCR register ...

Page 405: ...CC4OF CC3OF CC2OF CC1OF Reserved TIF Reserved CC4IF CC3IF CC2IF CC1IF UIF Reset value 0 0 0 0 0 0 0 0 0 0 0x14 TIMx_EGR Reserved TG Reserved CC4G CC3G CC2G CC1G UG Reset value 0 0 0 0 0 0 0x18 TIMx_CCMR1 Output Compare mode Reserved OC2CE OC2M 2 0 OC2PE OC2FE CC2 S 1 0 OC1CE OC1M 2 0 OC1PE OC1FE CC1 S 1 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_CCMR1 Input Capture mode Reserved IC2F 3 0 I...

Page 406: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x38 TIMx_CCR2 Reserved CCR2 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x3C TIMx_CCR3 Reserved CCR3 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x40 TIMx_CCR4 Reserved CCR4 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x44 Reserved 0x48 TIMx_DCR Reserved DBL 4 0 Reserve d DBA 4 0 Reset value 0 0 0 0 0 0 0 0 0 0 0x4C TIMx_DMAR Reserved DMAB 15 0 Reset...

Page 407: ...RM0008 General purpose timers TIM2 to TIM5 Doc ID 13902 Rev 12 407 1096 ...

Page 408: ...re the Flash memory density ranges between 768 Kbytes and 1 Mbyte Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers This section applies to XL density devices only 16 1 TIM9 to TIM14 introduction The TIM9 to TIM14 general purpose timers consist of a 16 bit auto reload counter driven by a programmable prescaler They may be used for a variety of purposes including measuring ...

Page 409: ...nter initialization by software or internal trigger Trigger event counter start stop initialization or count by internal trigger Input capture Output compare Figure 146 General purpose timer block diagram TIM9 and TIM12 Auto reload register Capture Compare 1 register Capture Compare 2 register U U U CC1I CC2I Trigger controller Stop Clear TI1FP1 TI2FP2 ITR0 ITR1 ITR2 ITR3 TRGI output control OC1 O...

Page 410: ...n edge aligned mode Interrupt generation on the following events Update counter overflow counter initialization by software Input capture Output compare Figure 147 General purpose timer block diagram TIM10 11 13 14 Autoreload register Capture Compare 1 register U U CC1I Stop Clear output control OC1 OC1REF U UI IC1 Prescaler Input filter edge detector IC1PS TI1FP1 Reg event Notes Preload registers...

Page 411: ...nable bit ARPE in TIMx_CR1 register The update event is sent when the counter reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register It can also be generated by software The generation of the update event is described in detailed for each configuration The counter is clocked by the prescaler output CK_CNT which is enabled only when the counter enable bit CEN in TIMx_CR1 registe...

Page 412: ...R1 register This is to avoid updating the shadow registers while writing new values in the preload registers Then no update event occurs until the UDIS bit has been written to 0 However the counter restarts from 0 as well as the counter of the prescaler but the prescale rate does not change In addition if the URS bit update request selection in TIMx_CR1 register is set setting the UG bit generates...

Page 413: ...x_ARR The buffer of the prescaler is reloaded with the preload value content of the TIMx_PSC register The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR 0x36 Figure 150 Counter timing diagram internal clock divided by 1 Figure 151 Counter timing diagram internal clock divided by 2 CK_PSC 00 CNT_EN Timer clock CK_CNT Counter register Updat...

Page 414: ...RR not preloaded CK_PSC 0000 0001 CNT_EN Timer clock CK_CNT Counter register Update interrupt flag UIF 0035 0036 Counter overflow Update event UEV Timer clock CK_CNT Counter register 00 1F 20 Update interrupt flag UIF Counter overflow Update event UEV CK_PSC CK_PSC 00 CEN Timer clock CK_CNT Counter register Update interrupt flag UIF Counter overflow Update event UEV 01 02 03 04 05 06 07 32 33 34 3...

Page 415: ...ce for TIM10 TIM11 and TIM13 TIM14 For TIM9 and TIM12 the internal clock source is selected when the slave mode controller is disabled SMS 000 The CEN bit in the TIMx_CR1 register and the UG bit in the TIMx_EGR register are then used as control bits and can be changed only by software except for UG which remains cleared As soon as the CEN bit is programmed to 1 the prescaler is clocked by the inte...

Page 416: ...ting CC2P 0 and CC2NP 0 in the TIMx_CCER register 4 Configure the timer in external clock mode 1 by writing SMS 111 in the TIMx_SMCR register 5 Select TI2 as the trigger input source by writing TS 110 in the TIMx_SMCR register 6 Enable the counter by writing CEN 1 in the TIMx_CR1 register Note The capture prescaler is not used for triggering so you don t need to configure it When a rising edge occ...

Page 417: ...generates a signal TIxFPx which can be used as trigger input by the slave mode controller or as the capture command It is prescaled before the capture register ICxPS Figure 159 Capture compare channel example channel 1 input stage The output stage generates an intermediate waveform which is then used for reference OCxRef active high The polarity acts at the end of the chain Counter clock CK_CNT CK...

Page 418: ...of the counter after a transition detected by the corresponding ICx signal When a capture occurs the corresponding CCXIF flag TIMx_SR register is set and an interrupt or a DMA request can be sent if they are enabled If a capture occurs while the CCxIF flag was already high then the over capture flag CCxOF TIMx_SR register is set CCxIF can be CC1E Capture compare shadow register comparator Capture ...

Page 419: ... wish the capture to be performed at each valid transition so the prescaler is disabled write IC1PS bits to 00 in the TIMx_CCMR1 register 5 Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register 6 If needed enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register When an input capture occurs The TIMx_CCR1 register ...

Page 420: ...t that only TI1FP1 and TI2FP2 are connected to the slave mode controller 16 4 7 Forced output mode In output mode CCxS bits 00 in the TIMx_CCMRx register each output compare signal OCxREF and then OCx can be forced to active or inactive level directly by software independently of any comparison between the output compare register and the counter To force an output compare signal OCXREF OCx to its ...

Page 421: ...rammed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register In output compare mode the update event UEV has no effect on OCxREF and OCx output The timing resolution is one count of the counter Output compare mode can also be used to output a single pulse in One pulse mode Procedure 1 Select the counter clock internal external prescaler 2 Write the desired data in the TI...

Page 422: ...ize all the registers by setting the UG bit in the TIMx_EGR register The OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register It can be programmed as active high or active low The OCx output is enabled by the CCxE bit in the TIMx_CCER register Refer to the TIMx_CCERx register description for more details In PWM mode 1 or 2 TIMx_CNT and TIMx_CCRx are always compared to...

Page 423: ...se timers TIM9 to TIM14 Doc ID 13902 Rev 12 423 1096 Figure 164 Edge aligned PWM waveforms ARR 8 Counter register Äò 0 1 2 3 4 5 6 7 8 0 1 Äò OCXREF CCxIF OCXREF CCxIF OCXREF CCxIF OCXREF CCxIF CCRx 4 CCRx 8 CCRx 8 CCRx 0 ...

Page 424: ...f the compare value is different from the counter initial value Before starting when the timer is waiting for the trigger the configuration must be as follows CNT CCRx ARR in particular 0 CCRx Figure 165 Example of one pulse mode For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input p...

Page 425: ...RR register generate an update by setting the UG bit and wait for external trigger event on TI2 CC1P is written to 0 in this example You only want 1 pulse Single mode so you write 1 in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event when the counter rolls over from the auto reload value back to 0 When OPM bit in the TIMx_CR1 register is set to 0 so the Repetitive ...

Page 426: ...lect the input capture source only CC1S 01 in the TIMx_CCMR1 register Program CC1P and CC1NP to 00 in TIMx_CCER register to validate the polarity and detect rising edges only 2 Configure the timer in reset mode by writing SMS 100 in TIMx_SMCR register Select TI1 as the input source by writing TS 101 in TIMx_SMCR register 3 Start the counter by writing CEN 1 in the TIMx_CR1 register The counter sta...

Page 427: ...o validate the polarity and detect low level only 2 Configure the timer in gated mode by writing SMS 101 in TIMx_SMCR register Select TI1 as the input source by writing TS 101 in TIMx_SMCR register 3 Enable the counter by writing CEN 1 in the TIMx_CR1 register in gated mode the counter doesn t start if CEN 0 whatever is the trigger input level The counter starts counting on the internal clock as l...

Page 428: ...MS 110 in TIMx_SMCR register Select TI2 as the input source by writing TS 110 in TIMx_SMCR register When a rising edge occurs on TI2 the counter starts counting on the internal clock and the TIF flag is set The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input Figure 168 Control circuit in trigger mode 16 4 12 Timer synchr...

Page 429: ...M One pulse mode 0 Counter is not stopped on the update event 1 Counter stops counting on the next update event clearing the CEN bit Bit 2 URS Update request source This bit is set and cleared by software to select the UEV event sources 0 Any of the following events generates an update interrupt if enabled Counter overflow Setting the UG bit 1 Only counter overflow generates an update interrupt if...

Page 430: ...gger output TRGO It is useful to start several timers at the same time or to control a window in which a slave timer is enabled The Counter Enable signal is generated by a logic OR between the CEN control bit and the trigger input when configured in Gated mode When the Counter Enable signal is controlled by the trigger input there is a delay on TRGO except if the master slave mode is selected see ...

Page 431: ...hey are not used e g when SMS 000 to avoid wrong edge detections at the transition Bit 3 Reserved always read as 0 Bits 2 0 SMS Slave mode selection When external signals are selected the active edge of the trigger signal TRGI is linked to the polarity selected on the external input see Input control register and Control register descriptions 000 Slave mode disabled if CEN 1 then the prescaler is ...

Page 432: ...M2 TIM3 TIM10 TIM11 TIM12 TIM4 TIM5 TIM13 TIM14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TIE Res CC2IE CC1IE UIE rw rw rw rw Bit 15 7 Reserved always read as 0 Bit 6 TIE Trigger interrupt enable 0 Trigger interrupt disabled 1 Trigger interrupt enabled Bit 5 3 Reserved always read as 0 Bit 2 CC2IE Capture Compare 2 interrupt enable 0 CC2 interrupt disabled 1 CC2 interrupt enabled Bit 1 CC1IE ...

Page 433: ...tected on TRGI input when the slave mode controller is enabled in all modes but gated mode It is set when the counter starts or stops when gated mode is selected It is cleared by software 0 No trigger event occurred 1 Trigger interrupt pending Bit 5 3 Reserved always read as 0 Bit 2 CC2IF Capture Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF Capture compare 1 interrupt flag If ch...

Page 434: ...to generate an event it is automatically cleared by hardware 0 No action 1 The TIF flag is set in the TIMx_SR register Related interrupt can occur if enabled Bits 5 3 Reserved always read as 0 Bit 2 CC2G Capture compare 2 generation refer to CC1G description Bit 1 CC1G Capture compare 1 generation This bit is set by software to generate an event it is automatically cleared by hardware 0 No action ...

Page 435: ... OC1FE CC1S 1 0 IC2F 3 0 IC2PSC 1 0 IC1F 3 0 IC1PSC 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 15 OC2CE Output compare 2 clear enable Bits 14 12 OC2M 2 0 Output compare 2 mode Bit 11 OC2PE Output compare 2 preload enable Bit 10 OC2FE Output compare 2 fast enable Bits 9 8 CC2S 1 0 Capture Compare 2 selection This bitfield defines the direction of the channel input output as well as the...

Page 436: ...ode Bit 3 OC1PE Output compare 1 preload enable 0 Preload register on TIMx_CCR1 disabled TIMx_CCR1 can be written at anytime the new value is taken into account immediately 1 Preload register on TIMx_CCR1 enabled Read Write operations access the preload register TIMx_CCR1 preload value is loaded into the active register at each update event Note The PWM mode can be used without validating the prel...

Page 437: ... fDTS 2 N 6 0101 fSAMPLING fDTS 2 N 8 0110 fSAMPLING fDTS 4 N 6 0111 fSAMPLING fDTS 4 N 8 1000 fSAMPLING fDTS 8 N 6 1001 fSAMPLING fDTS 8 N 8 1010 fSAMPLING fDTS 16 N 5 1011 fSAMPLING fDTS 16 N 6 1100 fSAMPLING fDTS 16 N 8 1101 fSAMPLING fDTS 32 N 5 1110 fSAMPLING fDTS 32 N 6 1111 fSAMPLING fDTS 32 N 8 Note In the current silicon revision fDTS is replaced in the formula by CK_INT when ICxF 3 0 1 2...

Page 438: ...1 active low CC1 channel configured as input CC1NP CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations 00 noninverted rising edge circuit is sensitive to TIxFP1 rising edge capture trigger in reset external clock or trigger mode TIxFP1 is not inverted trigger in gated mode encoder mode 01 inverted falling edge circuit is sensitive to TIxFP1 falling edge capture trigger in...

Page 439: ...rity OCx_EN 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 CNT 15 0 Counter value 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 PSC 15 0 Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC PSC 15 0 1 PSC contains the value to be loaded into the active prescaler ...

Page 440: ...active capture compare register contains the value to be compared to the TIMx_CNT counter and signaled on the OC1 output If channel CC1is configured as input CCR1 is the counter value transferred by the last input capture 1 event IC1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR2 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 CCR2 15 0 Capture Compare 2 value If channel CC2 is configur...

Page 441: ...ved CC2IF CC1IF UIF Reset value 0 0 0 0 0 0 0x14 TIMx_EGR Reserved TG Reserved Reserved Reserved CC2G CC1G UG Reset value 0 0 0 0 0x18 TIMx_CCMR1 Output Compare mode Reserved OC2M 2 0 OC2PE OC2FE CC2S 1 0 Reserved OC1M 2 0 OC1PE OC1FE CC1S 1 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_CCMR1 Input Capture mode Reserved IC2F 3 0 IC2 PSC 1 0 CC2S 1 0 IC1F 3 0 IC1 PSC 1 0 CC1S 1 0 Reset value 0 0 0...

Page 442: ...ffered 1 TIMx_ARR register is buffered Bits 6 3 Reserved always read as 0 Bit 2 URS Update request source This bit is set and cleared by software to select the update interrupt UEV sources 0 Any of the following events generate an UEV if enabled Counter overflow Setting the UG bit 1 Only counter overflow generates an UEV if enabled Bit 1 UDIS Update disable This bit is set and cleared by software ...

Page 443: ...responding channel is configured in input capture mode It is cleared by software by writing it to 0 0 No overcapture has been detected 1 The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set Bits 8 2 Reserved always read as 0 Bit 1 CC1IF Capture compare 1 interrupt flag If channel CC1 is configured as output This flag is set by hardware when the counter matches...

Page 444: ... read as 0 Bit 1 CC1G Capture compare 1 generation This bit is set by software in order to generate an event it is automatically cleared by hardware 0 No action 1 A capture compare event is generated on channel 1 If channel CC1 is configured as output CC1IF flag is set Corresponding interrupt or is sent if enabled If channel CC1 is configured as input The current value of the counter is captured i...

Page 445: ...compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs 001 Set channel 1 to active level on match OC1REF signal is forced high when the counter TIMx_CNT matches the capture compare register 1 TIMx_CCR1 010 Set channel 1 to inactive level on match OC1REF signal is forced low when the counter TIMx_CNT matches the capture compare register 1 TIMx_CCR1 011 Toggle OC1REF toggle...

Page 446: ...ently of the result of the comparison Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles OC1FE acts only if the channel is configured in PWM1 or PWM2 mode Bits 1 0 CC1S Capture Compare 1 selection This bit field defines the direction of the channel input output as well as the used input 00 CC1 channel is configured as output 01 CC1 channel is configured as in...

Page 447: ...S 32 N 8 Note In current silicon revision fDTS is replaced in the formula by CK_INT when ICxF 3 0 1 2 or 3 Bits 3 2 IC1PSC Input capture 1 prescaler This bit field defines the ratio of the prescaler acting on CC1 input IC1 The prescaler is reset as soon as CC1E 0 TIMx_CCER register 00 no prescaler capture is done each time an edge is detected on the capture input 01 capture is done once every 2 ev...

Page 448: ...1 active low CC1 channel configured as input The CC1P bit selects TI1FP1 and TI2FP1 polarity for trigger or capture operations 00 noninverted rising edge circuit is sensitive to TI1FP1 rising edge capture mode TI1FP1 is not inverted 01 inverted falling edge circuit is sensitive to TI1FP1 falling edge capture mode TI1FP1 is inverted 10 reserved do not use this configuration 11 noninverted both edge...

Page 449: ...lue 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSC 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 PSC 15 0 Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC PSC 15 0 1 PSC contains the value to be loaded in the active prescaler register at each update event 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARR 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 ARR 1...

Page 450: ...ontains the value to be compared to the counter TIMx_CNT and signaled on OC1 output If channel CC1is configured as input CCR1 is the counter value transferred by the last input capture 1 event IC1 Table 93 TIM10 11 13 14 register map and reset values Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 TIMx_CR1 Reserved CKD 1 0 ARPE Reserved Re...

Page 451: ...x_PSC Reserved PSC 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x2C TIMx_ARR Reserved ARR 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x30 Reserved 0x34 TIMx_CCR1 Reserved CCR1 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x38 to 0x4C Reserved Table 93 TIM10 11 13 14 register map and reset values continued Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11...

Page 452: ...ontrollers This section applies to high density and XL density STM32F101xx and STM32F103xx devices and to connectivity line devices only 17 1 TIM6 TIM7 introduction The basic timers TIM6 and TIM7 consist of a 16 bit auto reload counter driven by a programmable prescaler They may be used as generic timers for time base generation but they are also specifically used to drive the digital to analog co...

Page 453: ...ster are transferred into the shadow register permanently or at each update event UEV depending on the auto reload preload enable bit ARPE in the TIMx_CR1 register The update event is sent when the counter reaches the overflow value and if the UDIS bit equals 0 in the TIMx_CR1 register It can also be generated by software The generation of the update event is described in detail for each configura...

Page 454: ...es of the counter behavior when the prescaler ratio is changed on the fly Figure 170 Counter timing diagram with prescaler division change from 1 to 2 Figure 171 Counter timing diagram with prescaler division change from 1 to 4 CK_PSC 00 CNT_EN Timer clock CK_CNT Counter register Update event UEV 0 F9 FA FB FC F7 Prescaler control register 0 1 Write a new value in TIMx_PSC 01 02 03 Prescaler buffe...

Page 455: ...restart from 0 but the prescale rate does not change In addition if the URS update request selection bit in the TIMx_CR1 register is set setting the UG bit generates an update event UEV but the UIF flag is not set so no interrupt or DMA request is sent When an update event occurs all the registers are updated and the update flag UIF bit in the TIMx_SR register is set depending on the URS bit The b...

Page 456: ...m internal clock divided by N CK_INT 0035 0000 0001 0002 0003 CNT_EN Timer clock CK_CNT Counter register Update interrupt flag UIF 0034 0036 Counter overflow Update event UEV 0000 0001 CNT_EN TImer clock CK_CNT Counter register Update interrupt flag UIF 0035 0036 Counter overflow Update event UEV CK_INT Timer clock CK_CNT Counter register 00 1F 20 Update interrupt flag UIF Counter overflow Update ...

Page 457: ... automatically As soon as the CEN bit is written to 1 the prescaler is clocked by the internal clock CK_INT Figure 178 shows the behavior of the control circuit and the upcounter in normal mode without prescaler 00 CNT_EN Timer clock CK_CNT Counter register Update interrupt flag UIF Counter overflow Update event UEV 01 02 03 04 05 06 07 32 33 34 35 36 31 Auto reload register FF 36 Write a new valu...

Page 458: ...s used in register descriptions The peripheral registers can be accessed by half words 16 bit or words 32 bit 17 4 1 TIM6 TIM7 control register 1 TIMx_CR1 Address offset 0x00 Reset value 0x0000 CK_INT 00 Counter clock CK_CNT CK_PSC Counter register 01 02 03 04 05 06 07 32 33 34 35 36 31 CEN CNT_EN UG CNT_INIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ARPE Reserved OPM URS UDIS CEN rw rw rw rw...

Page 459: ...ion 0 UEV enabled The Update UEV event is generated by one of the following events Counter overflow underflow Setting the UG bit Update generation through the slave mode controller Buffered registers are then loaded with their preload values 1 UEV disabled The Update event is not generated shadow registers keep their value ARR PSC However the counter and the prescaler are reinitialized if the UG b...

Page 460: ... enable signal CNT_EN is used as a trigger output TRGO It is useful to start several timers at the same time or to control a window in which a slave timer is enabled The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode When the Counter Enable signal is controlled by the trigger input there is a delay on TRGO except if the ...

Page 461: ...et by hardware when the registers are updated At overflow or underflow regarding the repetition counter value and if UDIS 0 in the TIMx_CR1 register When CNT is reinitialized by software using the UG bit in the TIMx_EGR register if URS 0 and UDIS 0 in the TIMx_CR1 register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved UG w Bits 15 1 Reserved always read as 0 Bit 0 UG Update generation This bit ca...

Page 462: ...5 0 Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC PSC 15 0 1 PSC contains the value to be loaded into the active prescaler register at each update event 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARR 15 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 ARR 15 0 Prescaler value ARR is the value to be loaded into the actual auto reload register Refer to Section 17 3 1 T...

Page 463: ...12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 TIMx_CR1 Reserved ARPE Reserved OPM URS UDIS CEN Reset value 0 0 0 0 0 0x04 TIMx_CR2 Reserved MMS 2 0 Reserved Reset value 0 0 0 0x08 Reserved 0x0C TIMx_DIER Reserved UDE Reserved UIE Reset value 0 0 0x10 TIMx_SR Reserved UIF Reset value 0 0x14 TIMx_EGR Reserved UG Reset value 0 0x18 Reserved 0x1C Reserved 0x20 Reserved 0x24 TIMx_CNT Reserved CNT 15 0 Reset value ...

Page 464: ...applies to the whole STM32F10xxx family unless otherwise specified 18 1 RTC introduction The real time clock is an independent timer The RTC provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function The counter values can be written to set the current time date of the system The RTC core and clock configuration RCC_BDCR register a...

Page 465: ...lator clock LSI oscillator clock refer to Section 7 2 8 RTC clock for details Two separate reset types The APB1 interface is reset by system reset The RTC Core Prescaler Alarm Counter and Divider is reset only by a Backup domain reset see Section 7 1 3 Backup domain reset on page 88 Three dedicated maskable interrupt lines Alarm interrupt for generating a software programmable alarm interrupt Seco...

Page 466: ... includes a 20 bit programmable divider RTC Prescaler Every TR_CLK period the RTC generates an interrupt Second Interrupt if it is enabled in the RTC_CR register The second block is a 32 bit programmable counter that can be initialized to the current system time The system time is incremented at the TR_CLK rate and compared with a programmable date stored in the RTC_ALR register in order to genera...

Page 467: ...ower modes In all the above cases the RTC core has been kept running while the APB1 interface was disabled reset not clocked or unpowered Consequently when reading the RTC registers after having disabled the RTC APB1 interface the software must first wait for the RSF bit Register Synchronized Flag in the RTC_CRL register to be set by hardware Note that the RTC APB1 interface is not affected by WFI...

Page 468: ...he RTC interrupt routine the RTC Alarm and or RTC Counter registers are updated Wait for SECF bit to be set in the RTC Control register Update the RTC Alarm and or the RTC Counter register Figure 180 RTC second and alarm waveform example with PR 0003 ALARM 00004 Figure 181 RTC Overflow waveform example with PR 0003 RTC_CNT 0000 0001 RTC_PR 0002 0001 0000 0003 0002 0001 0000 0003 0002 RTC_ALARM 000...

Page 469: ...lization It is not possible to write to the RTC_CRH register when the peripheral is completing a previous write operation flagged by RTOFF 0 see Section 18 3 4 on page 467 The RTC functions are controlled by this control register Some bits must be written using a specific configuration procedure see Configuration procedure 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OWIE ALRIE SECIE rw rw rw Bi...

Page 470: ...cleared by software Before any read operation after an APB1 reset or an APB1 clock stop this bit must be cleared by software and the user application must wait until it is set to be sure that the RTC_CNT RTC_ALR or RTC_PRL registers are synchronized 0 Registers not yet synchronized 1 Registers synchronized Bit 2 OWF Overflow flag This bit is set by hardware when the 32 bit programmable counter ove...

Page 471: ...is also enabled through the EXTI Controller both the RTC global interrupt and the RTC Alarm interrupt are enabled 6 If ALRF 1 the RTC Alarm interrupt is enabled if EXTI Line 17 is enabled through the EXTI Controller in interrupt mode When the EXTI Line 17 is enabled in event mode a pulse is generated on this line no RTC Alarm interrupt generation 18 4 3 RTC prescaler load register RTC_PRLH RTC_PRL...

Page 472: ... and it is reloaded by hardware after any change in the RTC_PRL or RTC_CNT registers RTC prescaler divider register high RTC_DIVH Address offset 0x10 Reset value 0x0000 RTC prescaler divider register low RTC_DIVL Address offset 0x14 Reset value 0x8000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PRL 15 0 w w w w w w w w w w w w w w w w Bits 15 0 PRL 15 0 RTC prescaler reload value low These bits are used...

Page 473: ... register high RTC_CNTH Address offset 0x18 Reset value 0x0000 RTC counter register low RTC_CNTL Address offset 0x1C Reset value 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC_CNT 31 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 0 RTC_CNT 31 16 RTC counter high Reading the RTC_CNTH register the current value of the high part of the RTC Counter register is returned To write to this r...

Page 474: ...w RTC_ALRL Address offset 0x24 Write only see Section 18 3 4 on page 467 Reset value 0xFFFF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTC_ALR 31 16 w w w w w w w w w w w w w w w w Bits 15 0 RTC_ALR 31 16 RTC alarm high The high part of the alarm time is written by software in this register To write to this register it is necessary to enter configuration mode see Section 18 3 4 Configuring RTC register...

Page 475: ... Reserved RTOFF CNF RSF OWF ALRF SECF Reset value 1 0 0 0 0 0 0x08 RTC_PRLH Reserved PRL 19 16 Reset value 0 0 0 0 0x0C RTC_PRLL Reserved PRL 15 0 Reset value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x10 RTC_DIVH Reserved DIV 31 16 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x14 RTC_DIVL Reserved DIV 15 0 Reset value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x18 RTC_CNTH Reserved CNT 13 16 Reset value 0 0 0 0 0 0...

Page 476: ... or an interrupt window watchdog only when the counter reaches a given timeout value The independent watchdog IWDG is clocked by its own dedicated low speed clock LSI and thus stays active even if the main clock fails The window watchdog WWDG clock is prescaled from the APB1 clock and has a configurable time window that can be programmed to detect abnormally late or early application behavior The ...

Page 477: ...LR value is reloaded in the counter and the watchdog reset is prevented 19 3 1 Hardware watchdog If the Hardware watchdog feature is enabled through the device option bits the watchdog is automatically enabled at power on and will generate a reset unless the Key register is written by the software before the counter reaches end of count ...

Page 478: ...watchdog block diagram Note The watchdog function is implemented in the VDD voltage domain that is still functional in Stop and Standby modes The LSI can be calibrated so as to compute the IWDG timeout with an acceptable accuracy For more details refer to LSI clock on page 93 IWDG RESET prescaler 12 bit downcounter IWDG_PR Prescaler register IWDG_RLR Reload register 8 bit LSI IWDG_KR Key register ...

Page 479: ... the key value 5555h to enable access to the IWDG_PR and IWDG_RLR registers see Section 19 3 2 Writing the key value CCCCh starts the watchdog except if the hardware watchdog option is selected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PR 2 0 rw rw rw Bits 31 3 Reserved read as 0 Bits 2 0 PR 2 0 Prescaler divider These bits are write access prot...

Page 480: ...en in the IWDG_KR register The watchdog counter counts down from this value The timeout period is a function of this value and the clock prescaler Refer to Table 96 The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload value Note Reading this register returns the reload value from the VDD voltage domain This value may not be up to date valid if a write operatio...

Page 481: ...boundary addresses Table 97 IWDG register map and reset values Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 IWDG_KR Reserved KEY 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x04 IWDG_PR Reserved PR 2 0 Reset value 0 0 0 0x08 IWDG_RLR Reserved RL 11 0 Reset value 1 1 1 1 1 1 1 1 1 1 1 1 0x0C IWDG_SR Reserved RVU PVU Reset value 0 0 ...

Page 482: ...am to abandon its normal sequence The watchdog circuit generates an MCU reset on expiry of a programmed time period unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared An MCU reset is also generated if the 7 bit downcounter value in the control register is refreshed before the downcounter has reached the window register value This implies that the counter...

Page 483: ...m and a maximum value due to the unknown status of the prescaler when writing to the WWDG_CR register see Figure 184 The Configuration register WWDG_CFR contains the high limit of the window To prevent a reset the downcounter must be reloaded when its value is lower than the window register value and greater than 0x3F Figure 184 describes the window watchdog process Another way to reload the count...

Page 484: ... the WWDG counter either continues to work normally or stops depending on DBG_WWDG_STOP configuration bit in DBG module For more details refer to Section 31 16 2 Debug support for timers watchdog bxCAN and I2C T6 bit Reset W 6 0 T 6 0 CNT downcounter time Refresh window Refresh not allowed 0x3F The formula to calculate the timeout value is given by where TWWDG WWDG timeout TPCLK1 APB1 clock period...

Page 485: ...27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WDGA T 6 0 rs rw Bits 31 8 Reserved Bit 7 WDGA Activation bit This bit is set by software and only cleared by hardware after a reset When WDGA 1 the watchdog can generate a reset 0 Watchdog disabled 1 Watchdog enabled Bits 6 0 T 6 0 7 bit counter MSB to LSB These bits contain the value of the watchdog count...

Page 486: ...ts 8 7 WDGTB 1 0 Timer base The time base of the prescaler can be modified as follows 00 CK Counter Clock PCLK1 div 4096 div 1 01 CK Counter Clock PCLK1 div 4096 div 2 10 CK Counter Clock PCLK1 div 4096 div 4 11 CK Counter Clock PCLK1 div 4096 div 8 Bits 6 0 W 6 0 7 bit window value These bits contain the window value to be compared to the downcounter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1...

Page 487: ...age 50 for the register boundary addresses Table 98 WWDG register map and reset values Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 WWDG_CR Reserved WDGA T 6 0 Reset value 0 1 1 1 1 1 1 1 0x04 WWDG_CFR Reserved EWI WDGTB1 WDGTB0 W 6 0 Reset value 0 0 0 1 1 1 1 1 1 1 0x08 WWDG_SR Reserved EWIF Reset value 0 ...

Page 488: ...ranslate the AHB transactions into the appropriate external device protocol Meet the access timing requirements of the external devices All external memories share the addresses data and control signals with the controller Each external device is accessed by means of a unique chip select The FSMC performs only one access at a time to an external device The FSMC has the following main features Inte...

Page 489: ...ne burst at a time is buffered if a new AHB burst or single transaction occurs while an operation is in progress first the FIFO is drained The FSMC will insert wait states until the current memory access is complete External asynchronous wait control The FSMC registers that define the external device type and associated characteristics are usually set at boot time and do not change until the next ...

Page 490: ...owing conditions When reading or writing to an FSMC bank which is not enabled When reading or writing to the NOR Flash bank while the FACCEN bit is reset in the FSMC_BCRx register When reading or writing to the PC Card banks while the input pin FSMC_CD Card Presence Detection is low AHB bus FSMC interrupt to NVIC NOR HCLK From clock controller controller memory NAND PC Card controller memory Confi...

Page 491: ...e memory accesses in order to meet the external data width AHB transaction size is smaller than the memory size Asynchronous transfers may or not be consistent depending on the type of external device Asynchronous accesses to devices that have the byte select feature SRAM ROM PSRAM In this case the FSMC allows read write transactions and accesses the right data through its byte lanes BL 1 0 Asynch...

Page 492: ... each bank the type of memory to be used is user defined in the Configuration register Figure 186 FSMC memory banks 21 4 1 NOR PSRAM address mapping HADDR 27 26 bits are used to select one of the four memory banks as shown in Table 99 Bank 1 NAND Flash NOR PSRAM Supported memory type Banks 4 64 MB 6000 0000h 6FFF FFFFh Address 7000 0000h 7FFF FFFFh 8000 0000h 8FFF FFFFh 9000 0000h 9FFF FFFFh Bank ...

Page 493: ...n attribute memory space Table 100 External memory address Memory width 1 1 In case of a 16 bit external memory width the FSMC will internally use HADDR 25 1 to generate the address for external memory FSMC_A 24 0 Whatever the external memory width 16 bit or 8 bit FSMC_A 0 should be connected to external memory address A 0 Data address issued to the memory Maximum memory capacity bits 8 bit HADDR ...

Page 494: ... appropriate signal timings to drive the following types of memories Asynchronous SRAM and ROM 8 bit 16 bit 32 bit PSRAM Cellular RAM Asynchronous mode Burst mode NOR Flash Asynchronous mode or burst mode Multiplexed or nonmultiplexed The FSMC outputs a unique chip select signal NE 4 1 per bank All the other signals addresses data and control are shared For synchronous accesses the FSMC issues the...

Page 495: ...nous AHB clock cycle HCLK 1 16 Data latency Number of clock cycles to issue to the memory before the first data of the burst Synchronous Memory clock cycle CLK 2 17 Table 103 Programmable NOR PSRAM access parameters continued Parameter Function Access mode Unit Min Max Table 104 Nonmuxed I O NOR Flash FSMC signal name I O Function CLK O Clock for synchronous burst A 25 0 O Address bus D 15 0 I O B...

Page 496: ...s example appear in gray NWE O Write enable NL NADV O Latch enable this signal is called address valid NADV by some NOR Flash devices NWAIT I NOR Flash wait input signal to the FSMC Table 106 Non muxed I Os PSRAM SRAM FSMC signal name I O Function CLK O Clock only for PSRAM synchronous burst A 25 0 O Address bus D 15 0 I O Data bidirectional bus NE x O Chip select x 1 4 called NCE by PSRAM Cellula...

Page 497: ...R 8 16 N Synchronous R 16 16 Y Synchronous R 32 16 Y PSRAM muxed I Os and nonmuxed I Os Asynchronous R 8 16 Y Asynchronous W 8 16 Y Use of byte lanes NBL 1 0 Asynchronous R 16 16 Y Asynchronous W 16 16 Y Asynchronous R 32 16 Y Split into 2 FSMC accesses Asynchronous W 32 16 Y Split into 2 FSMC accesses Asynchronous page R 16 N Mode is not supported Synchronous R 8 16 N Synchronous R 16 16 Y Synchr...

Page 498: ... ID 13902 Rev 12 21 5 3 General timing rules Signals synchronization All controller output signals change on the rising edge of the internal clock HCLK In synchronous write mode PSRAM devices the output data changes on the falling edge of the memory clock CLK ...

Page 499: ...rting the chip select signal NE This guarantees that the memory data hold timing constraint is met chip enable high to data transition usually 0 ns min When extended mode is set it is possible to mix modes A B C and D in read and write it is for instance possible to read in mode A and write in mode B Mode 1 SRAM CRAM Figure 187 Mode1 read accesses A 25 0 NOE ADDSET 1 DATAST 1 Memory transaction Da...

Page 500: ...ST value must be greater than zero DATAST 0 Table 108 FSMC_BCRx bit fields Bit number Bit name Value to set 31 16 0x0000 15 ASYNCWAIT Set to 1 if the memory supports this feature Otherwise keep at 0 14 10 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 6 FACCEN 5 4 MWID As needed 3 2 MTYP As needed exclude 10 NOR Flash 1 MUXEN 0x0 0 MBKEN 0x1 A 25 0 NOE ADDSET 1 DATAST 1 Memory transa...

Page 501: ...x0000 15 8 DATAST Duration of the second access phase DATAST 1 HCLK cycles for write accesses DATAST 3 HCLK cycles for read accesses This value cannot be 0 minimum is 1 7 4 0x0 3 0 ADDSET Duration of the first access phase ADDSET 1 HCLK cycles A 25 0 NOE ADDSET 1 DATAST 1 Memory transaction Data strobe NEx D 15 0 HCLK cycles HCLK cycles NWE NBL 1 0 data driven by memory ai14722c High 2 HCLK cycles...

Page 502: ... fields Bit number Bit name Value to set 31 16 0x0000 15 ASYNCWAIT Set to 1 if the memory supports this feature Otherwise keep at 0 14 EXTMOD 0x1 13 10 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 6 FACCEN 5 4 MWID As needed 3 2 MTYP As needed exclude 10 NOR Flash 1 MUXEN 0x0 0 MBKEN 0x1 A 25 0 NOE ADDSET 1 DATAST 1 Memory transaction NEx D 15 0 HCLK cycles HCLK cycles NWE NBL 1 0 ...

Page 503: ...LK cycles in read This value cannot be 0 minimum is 1 7 4 0x0 3 0 ADDSET Duration of the first access phase ADDSET 1 HCLK cycles in read Table 112 FSMC_BWTRx bit fields Bit number Bit name Value to set 31 30 0x0 29 28 ACCMOD 0x0 27 16 0x000 15 8 DATAST Duration of the second access phase DATAST 1 HCLK cycles in write This value cannot be 0 minimum is 1 7 4 0x0 3 0 ADDSET Duration of the first acce...

Page 504: ...s Figure 192 Mode2 write accesses A 25 0 NOE ADDSET 1 DATAST 1 Memory transaction Data strobe NEx D 15 0 HCLK cycles HCLK cycles NWE NADV data driven by memory ai14724c High 2 HCLK cycles Data sampled A 25 0 NOE ADDSET 1 DATAST 1 Memory transaction NEx D 15 0 HCLK cycles HCLK cycles NWE NADV data driven by FSMC ai14723b 1HCLK ...

Page 505: ...BCRx bit fields Bit number Bit name Value to set 31 16 0x0000 15 ASYNCWAIT Set to 1 if the memory supports this feature Otherwise keep at 0 14 EXTMOD 0x1 for mode B 0x0 for mode 2 13 10 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 6 FACCEN 0x1 5 4 MWID As needed 3 2 MTYP 10 NOR Flash 1 MUXEN 0x0 0 MBKEN 0x1 A 25 0 NOE ADDSET 1 DATAST 1 Memory transaction NEx D 15 0 HCLK cycles HCLK...

Page 506: ...8 DATAST Duration of the access second phase DATAST 3 HCLK cycles in read This value can not be 0 minimum is 1 7 4 0x0 3 0 ADDSET Duration of the access first phase ADDSET 1 HCLK cycles in read Table 115 FSMC_BWTRx bit fields Bit number Bit name Value to set 31 30 0x0 29 28 ACCMOD 0x1 if extended mode is set 27 16 0x000 15 8 DATAST Duration of the access second phase DATAST 1 HCLK cycles in write ...

Page 507: ...mpared with mode1 are the toggling of NOE and NADV and the independent read and write timings A 25 0 NOE ADDSET 1 DATAST 1 Memory transaction Data strobe NEx D 15 0 HCLK cycles HCLK cycles NWE NADV data driven by memory ai14725c High 2 HCLK cycles Data sampled A 25 0 NOE ADDSET 1 DATAST 1 Memory transaction NEx D 15 0 HCLK cycles HCLK cycles NWE NADV data driven by FSMC ai14723b 1HCLK ...

Page 508: ...le 117 FSMC_BTRx bit fields Bit No Bit name Value to set 31 30 0x0 29 28 ACCMOD 0x2 27 16 0x000 15 8 DATAST Duration of the second access phase DATAST 3 HCLK cycles in read This value cannot be 0 minimum is 1 7 4 0x0 3 0 ADDSET Duration of the first access phase ADDSET 1 HCLK cycles in read Table 118 FSMC_BWTRx bit fields Bit No Bit name Value to set 31 30 0x0 29 28 ACCMOD 0x2 27 16 0x000 15 8 DAT...

Page 509: ...DV NOE that goes on toggling after NADV changes and the independent read and write timings A 25 0 NOE ADDSET 1 DATAST 1 Memory transaction Data strobe NEx D 15 0 HCLK cycles HCLK cycles NWE NADV data driven by memory ai14726c High ADDHLD 1 HCLK cycles 2 HCLK cycles Data sampled A 25 0 NOE ADDSET 1 DATAST 1 Memory transaction NEx D 15 0 HCLK cycles HCLK cycles NWE NADV data driven by FSMC ai14727c ...

Page 510: ...30 0x0 29 28 ACCMOD 0x2 27 16 0x000 15 8 DATAST Duration of the second access phase DATAST 3 HCLK cycles in read This value cannot be 0 minimum is 1 7 4 ADDHLD Duration of the middle phase of the read access ADDHLD 1 HCLK cycles 3 0 ADDSET Duration of the first access phase ADDSET 1 HCLK cycles in read Table 121 FSMC_BWTRx bit fields Bit No Bit name Value to set 31 30 0x0 29 28 ACCMOD 0x2 27 16 0x...

Page 511: ...te accesses The difference with mode D is the drive of the lower address byte s on the databus A 25 16 NOE ADDSET 1 DATAST 1 Memory transaction Data strobe NEx AD 15 0 HCLK cycles HCLK cycles NWE NADV data driven by memory ai14728c High ADDHLD 1 HCLK cycles Lower address BUSTURN 1 1 HCLK cycles 2 HCLK cycles Data sampled 1HCLK cycle A 25 16 NOE ADDSET 1 DATAST 2 Memory transaction NEx AD 15 0 HCLK...

Page 512: ...WAIT can be detected 4 HCLK cycles before the data sampling The following cases must be considered Table 122 FSMC_BCRx bit fields Bit No Bit name Value to set 31 16 0x0000 15 ASYNCWAIT Set to 1 if the memory supports this feature Otherwise keep at 0 14 EXTMOD 0x0 13 10 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 6 FACCEN 0x1 5 4 MWID As needed 3 2 MTYP 0x2 NOR 1 MUXEN 0x1 0 MBKEN ...

Page 513: ...x_wait_assertion_time address_phase hold_phase otherwise data_setup phase 4 HCLK Where max_wait_assertion_time is the maximum time taken by the memory to assert the WAIT signal once NEx NOE NWE is low The Figure 199 and Figure 200 show the number of HCLK clock cycles that memory access is extended after WAIT is removed by the asynchronous memory independently of the above cases Figure 199 Asynchro...

Page 514: ...controller FSMC RM0008 514 1096 Doc ID 13902 Rev 12 Figure 200 Asynchronous wait during a write access A 25 0 NWE Memory transaction NWAIT D 15 0 NEx data driven by FSMC ai15797 3HCLK address phase don t care data phase 1HCLK ...

Page 515: ...t the FSMC samples the data and waits long enough to evaluate if the data are valid Thus the FSMC detects when the memory exits latency and real data are taken Other memories do not assert NWAIT during latency In this case the latency must be set correctly for both the FSMC and the memory otherwise invalid data are mistaken for good data or valid data are lost in the initial phase of the memory ac...

Page 516: ...signal in burst mode Flash memory asserts the NWAIT signal one data cycle before the wait state default after reset Flash memory asserts the NWAIT signal during the wait state These two NOR Flash wait state configurations are supported by the FSMC individually for each chip select thanks to the WAITCFG bit in the FSMC_BCRx registers x 0 3 Figure 201 Wait configurations Addr 15 0 data data addr 25 ...

Page 517: ...7 IGH 6 7 4 7 4 CLOCK CYCLE CLOCK CYCLE 4 4 INSERTED WAIT STATE ATA STROBES AI B CYCLES DATA DATA ATA STROBES Table 124 FSMC_BCRx bit fields Bit No Bit name Value to set 31 20 0x0000 19 CBURSTRW No effect on synchronous read 18 15 0x0 14 EXTMOD 0x0 13 WAITEN When high the first data after latency period is taken as always valid regardless of the wait from memory value 12 WREN no effect on synchron...

Page 518: ...pport 5 4 MWID As needed 3 2 MTYP 0x1 or 0x2 1 MUXEN As needed 0 MBKEN 0x1 Table 125 FSMC_BTRx bit fields Bit No Bit name Value to set 27 24 DATLAT Data latency 23 20 CLKDIV 0x0 to get CLK HCLK not supported 0x1 to get CLK 2 HCLK 19 16 BUSTURN no effect 15 8 DATAST no effect 7 4 ADDHLD no effect 3 0 ADDSET no effect Table 124 FSMC_BCRx bit fields continued Bit No Bit name Value to set ...

Page 519: ...ignal one cycle in advance accordingly WAITCFG must be programmed to 0 2 Byte Lane NBL outputs are not shown they are held low while NEx is active Addr 15 0 data addr 25 16 Memory transaction burst of 2 half words HCLK CLK A 25 16 NEx NOE NWE Hi Z NADV NWAIT WAITCFG 0 A D 15 0 1 clock cycle 1 clock cycle DATALAT 2 inserted wait state ai14731d CLK cycles data ...

Page 520: ...hronous read 11 WAITCFG 0x0 10 WRAPMOD no effect 9 WAITPOL to be set according to memory 8 BURSTEN no effect on synchronous write 7 FWPRLVL Set to protect memory from accidental writes 6 FACCEN Set according to memory support 5 4 MWID As needed 3 2 MTYP 0x1 1 MUXEN As needed 0 MBKEN 0x1 Table 127 FSMC_BTRx bit fields Bit No Bit name Value to set 31 30 0x0 27 24 DATLAT Data latency 23 20 CLKDIV 0 t...

Page 521: ...ed in synchronous mode Bit 15 ASYNCWAIT Wait signal during asynchronous transfers This bit enables the FSMC to use the wait signal even during an asynchronous protocol 0 NWAIT signal is not taken in to account when running an asynchronous protocol default after reset 1 NWAIT signal is taken in to account when running an asynchronous protocol Bit 14 EXTMOD Extended mode enable This bit enables the ...

Page 522: ...st enable bit Enables the burst access mode for the memory Valid only with synchronous burst memories 0 Burst access mode disabled default after reset 1 Burst access mode enable Bit 7 Reserved Bit 6 FACCEN Flash access enable Enables NOR Flash memory access operations 0 Corresponding NOR Flash memory access is disabled 1 Corresponding NOR Flash memory access is enabled default after reset Bits 5 4...

Page 523: ...ynchronous burst mode enabled defines the number of memory clock cycles 2 to issue to the memory before getting the first data This timing parameter is not expressed in HCLK periods but in Flash clock CLK periods In asynchronous NOR Flash SRAM or ROM accesses this value is don t care In case of CRAM this field must be set to 0 0000 Data latency of 2 CLK clock cycles for first burst access 1111 Dat...

Page 524: ...T 1 Data phase duration DATAST 3 4 HCLK clock cycles Bits 7 4 ADDHLD Address hold phase duration These bits are written by software to define the duration of the address hold phase refer to Figure 196 to Figure 198 used in mode D and multiplexed accesses 0000 Reserved 0001 ADDHLD phase duration 2 HCLK clock cycle 0010 ADDHLD phase duration 3 HCLK clock cycle 1111 ADDHLD phase duration 16 HCLK cloc...

Page 525: ... memory clock cycles 2 to issue to the memory before getting the first data 0000 0x0 Data latency of 2 CLK clock cycles for first burst access 1111 0xF Data latency of 17 CLK clock cycles for first burst access default value after reset Note This timing parameter is not expressed in HCLK periods but in Flash clock CLK periods Note In asynchronous NOR Flash SRAM or ROM accesses this value is don t ...

Page 526: ...ase refer to Figure 196 to Figure 198 used in SRAMs ROMs and asynchronous multiplexed NOR Flash accesses 0000 Reserved 0001 ADDHLD phase duration 2 HCLK clock cycle 0010 ADDHLD phase duration 3 HCLK clock cycle 1111 ADDHLD phase duration 16 HCLK clock cycles default value after reset Note In synchronous NOR Flash accesses this value is not used the address hold phase is always 1 Flash clock period...

Page 527: ... mode Unit Min Max Memory setup time Number of clock cycles HCLK to set up the address before the command assertion Read Write AHB clock cycle HCLK 1 256 Memory wait Minimum duration HCLK clock cycles of the command assertion Read Write AHB clock cycle HCLK 2 256 Memory hold Number of clock cycles HCLK to hold the address and the data in case of a write access after the command de assertion Read W...

Page 528: ... name I O Function A 10 0 O Address bus NIOS16 I Data transfer in I O space It must be shorted to GND 16 bit tranfer only NIORD O Output enable for I O space NIOWR O Write enable for I O space NREG O Register signal indicating if access is in Common or Attribute space D 15 0 I O Bidirectional databus NCE4_1 O Chip select 1 NCE4_2 O Chip select 2 indicates if access is 16 bit or 8 bit NOE O Output ...

Page 529: ... to define number of HCLK cycles for the three phases of any PC Card CompactFlash or NAND Flash access plus one parameter that defines the timing for starting driving the databus in the case of a write Figure 204 shows the timing parameter definitions for common memory accesses knowing that Attribute and I O only for PC Card memory space access timings are similar Table 132 Supported memories and ...

Page 530: ... characteristics of the NAND Flash PWID bits for the databus width of the NAND Flash PTYP 1 PWAITEN 1 PBKEN 1 see section Common memory space timing register 2 4 FSMC_PMEM2 4 on page 537 for timing configuration 2 The CPU performs a byte write in the common memory space with data byte equal to one Flash command byte for example 0x00 for Samsung NAND Flash devices The CLE input of the NAND Flash is...

Page 531: ...s by simply performing the operation described in step 5 a new random address can be accessed by restarting the operation at step 3 a new command can be sent to the NAND Flash device by restarting at step 2 21 6 5 NAND Flash pre wait functionality Some NAND Flash devices require that after writing the last part of the address the controller wait for the R NB signal to go low as shown in Figure 205...

Page 532: ...lemented in the FSMC can perform 1 bit error correction and 2 bit error detection per 256 512 1 024 2 048 4 096 or 8 192 bytes read from or written to NAND Flash The ECC modules monitor the NAND Flash databus and read write signals NCE and NWE each time the NAND Flash memory bank is active The functional operations are When access to NAND Flash is made to bank 2 or bank 3 the data present on the D...

Page 533: ...on of nCE2 A 32 bit AHB request is translated into two 16 bit memory accesses Accesses to Attribute Memory Space where the PC Card stores configuration information are limited to 8 bit AHB accesses at even addresses Note that a 16 bit AHB access will be converted into a single 8 bit memory transfer nCE1 will be asserted low NCE2 will be asserted high and only the even Byte on D7 D0 will be valid I...

Page 534: ...mmed as follows xxWAITx 4 max_wait_assertion_time HCLK Where max_wait_assertion_time is the maximum time taken by NWAIT to go low once nOE nWE or nIORD nIOWR is low After the de assertion of nWAIT the FSMC extends the WAIT phase for 4 HCLK clock cycles 1 0 0 1 0 X X X X 0 I O space Read Even Byte on D7 0 Not supported 1 0 0 1 0 X X X X 1 Read Odd Byte on D7 0 Not supported 1 0 0 1 0 X X X X 0 Writ...

Page 535: ...AHB clock cycles HCLK Time is t_ar TAR SET 4 THCLK where THCLK is the HCLK clock period 0000 1 HCLK cycle default 1111 16 HCLK cycles Note SET is MEMSET or ATTSET according to the addressed space Bits 12 9 TCLR CLE to RE delay Sets time from CLE low to RE low in number of AHB clock cycles HCLK Time is t_clr TCLR SET 4 THCLK where THCLK is the HCLK clock period 0000 1 HCLK cycle default 1111 16 HCL...

Page 536: ...sponding memory bank is enabled Bit 1 PWAITEN Wait feature enable bit Enables the Wait feature for the PC Card NAND Flash memory bank 0 disabled 1 enabled Note For a PC Card when the wait feature is enabled the MEMWAITx ATTWAITx IOWAITx bits must be programmed to a value as follows xxWAITx 4 max_wait_assertion_time HCLK Where max_wait_assertion_time is the maximum time taken by NWAIT to go low onc...

Page 537: ...w rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 24 MEMHIZx Common memory x databus HiZ time Defines the number of HCLK 1 only for NAND clock cycles during which the databus is kept in HiZ after the start of a PC Card NAND Flash write access to common memory space on socket x Only valid for write transaction 0000 0000 0x00 0 HCLK cycle for PC Card 1 HCLK cycle for NAND Flash 1111 1111 0xFF 255 HCL...

Page 538: ...Dx ATTWAITx ATTSETx rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 24 ATTHIZx Attribute memory x databus HiZ time Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the start of a PC CARD NAND Flash write access to attribute memory space on socket x Only valid for write transaction 0000 0000 0 HCLK cycle 11...

Page 539: ...t x Only valid for write transaction 0000 0000 0 HCLK cycle 1111 1111 255 HCLK cycles default value after reset Bits 23 16 IOHOLDx I O x hold time Defines the number of HCLK clock cycles to hold address and data for write access after the command deassertion NWE NOE for PC Card read or write access to I O space on socket x 0000 0000 reserved 0000 0001 1 HCLK cycle 1111 1111 255 HCLK cycles default...

Page 540: ...d in the FSMC_PCRx registers the CPU must read the computed ECC value from the FSMC_ECCx registers and then verify whether these computed parity data are the same as the parity value recorded in the spare area to determine whether a page is valid and to correct it if applicable The FSMC_ECCRx registers should be cleared after being read by setting the ECCEN bit to zero For computing a new data blo...

Page 541: ...TAST ADDHLD ADDSET 0xA000 000C FSMC_BTR2 Res ACCM OD DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET 0xA000 0014 FSMC_BTR3 Res ACCM OD DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET 0xA000 001C FSMC_BTR4 Res ACCM OD DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET 0xA000 0104 FSMC_BWTR1 Res ACCM OD DATLAT CLKDIV Reserved DATAST ADDHLD ADDSET 0xA000 010C FSMC_BWTR2 Res ACCM OD DATLAT CLKDIV Reserved DATAST ADDHLD...

Page 542: ...C FSMC_PATT2 ATTHIZx ATTHOLDx ATTWAITx ATTSETx 0xA000 008C FSMC_PATT3 ATTHIZx ATTHOLDx ATTWAITx ATTSETx 0xA000 00AC FSMC_PATT4 ATTHIZx ATTHOLDx ATTWAITx ATTSETx 0xA000 00B0 FSMC_PIO4 IOHIZx IOHOLDx IOWAITx IOSETx 0xA000 0074 FSMC_ECCR2 ECCx 0xA000 0094 FSMC_ECCR3 ECCx Table 135 FSMC register map continued Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4...

Page 543: ... Association website at www sdcard org CE ATA system specifications are available through the CE ATA workgroup website at www ce ata org The SDIO features include the following Full compliance with MultiMediaCard System Specification Version 4 2 Card support for three different databus modes 1 bit default 4 bit and 8 bit Full compatibility with previous versions of MultiMediaCards forward compatib...

Page 544: ...ction transfer their information directly within the command or response structure In addition some operations have a data token Data transfers to from SD SDIO memory cards are done in data blocks Data transfers to from MMC are done data blocks or streams Data transfers to from the CE ATA Devices are done in data blocks Figure 206 SDIO no response and no data operations Figure 207 SDIO multiple bl...

Page 545: ...d to host Data from host to card Stop command stops data transfer Optional cards Busy Needed for CE ATA Command Response Command Response Data block crc Busy Busy Data block crc Busy SDIO_CMD SDIO_D ai14738 Data stop operation From card to host Stop command stops data transfer Command Response Command Response Data transfer operation Data stream From host to card s Data from card to host SDIO_CMD ...

Page 546: ... configured by the host to use SDIO_D0 or SDIO_D 3 0 All data lines are operating in push pull mode SDIO_CMD has two operational modes Open drain for initialization only for MMCV3 31 or previous Push pull for command transfer SD SD I O card MMC4 2 use push pull drivers also for initialization SDIO_CK is the clock to the card one bit is transferred on both command and data lines with each clock cyc...

Page 547: ...SDIOCLK Adapter register block The adapter register block contains all system registers This block also generates the signals that clear the static flags in the multimedia card The clear signals are generated when 1 is written into the corresponding bit location in the SDIO Clear register Table 136 SDIO I O definitions Pin Direction Description SDIO_CK Output MultiMediaCard SD SDIO card clock This...

Page 548: ...bus output signals during the power off and power up phases The clock management subunit generates and controls the SDIO_CK signal The SDIO_CK output can use either the clock divide or the clock bypass mode The clock output is inactive after reset during the power off or power up phases if the power saving mode is enabled and the card bus is in the Idle state eight clock periods after both the com...

Page 549: ...ate machine CPSM sets the status flags and enters the Idle state if a response is not required If a response is required it waits for the response see Figure 215 on page 550 When the response is received the received CRC code and the internally generated code are compared and the appropriate status flags are set ai14805 CMD Status flag Control logic Command timer CRC Argument Shift register CMD Re...

Page 550: ... Send state This enables the data counter to trigger the stop command transmission Note The CPSM remains in the Idle state for at least eight SDIO_CK periods to meet the NCC and NRC timing constraints NCC is the minimum delay between two host commands and NRC is the minimum delay between the host command and the card response Idle Pend Send Wait Receive Last Data CPSM disabled Enabled and command ...

Page 551: ...e SDIO_CMD output is in the Hi Z state as shown in Figure 216 on page 551 Data on SDIO_CMD are synchronous with the rising edge of SDIO_CK Table shows the command format Response a response is a token that is sent from an addressed card or synchronously from all connected cards for MMC V3 31 or previous to the host as an answer to a previously received command Responses are transferred serially on...

Page 552: ...transmitter bit and the six reserved bits are not used in the CRC calculation The CRC checksum is a 7 bit value CRC 6 0 Remainder M x x7 G x G x x7 x3 1 M x start bit x39 last bit before CRC x0 or M x start bit x119 last bit before CRC x0 Table 138 Short response format Bit position Width Value Description 47 1 0 Start bit 46 1 0 Transmission bit 45 40 6 Command index 39 8 32 Argument 7 1 7 CRC7 o...

Page 553: ...the transfer direction send or receive the data path state machine DPSM moves to the Wait_S or Wait_R state when it is enabled Send the DPSM moves to the Wait_S state If there is data in the transmit FIFO the DPSM moves to the Send state and the data path subunit starts sending data to a card Receive the DPSM moves to the Wait_R state and waits for a start bit When it receives a start bit the DPSM...

Page 554: ...de when the data block counter reaches zero the DPSM waits until it receives the CRC code If the received code matches the internally generated CRC code the DPSM moves to the Wait_R state If not the CRC fail status flag is set and the DPSM moves to the Idle state In stream mode the DPSM receives data while the data counter is not zero When the counter is zero the remaining data in the shift regist...

Page 555: ...ives a positive CRC status it moves to the Wait_S state if SDIO_D0 is not low the card is not busy If a timeout occurs while the DPSM is in the Busy state it sets the data timeout flag and moves to the Idle state The data timer is enabled when the DPSM is in the Wait_R or Busy state and generates the data timeout error When transmitting data the timeout occurs if the DPSM stays in the Busy state f...

Page 556: ...ts TXACT when it transmits data Receive FIFO When the data path subunit receives a word of data it drives the data on the write databus The write pointer is incremented after the write operation completes On the read side the contents of the FIFO word pointed to by the current value of the read pointer is driven onto the read databus If the receive FIFO is disabled all status flags are deasserted ...

Page 557: ... using the DMA controller 1 Do the card identification process 2 Increase the SDIO_CK frequency 3 Select the card by sending CMD7 4 Configure the DMA2 as follows a Enable DMA2 controller and clear any pending interrupts b Program the DMA2_Channel4 source address register with the memory location s base address and DMA2_Channel4 destination address register with the SDIO_FIFO register address c Pro...

Page 558: ... 2 Card reset The GO_IDLE_STATE command CMD0 is the software reset command and it puts the MultiMediaCard and SD memory in the Idle state The IO_RW_DIRECT command CMD52 resets the SD I O card After power up or CMD0 all cards output bus drivers are in the high impedance state and the cards are initialized with a default relative card address RCA 0x0001 and with a default driver stage register setti...

Page 559: ...ll CID to the SDIO card host and enters the Identification state 7 The SDIO card host issues SET_RELATIVE_ADDR CMD3 to that card This new address is called the relative card address RCA it is shorter than the CID and addresses the card The assigned card changes to the Standby state it does not react to further identification cycles and its output switches from open drain to push pull 8 The SDIO ca...

Page 560: ...SD registers does not require a previous block length setting The transferred data is also CRC protected If a part of the CSD or CID register is stored in ROM then this unchangeable part must match the corresponding part of the receive buffer If this match fails then the card reports an error and does not change any register contents Some cards may require long and unpredictable times to write a b...

Page 561: ...ite MultiMediaCard only WRITE_DAT_UNTIL_STOP CMD20 starts the data transfer from the SDIO card host to the card beginning at the specified address and continuing until the SDIO card host issues a stop command When partial blocks are allowed CSD parameter WRITE_BL_PARTIAL is set the data stream can start and stop at any address within the card address space otherwise it can only start and stop at b...

Page 562: ... state for a stop command 22 4 8 Erase group erase and sector erase The erasable unit of the MultiMediaCard is the erase group The erase group is measured in write blocks which are the basic writable units of the card The size of the erase group is a card specific parameter and defined in the CSD The host can erase a contiguous range of Erase Groups Starting the erase process is a three step seque...

Page 563: ...SEND_WRITE_PROT command is similar to a single block read command The card sends a data block containing 32 write protection bits representing 32 write protect groups starting at the specified address followed by 16 CRC bits The address field in the write protect commands is a group address in byte units The card ignores all LSBs below the group size Mechanical write protect switch A mechanical sl...

Page 564: ...e is already selected 2 Define the block length SET_BLOCKLEN CMD16 to send given by the 8 bit card lock unlock mode the 8 bit PWD_LEN and the number of bytes of the new password When a password replacement is done the block size must take into account that both the old and the new passwords are sent with the command 3 Send LOCK UNLOCK CMD42 with the appropriate data block size on the data line inc...

Page 565: ...is set in the card status register When the password sent does not correspond in size and or content to the expected password the LOCK_UNLOCK_FAILED error bit is set in the card status register and the lock fails It is possible to set the password and to lock the card in the same sequence In this case the SDIO card host module performs all the required steps for setting the password see Setting th...

Page 566: ...e erased including the PWD and PWD_LEN fields and the card is no longer locked When any other bits are set the LOCK_UNLOCK_FAILED error bit is set in the card status register and the card retains all of its data and remains locked An attempt to use a force erase on an unlocked card fails and the LOCK_UNLOCK_FAILED error bit is set in the card status register 22 4 11 Card status register The respon...

Page 567: ...r the previously defined block length is illegal for the current command e g the host issues a write command the current block length is smaller than the maximum allowed value for the card and it is not allowed to write partial blocks C 28 ERASE_SEQ_ERROR 0 no error 1 error An error in the sequence of erase commands occurred C 27 ERASE_PARAM E X 0 no error 1 error An invalid selection of erase gro...

Page 568: ...ernal ECC A 13 ERASE_RESET 0 cleared 1 set An erase sequence was cleared before executing because an out of erase sequence command was received commands other than CMD35 CMD36 CMD38 or CMD13 C 12 9 CURRENT_STATE S R 0 Idle 1 Ready 2 Ident 3 Stby 4 Tran 5 Data 6 Rcv 7 Prg 8 Dis 9 Btst 10 15 reserved The state of the card when receiving the command If the command execution causes a state change it w...

Page 569: ...g command execution The SDIO card Host must poll the card by issuing the status command to read these bits Clear condition A according to the card current state B always related to the previous command Reception of a valid command clears it with a delay of one command C clear by read 3 AKE_SEQ_ERROR E R 0 no error 1 error Error in the sequence of the authentication process C 2 Reserved for applica...

Page 570: ...wing cards are currently defined 0000 Regular SD RD WR Card 0001 SD ROM Card In the future the 8 LSBs will be used to define different variations of an SD memory card each bit will define different SD types The 8 MSBs will be used to define SD Cards that do not comply with current SD physical layer specification A 479 448 SIZE_OF_PROTE CT ED_AREA S R Size of protected area See below See below A 44...

Page 571: ...ZE This 4 bit field indicates the AU size and the value can be selected in the power of 2 base from 16 KB Table 146 Speed class code field SPEED_CLASS Value definition 00h Class 0 01h Class 2 02h Class 4 03h Class 6 04h FFh Reserved Table 147 Performance move field PERFORMANCE_MOVE Value definition 00h Not defined 01h 1 MB sec 02h 02h 2 MB sec FEh 254 MB sec FFh Infinity Table 148 AU_SIZE field AU...

Page 572: ...s TERASE and the value indicates the erase timeout from offset when multiple AUs are being erased as specified by ERASE_SIZE The range of ERASE_TIMEOUT can be defined as up to 63 seconds and the card manufacturer can choose any combination of ERASE_SIZE and ERASE_TIMEOUT depending on the implementation Determining ERASE_TIMEOUT determines the ERASE_SIZE 09h 4 MB Ah Fh Reserved Table 149 Maximum AU...

Page 573: ...sistors on all data lines SDIO_D 3 0 The MultiMediaCard SD module samples the level of pin 8 SDIO_D IRQ into the interrupt detector only during the interrupt period At all other times the MultiMediaCard SD module ignores this value The interrupt period is applicable for both memory and I O operations The definition of the interrupt period for operations with single blocks is different from the def...

Page 574: ...neric commands are defined in the standard application specific commands ACMD and general commands GEN_CMD When the card receives the APP_CMD CMD55 command the card expects the next command to be an application specific command ACMDs have the same structure as regular MultiMediaCard commands and can have the same CMD number The card recognizes it as ACMD because it appears after APP_CMD CMD55 When...

Page 575: ... point data transfer command ADTC sent to the card that is selected includes a data transfer on the SDIO_D line s Command formats See Table 137 on page 551 for command formats Commands for the MultiMediaCard SD module Table 153 Block oriented write commands CMD index Type Argument Response format Abbreviation Description CMD23 ac 31 16 set to 0 15 0 number of blocks R1 SET_BLOCK_COUNT Defines the ...

Page 576: ... command indexes cannot be used in order to maintain backward compatibility with older versions of the MultiMediaCard CMD35 ac 31 0 data address R1 ERASE_GROUP_START Sets the address of the first erase group within a range to be selected for erase CMD36 ac 31 0 data address R1 ERASE_GROUP_END Sets the address of the last erase group within a continuous range to be selected for erase CMD37 Reserved...

Page 577: ...m in the interrupt mode CMD41 Reserved Table 156 I O mode commands continued CMD index Type Argument Response format Abbreviation Description Table 157 Lock card CMD index Type Argument Response format Abbreviation Description CMD42 adtc 31 0 stuff bits R1b LOCK_UNLOCK Sets resets the password or locks unlocks the card The size of the data block is set by the SET_BLOCK_LEN command CMD43 CMD54 Rese...

Page 578: ... register are sent as a response to CMD9 Only the bits 127 1 of the CID and CSD are transferred the reserved bit 0 of these registers is replaced by the end bit of the response The card indicates that an erase is in progress by holding MCDAT low The actual erase time may be quite long and the host may issue CMD7 to deselect the card 22 5 4 R3 OCR register Code length 48 bits The contents of the OC...

Page 579: ...tart bit 46 1 0 Transmission bit 45 40 6 111111 Reserved 39 8 32 X OCR register 7 1 7 1111111 Reserved 0 1 1 End bit Table 162 R4 response Bit position Width bits Value Description 47 1 0 Start bit 46 1 0 Transmission bit 45 40 6 111111 Reserved 39 8 Argument field 31 16 16 X RCA 15 8 8 X register address 7 0 8 X read register contents 7 1 7 1111111 CRC7 0 1 1 End bit Table 163 R4b response Bit po...

Page 580: ...he card responds with response R4 the host determines the card s configuration based on the data contained within the R4 response 22 5 7 R5 interrupt request Only for MultiMediaCard Code length 48 bits If the response is generated by the host the RCA field in the argument will be 0x0 22 5 8 R6 Only for SD I O The normal response to CMD3 by a memory device It is shown in Table 165 7 1 7 X Reserved ...

Page 581: ... Idle to Readwait In Readwait the DPSM drives SDIO_D2 to 0 after 2 SDIO_CK clock cycles In this state when you set the RWSTOP bit SDIO_DCTRL 9 the DPSM remains in Wait for two more SDIO_CK clock cycles to drive SDIO_D2 to 1 for one clock cycle in accordance with SDIO specification The DPSM then starts waiting again until it receives data from the card The DPSM will not start a readwait interval wh...

Page 582: ... the FIF0 is empty and the DPSM goes Idle automatically 22 6 4 SDIO interrupts SDIO interrupts are detected on the SDIO_D1 line once the SDIO_DCTRL 11 bit is set 22 7 CE ATA specific operations The following features are CE ATA specific operations sending the command completion signal disable to the CE ATA device receiving the command completion signal from the CE ATA device signaling the completi...

Page 583: ...he command state machine must be disabled It then becomes Idle and the CMD12 command can be sent No command completion disable signal is sent during the operation 22 8 HW flow control The HW flow control functionality is used to avoid FIFO underrun TX mode and overrun RX mode errors The behavior is to stop SDIO_CK and freeze SDIO state machines The data transfer is stalled while the FIFO is unable...

Page 584: ...k to card is stopped 01 Reserved 10 Reserved power up 11 Power on the card is clocked 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved HWFC_EN NEGEDGE WID BUS BYPASS PWRSAV CLKEN CLKDIV rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 15 Reserved always read as 0 Bit 14 HWFC_EN HW Flow Control enable 0b HW Flow Control is disabled 1b HW Flow Contro...

Page 585: ...K is divided according to the CLKDIV value before driving the SDIO_CK output signal 1 Enable bypass SDIOCLK directly drives the SDIO_CK output signal Bit 9 PWRSAV Power saving configuration bit For power saving the SDIO_CK clock output can be disabled when the bus is idle by setting PWRSAV 0 SDIO_CK clock is always enabled 1 SDIO_CK is only enabled when the bus is active Bit 8 CLKEN Clock enable b...

Page 586: ...MD61 Bit 13 nIEN not Interrupt Enable if this bit is 0 interrupts in the CE ATA device are enabled Bit 12 ENCMDcompl Enable CMD completion If this bit is set the command completion signal is enabled Bit 11 SDIOSuspend SD I O suspend command If this bit is set the command to be sent is a suspend command to be used only with SDIO card Bit 10 CPSMEN Command path state machine CPSM Enable bit If this ...

Page 587: ... 3 4 registers contain the status of a card which is part of the received response The Card Status size is 32 or 127 bits depending on the response type The most significant bit of the card status is received first The SDIO_RESP3 register LSB is always 0b 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RESPCMD r r r r r r Bits 31 6 Reserved always rea...

Page 588: ...tains the number of data bytes to be transferred The value is loaded into the data counter when data transfer starts Note For a block data transfer the value in the data length register must be a multiple of the block size see SDIO_DCTRL A data transfer must be written to the data timer register and the data length register before being written to the data control register 31 30 29 28 27 26 25 24 ...

Page 589: ...T bit is set 1 Enable for read wait stop if RWSTART bit is set Bit 8 RWSTART Read wait start If this bit is set read wait operation starts Bits 7 4 DBLOCKSIZE Data block size Define the data block length when the block data transfer mode is selected 0000 0 decimal lock length 20 1 byte 0001 1 decimal lock length 21 2 bytes 0010 2 decimal lock length 22 4 bytes 0011 3 decimal lock length 23 8 bytes...

Page 590: ...fer 1 Stream or SDIO multibyte data transfer on STM32F10xxx XL density devices Stream data transfer on STM32F10xxx high density devices Bit 1 DTDIR Data transfer direction selection 0 From controller to card 1 From card to controller 0 DTEN Data transfer enabled bit Data transfer starts if 1b is written to the DTEN bit Depending on the direction bit DTDIR the DPSM moves to the Wait_S Wait_R state ...

Page 591: ... 0 Bit 23 CEATAEND CE ATA command completion signal received for CMD61 Bit 22 SDIOIT SDIO interrupt received Bit 21 RXDAVL Data available in receive FIFO Bit 20 TXDAVL Data available in transmit FIFO Bit 19 RXFIFOE Receive FIFO empty Bit 18 TXFIFOE Transmit FIFO empty When HW Flow Control is enabled TXFIFOE signals becomes activated when the FIFO contains 2 words Bit 17 RXFIFOF Receive FIFO full W...

Page 592: ... 5 4 3 2 1 0 Reserved CEATAENDC SDIOITC Reserved DBCKENDC STBITERRC DATAENDC CMDSENTC CMDRENDC RXOVERRC TXUNDERRC DTIMEOUTC CTIMEOUTC DCRCFAILC CCRCFAILC rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 24 Reserved always read as 0 Bit 23 CEATAENDC CEATAEND flag clear bit Set by software to clear the CEATAEND flag 0 CEATAEND not cleared 1 CEATAEND cleared Bit 22 SDIOITC SDIOIT flag clear bit Set by ...

Page 593: ...R cleared Bit 4 TXUNDERRC TXUNDERR flag clear bit Set by software to clear TXUNDERR flag 0 TXUNDERR not cleared 1 TXUNDERR cleared Bit 3 DTIMEOUTC DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag 0 DTIMEOUT not cleared 1 DTIMEOUT cleared Bit 2 CTIMEOUTC CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag 0 CTIMEOUT not cleared 1 CTIMEOUT cleared Bit 1 DCRCFAILC DCR...

Page 594: ...and cleared by software to enable disable the interrupt generated when receiving the SDIO mode interrupt 0 SDIO Mode Interrupt Received interrupt disabled 1 SDIO Mode Interrupt Received interrupt enabled Bit 21 RXDAVLIE Data available in Rx FIFO interrupt enable Set and cleared by software to enable disable the interrupt generated by the presence of data available in Rx FIFO 0 Data available in Rx...

Page 595: ...Set and cleared by software to enable disable interrupt caused by data being transferred data transmit acting 0 Data transmit acting interrupt disabled 1 Data transmit acting interrupt enabled Bit 11 CMDACTIE Command acting interrupt enable Set and cleared by software to enable disable interrupt caused by a command being transferred command acting 0 Command acting interrupt disabled 1 Command acti...

Page 596: ...rrun error interrupt enable Set and cleared by software to enable disable interrupt caused by Tx FIFO underrun error 0 Tx FIFO underrun error interrupt disabled 1 Tx FIFO underrun error interrupt enabled Bit 3 DTIMEOUTIE Data timeout interrupt enable Set and cleared by software to enable disable interrupt caused by data timeout 0 Data timeout interrupt disabled 1 Data timeout interrupt enabled Bit...

Page 597: ...ds from address SDIO base 0x080 to SDIO base 0xFC Table 167 SDIO register map Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 SDIO_POWER Reserved PWRCTRL 0x04 SDIO_CLKCR Reserved HWFC_EN NEGEDGE WIDBUS BYPASS PWRSAV CLKEN CLKDIV 0x08 SDIO_ARG CMDARG 0x0C SDIO_CMD Reserved CE ATACMD nIEN ENCMDcompl SDIOSuspend CPSMEN WAITPEND WAITINT WAITRE...

Page 598: ...CFAILC CCRCFAILC 0x3C SDIO_MASK Reserved CEATAENDIE SDIOITIE RXDAVLIE TXDAVLIE RXFIFOEIE TXFIFOEIE RXFIFOFIE TXFIFOFIE RXFIFOHFIE TXFIFOHEIE RXACTIE TXACTIE CMDACTIE DBCKENDIE STBITERRIE DATAENDIE CMDSENTIE CMDRENDIE RXOVERRIE TXUNDERRIE DTIMEOUTIE CTIMEOUTIE DCRCFAILIE CCRCFAILIE 0x48 SDIO_FIFOCNT Reserved FIFOCOUNT 0x80 SDIO_FIFO FIF0Data Table 167 SDIO register map continued Offset Register 31 ...

Page 599: ...d STM32F102xx USB access line families only 23 1 USB introduction The USB peripheral implements an interface between a full speed USB 2 0 bus and the APB1 bus USB suspend resume are supported which allows to stop the device clocks for low power consumption 23 2 USB main features USB specification version 2 0 full speed compliant Configurable number of endpoints from 1 to 8 Cyclic redundancy check ...

Page 600: ...by the USB standard Transaction formatting is performed by the hardware including CRC generation and checking Each endpoint is associated with a buffer description block indicating where the endpoint related memory area is located how large it is or how many bytes must be transmitted When a token for a valid function endpoint pair is recognized by the USB peripheral the related data transfer if re...

Page 601: ...ock include synchronization pattern recognition bit stuffing CRC generation and checking PID verification generation and handshake evaluation It must interface with the USB transceivers and uses the virtual buffers provided by the packet buffer interface for local data storage This unit also generates signals according to USB peripheral events such as Start of Frame SOF USB_Reset Data errors etc a...

Page 602: ...y this scheme Register Mapper This block collects the various byte wide and bit wide registers of the USB peripheral in a structured 16 bit wide word set addressed by the APB1 APB1 Wrapper This provides an interface to the APB1 for the memory and register It also maps the whole USB peripheral in the APB1 address space Interrupt Mapper This block is used to select how the possible USB events can ge...

Page 603: ...er paragraph USB reset RESET interrupt When this event occurs the USB peripheral is put in the same conditions it is left by the system reset after the initialization described in the previous paragraph communication is disabled in all endpoint registers the USB peripheral will not respond to any packet As a response to the USB reset event the USB function must be enabled having as USB address 0 i...

Page 604: ...tion 23 5 3 Buffer descriptor table If an endpoint is unidirectional and it is neither an Isochronous nor a double buffered bulk only one packet buffer is required the one related to the supported transfer direction Other table locations related to unsupported transfer directions or unused endpoints are available to the user Isochronous and double buffered bulk endpoints have special handling of p...

Page 605: ...n_TX locations inside buffer descriptor table entry related to the addressed endpoint The content of these locations is stored in its internal 16 bit registers ADDR and COUNT not accessible by software The packet memory is accessed again to read the first word to be transmitted Refer to Structure and usage of packet buffers on page 603 and starts sending a DATA0 or DATA1 PID according to USB_EPnR ...

Page 606: ...USB peripheral recovers from reception errors and remains ready for the next transaction to come If the addressed endpoint is not valid a NAK or STALL handshake packet is sent instead of the ACK according to bits STAT_RX in the USB_EPnR register and no data is written in the reception memory buffers Reception memory buffer locations are written starting from the address contained in the ADDRn_RX f...

Page 607: ...ets a STALL as a status stage While enabling the last data stage the opposite direction should be set to NAK so that if the host reverses the transfer direction to perform the status stage immediately it is kept waiting for the completion of the control operation If the control operation completes successfully the software will change NAK to VALID otherwise to STALL At the same time if the status ...

Page 608: ...ed buffer management requires the usage of all 4 buffer description table locations hosting the address pointer and the length of the allocated memory buffers the USB_EPnR registers used to implement double buffered bulk endpoints are forced to be used as unidirectional ones Therefore only one STAT bit pair must be set at a value different from 00 Disabled STAT_RX if the double buffered bulk endpo...

Page 609: ...depending on the enabled direction At the same time the affected DTOG bit in the USB_EPnR register is hardware toggled making the USB peripheral buffer swapping completely software independent Unlike common transactions and the first one after Table 168 Double buffering buffer flag definition Buffer flag Transmission endpoint Reception endpoint DTOG DTOG_TX USB_EPnRbit 6 DTOG_RX USB_EPnRbit 14 SW_...

Page 610: ...equiring a fixed and accurate data production consume frequency defining this kind of traffic as Isochronous Typical examples of this data are audio samples compressed video streams and in general any sort of sampled data having strict requirements for the accuracy of delivered frequency When an endpoint is defined to be isochronous during the enumeration phase the host allocates in the frame the ...

Page 611: ...pheral state called SUSPEND in which the average current drawn from the USB bus must not be greater than 500 μA This requirement is of fundamental importance for bus powered devices while self powered devices are not required to comply to this strict power consumption constraint In suspend mode the host PC sends the notification to not send any traffic on the USB bus for more than 3mS since a SOF ...

Page 612: ...ile the USB peripheral is suspended clears the LP_MODE bit in USB_CNTR register asynchronously Even if this event can trigger an WKUP interrupt if enabled the use of an interrupt response routine must be carefully evaluated because of the long latency due to system clock restart to have the shorter latency before re activating the nominal clock it is suggested to put the resume procedure just afte...

Page 613: ... in suspend mode setting the FSUSP bit in USB_CNTR register to 1 23 5 USB registers The USB peripheral registers can be divided into the following groups Common Registers Interrupt and Control registers Endpoint Registers Endpoint configuration and status Buffer Descriptor Table Location of packet memory used to locate data buffers All register addresses are expressed as offsets with respect to th...

Page 614: ...13 ERRM Error interrupt mask 0 ERR Interrupt disabled 1 ERR Interrupt enabled an interrupt request is generated when the corresponding bit in the USB_ISTR register is set Bit 12 WKUPM Wakeup interrupt mask 0 WKUP Interrupt disabled 1 WKUP Interrupt enabled an interrupt request is generated when the corresponding bit in the USB_ISTR register is set Bit 11 SUSPM Suspend mode interrupt mask 0 Suspend...

Page 615: ...nd mode power constraints require that all static power dissipation is avoided except the one required to supply the external pull up resistor This condition should be entered when the application is ready to stop all system clocks or reduce their frequency in order to meet the power consumption requirements of the USB suspend condition The USB activity during the suspend mode WKUP event asynchron...

Page 616: ...n is activated independently from the CTRM bit in the USB_CNTR register Both interrupt conditions remain active until software clears the pending bit in the corresponding USB_EPnR register the CTR bit is actually a read only bit For endpoint related interrupts the software can use the Direction of Transaction DIR and EP_ID read only bits to identify which endpoint made the last interrupt request a...

Page 617: ... Check error One of the received CRCs either in the token or in the data was wrong BST Bit Stuffing error A bit stuffing error was detected anywhere in the PID data and or CRC FVIO Framing format Violation A non standard frame was received EOP not in the right place wrong token sequence etc The USB software can usually ignore errors since the USB peripheral and the PC host manage retransmission in...

Page 618: ... missing SOF packets occur while the Suspend Timer is not yet locked This bit is read write but only 0 can be written and writing 1 has no effect Bits 7 5 Reserved Bit 4 DIR Direction of transaction This bit is written by the hardware according to the direction of the successful transaction which generated the interrupt request If DIR bit 0 CTR_TX bit is set in the USB_EPnR register related to the...

Page 619: ...suspend routines to help determining the wakeup event Bit 13 LCK Locked This bit is set by the hardware when at least two consecutive SOF packets have been received after the end of an USB reset condition or after the end of an USB resume sequence Once locked the frame timer remains in this state until an USB reset or USB suspend event occurs Bits 12 11 LSOF 1 0 Lost SOF These bits are written by ...

Page 620: ...ng the enumeration process Both this field and the Endpoint Address EA field in the associated USB_EPnR register must match with the information contained in a USB token in order to handle a transaction to the required endpoint 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BTABLE 15 3 Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15 3 BTABLE 15 3 Buffer table These bits contain the start address of...

Page 621: ...h bit FRES in the CTLR register except the CTR_RX and CTR_TX bits which are kept unchanged to avoid missing a correct packet notification immediately followed by an USB reset event Each endpoint has its USB_EPnR register where n is the endpoint identifier Read modify write cycles on these registers should be avoided because between the read and the write operations some bits could be set by the ha...

Page 622: ...to initialize its value mandatory when the endpoint is not a control one or to force specific data toggle packet buffer usage When the application software writes 0 the value of DTOG_RX remains unchanged while writing 1 makes the bit value toggle This bit is read write but it can be only toggled by writing 1 Bits 13 12 STAT_RX 1 0 Status bits for reception transfers These bits contain information ...

Page 623: ... errors during control transfers and its usage is intended for control endpoints only When STATUS_OUT is reset OUT transactions can have any number of bytes as required Bit 7 CTR_TX Correct Transfer for transmission This bit is set by the hardware when an IN transaction is successfully completed on this endpoint the software can only clear this bit If the CTRM bit in the USB_CNTR register is set a...

Page 624: ...n only be VALID or DISABLED Therefore the hardware cannot change the status of the endpoint after a successful transaction If the software sets the STAT_TX bits to STALL or NAK for an Isochronous endpoint the USB peripheral behavior is not defined These bits are read write but they can be only toggled by writing 1 Bits 3 0 EA 3 0 Endpoint address Software must write in this field the 4 bit address...

Page 625: ... be multiplied by two The first packet memory location is located at 0x4000 6000 The buffer descriptor table entry associated with the USB_EPnR registers is described below A thorough explanation of packet buffers and the buffer descriptor table usage can be found in Structure and usage of packet buffers on page 603 Transmission buffer address n USB_ADDRn_TX Address offset USB_BTABLE n 16 USB loca...

Page 626: ...d by the USB peripheral Bits 9 0 COUNTn_TX 9 0 Transmission byte count These bits contain the number of bytes to be transmitted by the endpoint associated with the USB_EPnR register at the next IN token addressed to it 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved COUNTn_TX_1 9 0 rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved COUNTn_TX_0 9 0 rw rw rw rw rw ...

Page 627: ...th the following content 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BLSIZE NUM_BLOCK 4 0 COUNTn_RX 9 0 rw rw rw rw rw rw r r r r r r r r r r Bit 15 BL_SIZE BLock size This bit selects the size of memory block used to define the allocated buffer area If BL_SIZE 0 the memory block is 2 byte large which is the minimum block allowed in a word wide memory With this block size the allocated buffer size range...

Page 628: ...erved CTR_RX DTOG_RX STAT_ RX 1 0 SETUP EP TYPE 1 0 EP_KIND CTR_TX DTOG_TX STAT_ TX 1 0 EA 3 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x04 USB_EP1R Reserved CTR_RX DTOG_RX STAT_ RX 1 0 SETUP EP TYPE 1 0 EP_KIND CTR_TX DTOG_TX STAT_ TX 1 0 EA 3 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x08 USB_EP2R Reserved CTR_RX DTOG_RX STAT_ RX 1 0 SETUP EP TYPE 1 0 EP_KIND CTR_TX DTOG_TX STAT_ TX 1 0 ...

Page 629: ... Reserved 0x40 USB_CNTR Reserved CTRM PMAOVRM ERRM WKUPM SUSPM RESETM SOFM ESOFM Reserved RESUME FSUSP LPMODE PDWN FRES Reset value 0 0 0 0 0 0 0 0 0 0 0 1 1 0x44 USB_ISTR Reserved CTR PMAOVR ERR WKUP SUSP RESET SOF ESOF Reserved DIR EP_ID 3 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0x48 USB_FNR Reserved RXDP RXDM LCK LSOF 1 0 FN 10 0 Reset value 0 0 0 0 0 x x x x x x x x x x x 0x4C USB_DADDR Reserv...

Page 630: ...32F103xx performance line only 24 1 bxCAN introduction The Basic Extended CAN peripheral named bxCAN interfaces the CAN network It supports the CAN protocols version 2 0A and B It has been designed to manage a high number of incoming messages efficiently with a minimum CPU load It also meets the priority requirements for transmit messages For safety critical applications the CAN controller provide...

Page 631: ... in the same application but not at the same time 24 3 bxCAN general description In today s CAN applications the number of nodes in a network is increasing and often several networks are linked together via gateways Typically the number of messages in the system and thus to be handled by each node has significantly increased In addition to the application messages Network Management and Diagnostic...

Page 632: ...upts Get diagnostic information 24 3 3 Tx mailboxes Three transmit mailboxes are provided to the software for setting up messages The transmission Scheduler decides which mailbox has to be transmitted first 24 3 4 Acceptance filters In Connectivity line devices the bxCAN provides 28 scalable configurable identifier filter banks for selecting the incoming messages the software needs and discarding ...

Page 633: ... Acceptance Filters 3 2 1 Filter 0 27 Transmission Scheduler Mailbox 0 1 2 Receive FIFO 1 Mailbox 0 1 2 Receive FIFO 0 Mailbox 0 1 2 Tx Mailboxes Transmission Scheduler Mailbox 0 1 2 Receive FIFO 1 Mailbox 0 1 2 Receive FIFO 0 Mailbox 0 1 2 Tx Mailboxes Memory Access Controller Master Control Master Status Rx FIFO 0 Status Rx FIFO 1 Status Error Status Bit Timing Interrupt Enable Control Status Co...

Page 634: ...vation bits in the CAN_FA1R register If a filter bank is not used it is recommended to leave it non active leave the corresponding FACT bit cleared 24 4 2 Normal mode Once the initialization has been done the software must request the hardware to enter Normal mode to synchronize on the CAN bus and start reception and transmission Entering Normal mode is done by clearing the INRQ bit in the CAN_MCR...

Page 635: ...gister 2 SYNC The state during which bxCAN waits until the CAN bus is idle meaning 11 consecutive recessive bits have been monitored on CANRX 24 5 Test mode Test mode can be selected by the SILM and LBKM bits in the CAN_BTR register These bits must be configured while bxCAN is in Initialization mode Once test mode has been selected the INRQ bit in the CAN_MCR register must be reset to enter Normal...

Page 636: ...cknowledge slot of a data remote frame in Loop Back Mode In this mode the bxCAN performs an internal feedback from its Tx output to its Rx input The actual value of the CANRX input pin is disregarded by the bxCAN The transmitted messages can be monitored on the CANTX pin 24 5 3 Loop back combined with silent mode It is also possible to combine Loop Back mode and Silent mode by setting the LBKM and...

Page 637: ... Immediately after the TXRQ bit has been set the mailbox enters pending state and waits to become the highest priority mailbox see Transmit Priority As soon as the mailbox has the highest priority it will be scheduled for transmission The transmission of the message of the scheduled mailbox will start enter transmit state when the CAN bus becomes idle Once the mailbox has been successfully transmi...

Page 638: ...rent transmission Nonautomatic retransmission mode This mode has been implemented in order to fulfil the requirement of the Time Triggered Communication option of the CAN standard To configure the hardware in this mode the NART bit in the CAN_MCR register must be set In this mode each transmission is started only once If the first attempt fails due to an arbitration loss or an error the hardware w...

Page 639: ...e CPU load simplify the software and guarantee data consistency the FIFO is managed completely by hardware The application accesses the messages stored in the FIFO through the FIFO output mailbox Valid message A received message is considered as valid when it has been received correctly according to the CAN protocol no error until the last but one bit of the EOF field and It passed through the ide...

Page 640: ...CAN_MCR register cleared the last message stored in the FIFO will be overwritten by the new incoming message In this case the latest messages will be always available to the application If the FIFO lock function is enabled RFLM bit in the CAN_MCR register set the most recent message will be discarded and the software will have the three oldest messages in the FIFO available Reception related inter...

Page 641: ...fier and a mask two identifiers are specified doubling the number of single identifiers All bits of the incoming identifier must match the bits specified in the filter registers Filter bank scale and mode configuration The filter banks are configured by means of the corresponding CAN_FMR register To configure a filter bank it must be deactivated by clearing the FACT bit in the CAN_FAR register The...

Page 642: ...ccount the activation state of the filter banks In addition two independent numbering schemes are used one for each FIFO Refer to Figure 230 for an example One 32 Bit Filter Identifier Mask Two 16 Bit Filters Identifier Mask CAN_FxR1 31 24 CAN_FxR2 31 24 CAN_FxR1 15 8 CAN_FxR1 31 24 CAN_FxR1 7 0 CAN_FxR1 23 16 x filter bank number FSCx 1 FSCx 0 1 These bits are located in the CAN_FS1R register Fil...

Page 643: ... equal scale priority is given to the Identifier List mode over the Identifier Mask mode For filters of equal scale and mode priority is given by the filter number the lower the number the higher the priority 9 8 ID List 32 bit ID Mask 32 bit ID List 16 bit ID List 32 bit Deactivated ID Mask 16 bit ID List 32 bit Filter 0 1 3 5 6 9 ID Mask 32 bit 13 FIFO0 Filter 0 1 2 3 4 5 6 7 10 11 12 13 ID Mask...

Page 644: ... discarded by hardware without disturbing the software 24 7 5 Message storage The interface between the software and the hardware for the CAN messages is implemented by means of mailboxes A mailbox contains all information related to a message identifier data control status and time stamp information Transmit mailbox The software sets up the message to be transmitted in an empty transmit mailbox T...

Page 645: ...e available The filter match index is stored in the MFMI field of the CAN_RDTxR register The 16 bit time stamp value is stored in the TIME 15 0 field of CAN_RDTxR Figure 232 CAN error state diagram Table 178 Transmit mailbox mapping Offset to transmit mailbox base address Register name 0 CAN_TIxR 4 CAN_TDTxR 8 CAN_TDLxR 12 CAN_TDHxR Table 179 Receive mailbox mapping Offset to receive mailbox base ...

Page 646: ...the recovering sequence automatically after it has entered Bus Off state If ABOM is cleared the software must initiate the recovering sequence by requesting bxCAN to enter and to leave initialization mode Note In initialization mode bxCAN does not monitor the CANRX signal therefore it cannot complete the recovery sequence To recover bxCAN must be in normal mode 24 7 7 Bit timing The bit timing log...

Page 647: ... moved earlier As a safeguard against programming errors the configuration of the Bit Timing Register CAN_BTR is only possible while the device is in Standby mode Note For a detailed description of the CAN bit timing and resynchronization mechanism please refer to the ISO 11898 standard Figure 233 Bit timing SYNC_SEG BIT SEGMENT 1 BS1 BIT SEGMENT 2 BS2 NOMINAL BIT TIME 1 x tq tBS1 tBS2 SAMPLE POIN...

Page 648: ...rame Inter Frame Space Inter Frame Space or Overload Frame Inter Frame Space Inter Frame Space or Overload Frame Notes 0 N 8 SOF Start Of Frame ID Identifier RTR Remote Transmission Request IDE Identifier Extension Bit r0 Reserved Bit DLC Data Length Code CRC Cyclic Redundancy Code Error flag 6 dominant bits if node is error active else 6 recessive bits Suspend transmission applies to error passiv...

Page 649: ...er are not 00 FIFO0 full condition FULL0 bit in the CAN_RF0R register set FIFO0 overrun condition FOVR0 bit in the CAN_RF0R register set The FIFO 1 interrupt can be generated by the following events Reception of a new message FMP1 bits in the CAN_RF1R register are not 00 FIFO1 full condition FULL1 bit in the CAN_RF1R register set FIFO1 overrun condition FOVR1 bit in the CAN_RF1R register set RQCP0...

Page 650: ...ox can be only modified by software while it is in empty state refer to Figure 227 Transmit mailbox states The filter values can be modified either deactivating the associated filter banks or by setting the FINIT bit Moreover the modification of the filter configuration scale mode and FIFO assignment in CAN_FMxR CAN_FSxR and CAN_FFAR registers can only be done when the filter initialization mode i...

Page 651: ...tware request by clearing the SLEEP bit of the CAN_MCR register 1 The Sleep mode is left automatically by hardware on CAN message detection The SLEEP bit of the CAN_MCR register and the SLAK bit of the CAN_MSR register are cleared by hardware Bit 4 NART No automatic retransmission 0 The CAN hardware will automatically retransmit the message until it has been successfully transmitted according to t...

Page 652: ... TXM Reserved SLAKI WKUI ERRI SLAK INAK r r r r rc_w1 rc_w1 rc_w1 r r Bits 31 12 Reserved forced by hardware to 0 Bit 11 RX CAN Rx signal Monitors the actual value of the CAN_RX Pin Bit 10 SAMP Last sample point The value of RX on the last sample point current received bit value Bit 9 RXM Receive mode The CAN hardware is currently receiver Bit 8 TXM Transmit mode The CAN hardware is currently tran...

Page 653: ...CAN hardware is now in initialization mode This bit acknowledges the initialization request from the software set INRQ bit in CAN_MCR register This bit is cleared by hardware when the CAN hardware has left the initialization mode to be synchronized on the CAN bus To be synchronized the hardware has to monitor a sequence of 11 consecutive recessive bits on the CAN RX signal 31 30 29 28 27 26 25 24 ...

Page 654: ...t after each transmission attempt 0 The previous transmission failed 1 The previous transmission was successful This bit is set by hardware when the transmission request on mailbox 2 has been completed successfully Please refer to Figure 227 Bit 16 RQCP2 Request completed mailbox2 Set by hardware when the last request transmit or abort has been performed Cleared by software writing a 1 or by hardw...

Page 655: ...e hardware updates this bit after each transmission attempt 0 The previous transmission failed 1 The previous transmission was successful This bit is set by hardware when the transmission request on mailbox 1 has been completed successfully Please refer to Figure 227 Bit 0 RQCP0 Request completed mailbox0 Set by hardware when the last request transmit or abort has been performed Cleared by softwar...

Page 656: ... rc_w1 r r Bits 31 6 Reserved forced by hardware to 0 Bit 5 RFOM1 Release FIFO 1 output mailbox Set by software to release the output mailbox of the FIFO The output mailbox can only be released when at least one message is pending in the FIFO Setting this bit when the FIFO is empty has no effect If at least two messages are pending in the FIFO the software has to release the output mailbox to acce...

Page 657: ...t will be generation when an error condition is pending in the CAN_ESR Bits 14 12 Reserved forced by hardware to 0 Bit 11 LECIE Last error code interrupt enable 0 ERRI bit will not be set when the error code in LEC 2 0 is set by hardware on error detection 1 ERRI bit will be set when the error code in LEC 2 0 is set by hardware on error detection Bit 10 BOFIE Bus off interrupt enable 0 ERRI bit wi...

Page 658: ... enable 0 No interrupt when RQCPx bit is set 1 Interrupt generated when RQCPx bit is set Note Refer to Section 24 8 bxCAN interrupts 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 REC 7 0 TEC 7 0 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LEC 2 0 Res BOFF EPVF EWGF rw rw rw r r r Bits 31 24 REC 7 0 Receive error counter The implementing part of the fault confin...

Page 659: ...CRC Error 111 Set by software Bit 3 Reserved forced by hardware to 0 Bit 2 BOFF Bus off flag This bit is set by hardware when it enters the bus off state The bus off state is entered on TEC overflow greater than 255 refer to Section 24 7 6 on page 646 Bit 1 EPVF Error passive flag This bit is set by hardware when the Error Passive limit has been reached Receive Error Counter or Transmit Error Coun...

Page 660: ... Resynchronization jump width These bits define the maximum number of time quanta the CAN hardware is allowed to lengthen or shorten a bit to perform the resynchronization tRJW tCAN x SJW 1 0 1 Bit 23 Reserved forced by hardware to 0 Bits 22 20 TS2 2 0 Time segment 2 These bits define the number of time quanta in Time Segment 2 tBS2 tCAN x TS2 2 0 1 Bits 19 16 TS1 3 0 Time segment 1 These bits def...

Page 661: ...11 10 9 8 7 6 5 4 3 2 1 0 EXID 12 0 IDE RTR TXRQ rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 21 STID 10 0 EXID 28 18 Standard identifier or extended identifier The standard identifier or the MSBs of the extended identifier depending on the IDE bit value Bit 20 3 EXID 17 0 Extended identifier The LSBs of the extended identifier Bit 2 IDE Identifier extension This bit defines the identif...

Page 662: ... at the SOF transmission Bits 15 9 Reserved Bit 8 TGT Transmit global time This bit is active only when the hardware is in the Time Trigger Communication mode TTCM bit of the CAN_MCR register is set 0 Time stamp TIME 15 0 is not sent 1 Time stamp TIME 15 0 value is sent in the last two data bytes of the 8 byte message TIME 7 0 in data byte 7 and TIME 15 8 in data byte 6 replacing the data written ...

Page 663: ...ts 31 24 DATA3 7 0 Data byte 3 Data byte 3 of the message Bits 23 16 DATA2 7 0 Data byte 2 Data byte 2 of the message Bits 15 8 DATA1 7 0 Data byte 1 Data byte 1 of the message Bits 7 0 DATA0 7 0 Data byte 0 Data byte 0 of the message A message can contain from 0 to 8 data bytes and starts with byte 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATA7 7 0 DATA6 7 0 rw rw rw rw rw rw rw rw rw rw...

Page 664: ... 11 10 9 8 7 6 5 4 3 2 1 0 EXID 12 0 IDE RTR Res r r r r r r r r r r r r r r r Bits 31 21 STID 10 0 EXID 28 18 Standard identifier or extended identifier The standard identifier or the MSBs of the extended identifier depending on the IDE bit value Bits 20 3 EXID 17 0 Extended identifier The LSBs of the extended identifier Bit 2 IDE Identifier extension This bit defines the identifier type of messa...

Page 665: ...r r r r r r r r r r r r Bits 31 16 TIME 15 0 Message time stamp This field contains the 16 bit timer value captured at the SOF detection Bits 15 8 FMI 7 0 Filter match index This register contains the index of the filter the message stored in the mailbox passed through For more details on identifier filtering please refer to Section 24 7 4 Identifier filtering on page 640 Filter Match Index paragr...

Page 666: ...r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA1 7 0 DATA0 7 0 r r r r r r r r r r r r r r r r Bits 31 24 DATA3 7 0 Data Byte 3 Data byte 3 of the message Bits 23 16 DATA2 7 0 Data Byte 2 Data byte 2 of the message Bits 15 8 DATA1 7 0 Data Byte 1 Data byte 1 of the message Bits 7 0 DATA0 7 0 Data Byte 0 Data byte 0 of the message A message can contain from 0 to 8 data bytes an...

Page 667: ...0 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FINIT rw Reserved CAN2SB 5 0 Reserved FINIT rw rw rw rw rw rw rw Bits 31 14 Reserved forced to reset value Bits 13 8 CAN2SB 5 0 CAN2 start bank These bits are set and cleared by software They define the start bank for the CAN2 interface Slave in the range 1 to 27 Note These bits are available in connectivity line devices only an...

Page 668: ...0 FBM9 FBM8 FBM7 FBM6 FBM5 FBM4 FBM3 FBM2 FBM1 FBM0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 28 Reserved Forced to 0 by hardware Bits 27 0 FBMx Filter mode Mode of the registers of Filter x 0 Two 32 bit registers of filter bank x are in Identifier Mask mode 1 Two 32 bit registers of filter bank x are in Identifier List mode Note Bits 27 14 are available in connectivity line devices ...

Page 669: ...The message passing through this filter will be stored in the specified FIFO 0 Filter assigned to FIFO 0 1 Filter assigned to FIFO 1 Note Bits 27 14 are available in connectivity line devices only and are reserved otherwise 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved FACT27 FACT26 FACT25 FACT24 FACT23 FACT22 FACT21 FACT20 FACT19 FACT18 FACT17 FACT16 rw rw rw rw rw rw rw rw rw rw rw rw...

Page 670: ...e same bit mapping as in identifier list mode For the register mapping addresses of the filter banks please refer to the Table 180 on page 671 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FB31 FB30 FB29 FB28 FB27 FB26 FB25 FB24 FB23 FB22 FB21 FB20 FB19 FB18 FB17 FB16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FB15 FB14 FB13 FB12 FB11 FB10 FB9 FB8 FB7 F...

Page 671: ...R1 FULL1 Reserved FMP1 1 0 Reset value 0 0 0 0 0 0x014 CAN_IER Reserved SLKIE WKUIE ERRIE Reserved LECIE BOFIE EPVIE EWGIE Reserved FOVIE1 FFIE1 FMPIE1 FOVIE0 FFIE0 FMPIE0 TMEIE Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x018 CAN_ESR REC 7 0 TEC 7 0 Reserved LEC 2 0 Reserved BOFF EPVF EWGF Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x01C CAN_BTR SILM LBKM Reserved SJW 1 0 Reserved TS2 2...

Page 672: ...8 EXID 17 0 IDE RTR Reserved Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x1B4 CAN_RDT0R TIME 15 0 FMI 7 0 Reserved DLC 3 0 Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x1B8 CAN_RDL0R DATA3 7 0 DATA2 7 0 DATA1 7 0 DATA0 7 0 Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x1BC CAN_RDH0R DATA7 7 0 DATA6 7 0 DATA5 7 0 ...

Page 673: ...0 0x220 Reserved 0x224 0x23F Reserved 0x240 CAN_F0R1 FB 31 0 Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x244 CAN_F0R2 FB 31 0 Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x248 CAN_F1R1 FB 31 0 Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0x24C CAN_F1R2 FB 31 0 Reset value x x x x x x x x x x x x x x x ...

Page 674: ...ication with external devices The interface can be configured as the master and in this case it provides the communication clock SCK to the external slave device The interface is also capable of operating in multimaster configuration It may be used for a variety of purposes including Simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using ...

Page 675: ...mmunication for both master and slave NSS management by hardware or software for both master and slave dynamic change of master slave operations Programmable clock polarity and phase Programmable data order with MSB first or LSB first shifting Dedicated transmission and reception flags with interrupt capability SPI bus busy status flag Hardware CRC feature for reliable communication CRC value can ...

Page 676: ... reception mode master and slave 16 bit register for transmission and reception with one data register for both channel sides Supported I2S protocols I2S Phillips standard MSB Justified standard Left Justified LSB Justified standard Right Justified PCM standard with short and long frame synchronization on 16 bit channel frame or 16 bit data frame extended to 32 bit channel frame Data direction is ...

Page 677: ...can be driven by standard IO ports on the master device The NSS pin may also be used as an output if enabled SSOE bit and driven low if the SPI is in master configuration In this manner all NSS pins from devices connected to the Master NSS pin see a low level and become slaves when they are configured in NSS hardware mode When configured in master mode with NSS configured as an input MSTR 1 and SS...

Page 678: ...bled by setting the SSM bit in the SPI_CR1 register see Figure 238 In this mode the external NSS pin is free for other application uses and the internal NSS signal level is driven by writing to the SSI bit in the SPI_CR1 register Hardware NSS mode there are two cases NSS output is enabled when the STM32F10xxx are operates as a Master and the NSS output is enabled through the SSOE bit in the SPI_CR...

Page 679: ...edge if CPOL bit is set rising edge if CPOL bit is reset is the MSBit capture strobe Data are latched on the occurrence of the first clock transition The combination of the CPOL clock polarity and CPHA clock phase bits selects the data capture clock edge Figure 239 shows an SPI transfer with the four combinations of the CPHA and CPOL bits The diagram may be interpreted as a master or slave timing ...

Page 680: ...CK pin from the master device The value set in the BR 2 0 bits in the SPI_CR1 register does not affect the data transfer rate Note It is recommended to enable the SPI slave before the master sends the clock If not undesired data transmission might occur The data register of the slave needs to be ready before the first edge of the communication clock or before the end of the ongoing communication I...

Page 681: ...he MOSI pin is a data input and the MISO pin is a data output Transmit sequence The data byte is parallel loaded into the Tx buffer during a write cycle The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin The remaining bits the 7 bits in 8 bit data frame format and the 15 bits in 16 bit data frame format are loaded i...

Page 682: ...is written in the Tx Buffer The data byte is parallel loaded into the shift register from the internal bus during the first bit transmission and then shifted out serially to the MOSI pin MSB first or LSB first depending on the LSBFIRST bit in the SPI_CR1 register The TXE flag is set on the transfer of data from the Tx Buffer to the shift register and an interrupt is generated if the TXEIE bit in t...

Page 683: ...e used as a general purpose IO In this case the application just needs to ignore the Rx buffer if the data register is read it does not contain the received value In receive only mode the application can disable the SPI output function by setting the RXONLY bit in the SPI_CR2 register In this case it frees the transmit IO pin MOSI in master mode or MISO in slave mode so it can be used for other pu...

Page 684: ...t transmission and then shifted out serially to the MOSI pin No data are received In bidirectional mode when receiving BIDIMODE 1 and BIDIOE 0 The sequence begins as soon as SPE 1 and BIDIOE 0 The received data on the MOSI pin are shifted in serially to the 8 bit shift register and then parallel loaded into the SPI_DR register Rx buffer The transmitter is not activated and no data are shifted out ...

Page 685: ...PI_DR register Note The software must ensure that the TXE flag is set to 1 before attempting to write to the Tx buffer Otherwise it overwrites the data previously written to the Tx buffer The RXNE flag Rx buffer not empty is set on the last sampling clock edge when the data are transferred from the shift register to the Rx buffer It indicates that data are ready to be read from the SPI_DR register...

Page 686: ...2 from SPI_ DR software waits until RXNE 1 and reads 0xA3 from SPI_DR b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 cleared by software ai17343 0xF1 set by cleared by software MISO MOSI in Tx buffer DATA 1 0xA1 TXE flag 0xF2 BSY flag 0xF3 software writes 0xF1 into SPI_DR software waits until TXE 1 and...

Page 687: ...ions there is a 2 APB clock period delay between the write operation to SPI_DR and the BSY bit setting As a consequence in transmit only mode it is mandatory to wait first until TXE is set and then until BSY is cleared after writing the last data 2 After transmitting two data items in transmit only mode the OVR flag is set in the SPI_SR register since the received data are never read Figure 242 TX...

Page 688: ...ster device drives NSS low and generates the SCK clock 3 Wait until RXNE 1 and read the SPI_DR register to get the received data this clears the RXNE bit Repeat this operation for each data item to be received This procedure can also be implemented using dedicated interrupt subroutines launched at each rising edge of the RXNE flag Note If it is required to disable the SPI after the last transfer f...

Page 689: ... BSY bit is never cleared between each data transfer On the contrary if the software is not fast enough this can lead to some discontinuities in the communication In this case the BSY bit is cleared between each data transmission see Figure 245 In Master receive only mode RXONLY 1 the communication is always continuous and the BSY flag is always read at 1 In slave mode the continuity of the commun...

Page 690: ... be transferred is written to the SPI_DR At the end of this last data transfer the SPI_TXCRCR value is transmitted In receive only mode and when the transfers are managed by software CPU mode it is necessary to write the CRCNEXT bit after the second last data has been received The CRC is received just after the last data reception and the CRC check is then performed At the end of data and CRC tran...

Page 691: ...n slave mode be careful to enable CRC calculation only when the clock is stable that is when the clock is in the steady state If not a wrong CRC calculation may be done In fact the CRC is sensitive to the SCK slave input clock as soon as CRCEN is set and this whatever the value of the SPE bit With high bitrate frequencies be careful when transmitting the CRC As the number of used CPU cycles has to...

Page 692: ...re the BSY flag is kept low during reception The BSY flag is useful to detect the end of a transfer if the software wants to disable the SPI and enter Halt mode or disable the peripheral clock This avoids corrupting the last transfer For this the procedure described below must be strictly respected The BSY flag is also useful to avoid write collisions in a multimaster system The BSY flag is set wh...

Page 693: ...tten into the SPI_DR register 1 Wait until TXE 1 2 Then wait until BSY 0 3 Disable the SPI SPE 0 and eventually enter the Halt mode or disable the peripheral clock In master unidirectional receive only mode MSTR 1 BIDIMODE 0 RXONLY 1 or bidirectional receive mode MSTR 1 BIDIMODE 1 BIDIOE 0 This case must be managed in a particular way to ensure that the SPI does not initiate a new transfer 1 Wait ...

Page 694: ...to be transmitted flag TCIF is set in the DMA_ISR register the BSY flag can be monitored to ensure that the SPI communication is complete This is required to avoid corrupting the last transmission before disabling the SPI or entering the Stop mode The software must first wait until TXE 1 and then until BSY 0 Note During discontinuous communications there is a 2 APB clock period delay between the w...

Page 695: ...s blocks all output from the device and disables the SPI interface The MSTR bit is cleared thus forcing the device into slave mode Use the following software sequence to clear the MODF bit 1 Make a read or write access to the SPI_SR register while the MODF bit is set 2 Then write to the SPI_CR1 register To avoid any multiple slave conflicts in a system comprising several MCUs the NSS pin must be p...

Page 696: ...errun condition occurs the OVR bit is set and an interrupt is generated if the ERRIE bit is set In this case the receiver buffer contents will not be updated with the newly received data from the master device A read from the SPI_DR register returns this byte All other subsequently transmitted bytes are lost Clearing the OVR bit is done by a read from the SPI_DR register followed by a read access ...

Page 697: ...interface when the I2 S capability is enabled by setting the I2SMOD bit in the SPI_I2SCFGR register This interface uses almost the same pins flags and interrupts as the SPI Tx buffer Shift register 16 bit Communication Rx buffer 16 bit MOSI SD Master control logic MISO SPI baud rate generator CK I2SMOD LSB first LSB First SPE BR2 BR1 BR0 MSTR CPOL CPHA Bidi mode Bidi OE CRC EN CRC Next DFF Rx only...

Page 698: ... in the SPI_CR2 register and the MODF and CRCERR bits in the SPI_SR are not used The I2 S uses the same SPI register for data transfer SPI_DR in 16 bit wide mode 25 4 2 Supported audio protocols The three line bus has to handle only audio data generally time multiplexed on two channels the right channel and the left channel However there is only one 16 bit register for the transmission or the rece...

Page 699: ...rotocol waveforms 16 32 bit full accuracy CPOL 0 Data are latched on the falling edge of CK for the transmitter and are read on the rising edge for the receiver The WS signal is also latched on the falling edge of CK Figure 250 I2S Phillips standard waveforms 24 bit frame with CPOL 0 This mode needs two write or read operations to from the SPI_DR In transmission mode if 0x8EAA33 has to be sent 24 ...

Page 700: ...ing bits are forced by hardware to 0x0000 to extend the data to 32 bit format If the data to transmit or the received data are 0x76A3 0x76A30000 extended to 32 bit the operation shown in Figure 254 is required 0x8EAA 0x33XX Only the 8 MSBs are sent to complete the 24 bits First write to Data register Second write to Data register 8 LSB bits have no meaning and could be anything 0x8EAA 0x3300 Only ...

Page 701: ...6 MSB half word is received In this way more time is provided between two write or read operations which prevents underrun or overrun conditions depending on the direction of the data transfer MSB justified standard For this standard the WS signal is generated at the same time as the first data bit which is the MSBit Figure 255 MSB Justified 16 bit or 32 bit full accuracy length with CPOL 0 Data a...

Page 702: ...ified standard no difference for the 16 bit and 32 bit full accuracy frame formats Figure 258 LSB justified 16 bit or 32 bit full accuracy with CPOL 0 CK WS SD Channel left 32 bit Channel right MSB LSB 8 bit remaining 0 forced 24 bit data Transmission Reception CK WS SD Channel left 32 bit Channel right MSB LSB 16 bit remaining 0 forced 16 bit data Transmission Reception MSB LSB MSB CK WS SD Chann...

Page 703: ... are required on each RXNE event Figure 261 Operations required to receive 0x3478AE CK WS SD Channel left 32 bit Channel right MSB LSB 24 bit remaining 0 forced 8 bit data Transmission Reception 0xXX34 0x78AE First write to Data register Second write to Data register Only the 8 LSB bits of the half word are significant Whatever the 8 MSBs a field of 0x00 is forced instead conditioned by TXE 1 cond...

Page 704: ...ion mode when TXE is asserted the application has to write the data to be transmitted in this case 0x76A3 The 0x000 field is transmitted first extension on 32 bit TXE is asserted again as soon as the effective data 0x76A3 is sent on SD In reception mode RXNE is asserted as soon as the significant half word is received and not the 0x0000 field In this way more time is provided between two write or ...

Page 705: ...and long the number of bits between two consecutive pieces of data and so two synchronization signals needs to be specified DATLEN and CHLEN bits in the SPI_I2SCFGR register even in slave mode 25 4 3 Clock generator The I2 S bitrate determines the dataflow on the I2 S data line and the I2 S clock signal frequency I2 S bitrate number of bits per channel number of channels sampling audio frequency F...

Page 706: ...ter The audio sampling frequency may be 96 kHz 48 kHz 44 1 kHz 32 kHz 22 05 kHz 16 kHz 11 025 kHz or 8 kHz or any other value within this range In order to reach the desired frequency the linear divider needs to be programmed according to the formulas below When the master clock is generated MCKOE in the SPI_I2SPR register is set FS I2SxCLK 16 2 2 I2SDIV ODD 8 when the channel frame is 16 bit wide...

Page 707: ...5 13 1 0 No 44100 44117 65 43269 23 0 04 1 88 72 35 17 0 1 No 32000 32142 86 32142 86 0 44 0 44 72 51 25 0 1 No 22050 22058 82 22058 82 0 04 0 04 72 70 35 1 0 No 16000 15675 75 16071 43 0 27 0 45 72 102 51 0 0 No 11025 11029 41 11029 41 0 04 0 04 72 140 70 1 1 No 8000 8007 11 7978 72 0 09 0 27 72 2 2 0 0 Yes 96000 70312 15 70312 15 26 76 26 76 72 3 3 0 0 Yes 48000 46875 46875 2 34 2 34 72 3 3 0 0 ...

Page 708: ...64 32 5 13 63 1 No 16000 15994 0945 0 0369 16 8 14 124 0 No 11025 11025 7056 0 0064 32 8 14 62 0 No 11025 11025 7056 0 0064 16 7 10 139 1 No 8000 8000 51203 0 0064 32 7 20 139 1 No 8000 8000 51203 0 0064 16 5 10 2 0 Yes 96000 97656 25 1 7253 32 5 10 2 0 Yes 96000 97656 25 1 7253 16 7 12 3 1 Yes 48000 47831 6327 0 3508 32 7 12 3 1 Yes 48000 47831 6327 0 3508 16 5 9 4 0 Yes 44100 43945 3125 0 3508 3...

Page 709: ...434 16 3 10 96 0 No 16000 16000 0 0000 32 3 10 48 0 No 16000 16000 0 0000 16 4 20 209 1 No 11025 11023 923 0 0098 32 4 20 104 1 No 11025 11023 923 0 0098 16 3 10 192 0 No 8000 8000 0 0000 32 3 10 96 0 No 8000 8000 0 0000 16 3 10 2 0 Yes 96000 96000 0 0000 32 3 10 2 0 Yes 96000 96000 0 0000 16 3 10 4 0 Yes 48000 48000 0 0000 32 3 10 4 0 Yes 48000 48000 0 0000 16 4 20 6 1 Yes 44100 44307 6923 0 4710...

Page 710: ...gister 5 The I2SE bit in SPI_I2SCFGR register must be set WS and CK are configured in output mode MCK is also an output if the MCKOE bit in SPI_I2SPR is set Transmission sequence The transmission sequence begins when a half word is written into the Tx buffer Assumedly the first data written into the Tx buffer correspond to the channel Left data When data are transferred from the Tx buffer to the s...

Page 711: ...enerated to indicate the error To switch off the I2S specific actions are required to ensure that the I2S completes the transfer cycle properly without initiating a new data transfer The sequence depends on the configuration of the data and channel lengths and on the audio protocol mode selected In the case of 16 bit data length extended on 32 bit channel length DATLEN 00 and CHLEN 1 using the LSB...

Page 712: ... transmitted Compared to the master transmission mode in slave mode CHSIDE is sensitive to the WS signal coming from the external master This means that the slave needs to be ready to transmit the first data before the clock is generated by the master WS assertion corresponds to left channel transmitted first Note The I2SE has to be written at least two PCLK cycles before the first clock of the ma...

Page 713: ...egister an interrupt is generated to indicate the error To switch off the I2S in reception mode I2SE has to be cleared immediately after receiving the last RXNE 1 Note The external master components should have the capability of sending receiving data in 16 bit or 32 bit packets via an audio channel 25 4 6 Status flags Three status flags are provided for the application to fully monitor the state ...

Page 714: ...eds changing This flag has no meaning in the PCM standard for both Short and Long frame modes When the OVR or UDR flag in the SPI_SR is set and the ERRIE bit in SPI_CR2 is also set an interrupt is generated This interrupt can be cleared by reading the SPI_SR status register once the interrupt source has been cleared 25 4 7 Error flags There are two error flags for the I2 S cell Underrun flag UDR I...

Page 715: ...n exactly the same way as for the SPI mode There is no difference on the I2 S Only the CRC feature is not available in I2 S mode since there is no data transfer protection system Table 185 I2 S interrupt requests Interrupt event Event flag Enable Control bit Transmit buffer empty flag TXE TXEIE Receive buffer not empty flag RXNE RXNEIE Overrun error OVR ERRIE Underrun error UDR ...

Page 716: ...ceive only mode 1 Output enabled transmit only mode Note In master mode the MOSI pin is used and in slave mode the MISO pin is used Not used in I2S mode Bit 13 CRCEN Hardware CRC calculation enable 0 CRC calculation disabled 1 CRC calculation enabled Note This bit should be written only when SPI is disabled SPE 0 for correct operation Not used in I2S mode Bit 12 CRCNEXT CRC transfer next 0 Data ph...

Page 717: ...t has an effect only when the SSM bit is set The value of this bit is forced onto the NSS pin and the IO value of the NSS pin is ignored Note Not used in I2 S mode Bit 7 LSBFIRST Frame format 0 MSB transmitted first 1 LSB transmitted first Note This bit should not be changed when communication is ongoing Not used in I2 S mode Bit 6 SPE SPI enable 0 Peripheral disabled 1 Peripheral enabled Note 1 N...

Page 718: ...idle Note This bit should not be changed when communication is ongoing Not used in I2 S mode Bit 0 CPHA Clock phase 0 The first clock transition is the first data capture edge 1 The second clock transition is the first data capture edge Note This bit should not be changed when communication is ongoing Note Not used in I2 S mode ...

Page 719: ...IE Error interrupt enable This bit controls the generation of an interrupt when an error condition occurs CRCERR OVR MODF in SPI mode and UDR OVR in I2S mode 0 Error interrupt is masked 1 Error interrupt is enabled Bits 4 3 Reserved Forced to 0 by hardware Bit 2 SSOE SS output enable 0 SS output is disabled in master mode and the cell can work in multimaster configuration 1 SS output is enabled in...

Page 720: ... fault occurred 1 Mode fault occurred This flag is set by hardware and reset by a software sequence Refer to Section 25 3 10 on page 695 for the software sequence Note Not used in I2S mode Bit 4 CRCERR CRC error flag 0 CRC value received matches the SPI_RXCRCR value 1 CRC value received does not match the SPI_RXCRCR value This flag is set by hardware and cleared by software writing 0 Note Not used...

Page 721: ... mode Depending on the data frame format selection bit DFF in SPI_CR1 register the data sent or received is either 8 bit or 16 bit This selection has to be made before enabling the SPI to ensure correct operation For an 8 bit data frame the buffers are 8 bit and only the LSB of the register SPI_DR 7 0 is used for transmission reception When in reception mode the MSB of the register SPI_DR 15 8 is ...

Page 722: ...6 bit data frame format is selected DFF bit of the SPI_CR1 register is set CRC calculation is done based on any CRC16 standard Note A read to this register when the BSY Flag is set could return an incorrect value Not used for the I2S mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXCRC 15 0 r r r r r r r r r r r r r r r r Bits 15 0 TXCRC 15 0 Tx CRC register When CRC calculation is enabled the TxCRC 7...

Page 723: ...11 Master receive Note This bit should be configured when the I2S is disabled Not used for the SPI mode Bit 7 PCMSYNC PCM frame synchronization 0 Short frame synchronization 1 Long frame synchronization Note This bit has a meaning only if I2SSTD 11 PCM standard is used Not used for the SPI mode Bit 6 Reserved forced at 0 by hardware Bit 5 4 I2SSTD I2S standard selection 00 I2 S Phillips standard 0...

Page 724: ...disabled Not used in SPI mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MCKOE ODD I2SDIV rw rw rw Bits 15 10 Reserved Forced to 0 by hardware Bit 9 MCKOE Master clock output enable 0 Master clock output is disabled 1 Master clock output is enabled Note This bit should be configured when the I2S is disabled It is used only when the I2S is in master mode Not used in SPI mode Bit 8 ODD Odd facto...

Page 725: ... 0 0 0 0 0 0 0 0 0 0 0x04 SPI_CR2 Reserved TXEIE RXNEIE ERRIE Reserved SSOE TXDMAEN RXDMAEN Reset value 0 0 0 0 0 0 0x08 SPI_SR Reserved BSY OVR MODF CRCERR UDR CHSIDE TXE RXNE Reset value 0 0 0 0 0 0 1 0 0x0C SPI_DR Reserved DR 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x10 SPI_CRCPR Reserved CRCPOLY 15 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0x14 SPI_RXCRCR Reserved RxCRC 15 0 Reset...

Page 726: ...cuit bus Interface serves as an interface between the microcontroller and the serial I2 C bus It provides multimaster capability and controls all I2 C bus specific sequencing protocol arbitration and timing It supports standard and fast speed modes It is also SMBus 2 0 compatible It may be used for a variety of purposes including CRC generation and verification SMBus system management bus and PMBu...

Page 727: ...l Address Resolution Protocol ARP supported PMBus Compatibility Note Some of the above features may not be available in certain products The user should refer to the product data sheet to identify the specific features supported by the I2 C interface implementation 26 3 I2C functional description In addition to receiving and transmitting data this interface converts it from serial to parallel form...

Page 728: ...bled or disabled by software Data and addresses are transferred as 8 bit bytes MSB first The first byte s following the start condition contain the address one in 7 bit mode two in 10 bit mode The address is always transmitted in Master mode A 9th clock pulse follows the 8 clock cycles of a byte transfer during which the receiver must send an acknowledge bit to the transmitter Refer to Figure 268 ...

Page 729: ...from the SDA line and sent to the shift register Then it is compared with the address of the interface OAR1 and with OAR2 if ENDUAL 1 or the General Call address if ENGC 1 Note In 10 bit addressing mode the comparison includes the header sequence 11110xx0 where xx denotes the two most significant bits of the address Header or address not matched the interface ignores it and waits for another Start...

Page 730: ... the ITBUFEN bits are set If TxE is set and some data were not written in the I2C_DR register before the end of the next data transmission the BTF bit is set and the interface waits until BTF is cleared by a read to I2C_SR1 followed by a write to the I2C_DR register stretching SCL low Figure 270 Transfer sequence diagram for slave transmitter 7 bit slave transmitter 10 bit slave transmitter Legend...

Page 731: ...nd sets The STOPF bit and generates an interrupt if the ITEVFEN bit is set Then the interface waits for a read of the SR1 register followed by a write to the CR1 register see Figure 271 Transfer sequencing EV4 26 3 3 I2 C master mode In Master mode the I2 C interface initiates a data transfer and generates the clock signal A serial data transfer always begins with a Start condition and ends with a...

Page 732: ...t clock in I2C_CR2 Register in order to generate correct timings Configure the clock control registers Configure the rise time register Program the I2C_CR1 register to enable the peripheral Set the START bit in the I2C_CR1 register to generate a Start condition The peripheral input clock frequency must be at least 2 MHz in Standard mode 4 MHz in Fast mode ...

Page 733: ...ing The ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit is set Then the master waits for a read of the SR1 register followed by a read of the SR2 register see Figure 272 Figure 273 Transfer sequencing In 7 bit addressing mode one address byte is sent As soon as the address byte is sent The ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit is ...

Page 734: ... either TxE or BTF is set Figure 272 Transfer sequence diagram for master transmitter 7 bit master transmitter 10 bit master transmitter Legend S Start Sr Repeated Start P Stop A Acknowledge EVx Event with interrupt if ITEVFEN 1 EV5 SB 1 cleared by reading SR1 register followed by writing DR register with Address EV6 ADDR 1 cleared by reading SR1 register followed by reading SR2 EV8_1 TxE 1 shift ...

Page 735: ...he DR register stretching SCL low Closing the communication Method 1 This method is for the case when the I2C is used with interrupts that have the highest priority in the application The master sends a NACK for the last byte received from the slave After receiving this NACK the slave releases the control of the SCL and SDA lines Then the master can send a Stop Restart condition 1 To generate the ...

Page 736: ...DataN_1 the communication is stretched both RxNE and BTF are set Then clear the ACK bit before reading DataN 2 in DR to ensure it is be cleared before the DataN Acknowledge pulse After that just after reading DataN_2 set the STOP START bit and read DataN_1 After RxNE is set read DataN This is illustrated below BIT MASTER RECEIVER BIT MASTER RECEIVER EGEND 3 3TART 3R 2EPEATED 3TART 0 3TOP CKNOWLEDG...

Page 737: ...aN 2 in DR This will launch the DataN reception in the shift register DataN received with a NACK Program START STOP Read DataN 1 RxNE 1 Read DataN A Address S EV5 EV6 A Data1 A Data2 EV7 EV7 A DataN 2 A DataN 1 EV7_2 NA DataN EV7 P Legend S Start Sr Repeated Start P Stop A Acknowledge NA Non acknowledge EV5 SB 1 cleared by reading SR1 register followed by writing the DR register EV6 ADDR1 cleared ...

Page 738: ...nce 2 The EV6_1 software sequence must complete before the ACK pulse of the current byte transfer A Address S EV5 EV6 A Data1 Data2 EV7_3 NA P Legend S Start Sr Repeated Start P Stop A Acknowledge NA Non acknowledge EV5 SB 1 cleared by reading SR1 register followed by writing the DR register EV6 ADDR1 cleared by reading SR1 register followed by reading SR2 In 10 bit master receiver mode this seque...

Page 739: ... up to the software to abort or not the current transmission Acknowledge failure AF This error occurs when the interface detects a nonacknowledge bit In this case the AF bit is set and an interrupt is generated if the ITERREN bit is set a transmitter which receives a NACK must reset the communication If Slave lines are released by hardware If Master a Stop or repeated Start condition must be gener...

Page 740: ... DR with the next byte TxE 1 before the clock comes for the next byte In this case The same byte in the DR register will be sent again The user should make sure that data received on the receiver side during an underrun error are discarded and that the next bytes are written within the clock low time specified in the I2C bus standard For the first byte to be transmitted the DR must be written afte...

Page 741: ...tional Master slave communication Master provides clock Multi master capability SMBus data format similar to I2C 7 bit addressing format Figure 268 Differences between SMBus and I2 C The following table describes the differences between SMBus and I2C SMBus application usage With System Management Bus a device can provide manufacturer information tell the system what its model part number is save i...

Page 742: ... alert mode SMBus Alert is an optional signal with an interrupt line for devices that want to trade their ability to master for a pin SMBA is a wired AND signal just as the SCL and SDA signals are SMBA is used in conjunction with the SMBus General Call Address Messages invoked with the SMBus are 2 bytes long A slave only device can signal the host through SMBA that it wants to talk by setting ALER...

Page 743: ...T 1 26 3 7 DMA requests DMA requests when enabled are generated only for data transfer DMA requests are generated by Data Register becoming empty in transmission and Data Register becoming full in reception The DMA request must be served before the end of the current byte transfer When the number of data transfers which has been programmed for the corresponding DMA channel is reached the DMA contr...

Page 744: ...eption by setting the DMAEN bit in the I2C_CR2 register Data will be loaded from the I2C_DR register to a Memory area configured using the DMA peripheral refer to the DMA specification whenever a data byte is received To map a DMA channel for I2 C reception perform the following sequence Here x is the channel number 1 Set the I2C_DR register address in DMA_CPARx register The data will be moved fro...

Page 745: ...CERR error flag interrupt is also available in the I2C_SR1 register If DMA and PEC calculation are both enabled In transmission when the I2 C interface receives an EOT signal from the DMA controller it automatically sends a PEC after the last byte In reception when the I2 C interface receives an EOT_1 signal from the DMA controller it will automatically consider the next byte as a PEC and will che...

Page 746: ...n the same interrupt channel Figure 277 I2 C interrupt mapping diagram Bus error BERR ITERREN Arbitration loss Master ARLO Acknowledge failure AF Overrun Underrun OVR PEC error PECERR Timeout Tlow error TIMEOUT SMBus Alert SMBALERT Table 188 I2 C Interrupt requests continued Interrupt event Event flag Enable control bit ADDR SB ADD10 RxNE TxE BTF it_event ARLO BERR AF OVR PECERR TIMEOUT SMBALERT I...

Page 747: ...C ENPEC ENARP SMB TYPE Res SMBUS PE rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 15 SWRST Software reset When set the I2C is under reset state Before resetting this bit make sure the I2C lines are released and the bus is free 0 I2 C Peripheral not under reset 1 I2 C Peripheral under reset state Note This bit can be used in case the BUSY bit is set to 1 when no stop condition has been detected on ...

Page 748: ...address or data Bit 9 STOP Stop generation The bit is set and cleared by software cleared by hardware when a Stop condition is detected set by hardware when a timeout error is detected In Master Mode 0 No Stop generation 1 Stop generation after the current byte transfer or after the current Start condition is sent In Slave mode 0 No Stop generation 1 Release the SCL and SDA lines after the current...

Page 749: ...bled at the end of the current communication when back to IDLE state All bit resets due to PE 0 occur at the end of the communication In master mode this bit must not be reset before the end of the communication 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LAST DMA EN ITBUF EN ITEVT EN ITERR EN Reserved FREQ 5 0 rw rw rw rw rw rw rw rw rw rw rw Bits 15 13 Reserved forced by hardware to 0 Bit 12 ...

Page 750: ...TIMEOUT 1 SMBALERT 1 Bits 7 6 Reserved forced by hardware to 0 Bits 5 0 FREQ 5 0 Peripheral clock frequency The peripheral clock frequency must be configured using the input APB clock frequency I2C peripheral connected to APB The minimum allowed frequency is 2 MHz the maximum frequency is limited by the maximum APB frequency 36 MHz and an intrinsic limitation of 46 MHz 0b000000 Not allowed 0b00000...

Page 751: ... Dual addressing mode enable 0 Only OAR1 is recognized in 7 bit addressing mode 1 Both OAR1 and OAR2 are recognized in 7 bit addressing mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DR 7 0 rw rw rw rw rw rw rw rw Bits 15 8 Reserved forced by hardware to 0 Bits 7 0 DR 7 0 8 bit data register Byte received or to be transmitted to the bus Transmitter mode Byte transmission starts automatically ...

Page 752: ...de slave resets the communication and lines are released by hardware When set in master mode Stop condition sent by hardware Cleared by software writing 0 or by hardware when PE 0 Note This functionality is available only in SMBus mode Bit 13 Reserved forced by hardware to 0 Bit 12 PECERR PEC Error in reception 0 no PEC error receiver returns ACK after PEC reception if ACK 1 1 PEC error receiver r...

Page 753: ...ers 0 Data register not empty 1 Data register empty Set when DR is empty in transmission TxE is not set during address phase Cleared by software writing to the DR register or by hardware after a start or a stop condition or when PE 0 TxE is not set if either a NACK is received or if next byte to be transmitted is PEC PEC 1 Note TxE is not cleared by writing the first data being transmitted or by w...

Page 754: ...PE 0 Note The BTF bit is not set after a NACK reception The BTF bit is not set if next byte to be transmitted is the PEC TRA 1 in I2C_SR2 register and PEC 1 in I2C_CR1 register Bit 1 ADDR Address sent master mode matched slave mode This bit is cleared by software reading SR1 register followed reading SR2 or by hardware when PE 0 Address matched Slave 0 Address mismatched or not received 1 Received...

Page 755: ... mode 0 No SMBus Device Default address 1 SMBus Device Default address received when ENARP 1 Cleared by hardware after a Stop condition or repeated Start condition or when PE 0 Bit 4 GENCALL General call address Slave mode 0 No General Call 1 General Call Address received when ENGC 1 Cleared by hardware after a Stop condition or repeated Start condition or when PE 0 Bit 3 Reserved forced by hardwa...

Page 756: ...e I2C Bit 14 DUTY Fast mode duty cycle 0 Fast Mode tlow thigh 2 1 Fast Mode tlow thigh 16 9 see CCR Bits 13 12 Reserved forced by hardware to 0 Bits 11 0 CCR 11 0 Clock control register in Fast Standard mode Master mode Controls the SCL clock in master mode Standard mode or SMBus Thigh CCR TPCLK1 Tlow CCR TPCLK1 Fast mode If DUTY 0 Thigh CCR TPCLK1 Tlow 2 CCR TPCLK1 If DUTY 1 to reach 400 kHz Thig...

Page 757: ...d with the maximum SCL rise time given in the I2 C bus specification incremented by 1 For instance in standard mode the maximum allowed SCL rise time is 1000 ns If in the I2C_CR2 register the value of FREQ 5 0 bits is equal to 0x08 and TPCLK1 125 ns therefore the TRISE 5 0 bits must be programmed with 09h 1000 ns 125 ns 8 1 The filter value can also be added to TRISE 5 0 If the result is not an in...

Page 758: ... 0 0x04 I2C_CR2 Reserved LAST DMAEN ITBUFEN ITEVTEN ITERREN Reserved FREQ 5 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0x08 I2C_OAR1 Reserved ADDMODE Reserved ADD 9 8 ADD 7 1 ADD0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0x0C I2C_OAR2 Reserved ADD2 7 1 ENDUAL Reset value 0 0 0 0 0 0 0 0 0x10 I2C_DR Reserved DR 7 0 Reset value 0 0 0 0 0 0 0 0 0x14 I2C_SR1 Reserved SMBALERT TIMEOUT Reserved PECERR OVR AF ARLO BER...

Page 759: ...anges between 768 Kbytes and 1 Mbyte Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers This Section applies to the whole STM32F10xxx family unless otherwise specified 27 1 USART introduction The universal synchronous asynchronous receiver transmitter USART offers a flexible means of full duplex data exchange with external equipment requiring an industry standard NRZ asynch...

Page 760: ...on and 10 11 bit break detection when USART is hardware configured for LIN Transmitter clock output for synchronous transmission IrDA SIR Encoder Decoder Support for 3 16 bit duration for normal mode Smartcard Emulation Capability The Smartcard interface supports the asynchronous protocol Smartcards as defined in ISO 7816 3 standards 0 5 1 5 Stop Bits for Smartcard operation Single wire half duple...

Page 761: ...ess mark detection Two receiver wakeup modes Address bit MSB 9th bit Idle line 27 3 USART functional description The interface is externally connected to another device by three pins see Figure 27 3 1 Any USART bidirectional communication requires a minimum of two pins Receive Data In RX and Transmit Data Out TX RX Receive Data Input is the serial data input Oversampling techniques are used for da...

Page 762: ... pin is required to interface in synchronous mode CK Transmitter clock output This pin outputs the transmitter data clock for synchronous transmission corresponding to SPI master mode no clock pulses on start bit and stop bit and a software option to send a clock pulse on the last data bit In parallel data can be received synchronously on RX This can be used to control peripherals that have shift ...

Page 763: ...IVER CONTROL SR TRANSMIT CONTROL TXE TC RXNE IDLE ORE NE FE USART CONTROL INTERRUPT CR1 M WAKE Receive Data Register RDR Receive Shift Register Read Transmit Data Register TDR Transmit Shift Register Write SW_RX TX DATA REGISTER DR TRANSMITTER CLOCK RECEIVER CLOCK RECEIVER RATE TRANSMITTER RATE fPCLKx x 1 2 CONTROL CONTROL 16 CONVENTIONAL BAUD RATE GENERATOR SBK RWU RE TE IDLE RXNE TCIE TXEIE CR1 ...

Page 764: ...the transmitter and receiver The details of each block is given below Figure 278 Word length programming Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Start bit Stop bit Next Start bit Idle frame Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Start Bit Stop Bit Next Start Bit Idle frame Start bit 9 bit word length M bit is set 1 stop bit 8 bit word length M bit is reset 1 stop bit Possible parity bit Poss...

Page 765: ...top bits Note 1 The TE bit should not be reset during transmission of data Resetting the TE bit during the transmission will corrupt the data on the TX pin as the baud rate counters will get frozen The current data being transmitted will be lost 2 An idle frame will be sent after the TE bit is enabled Configurable stop bits The number of stop bits to be transmitted with every character can be prog...

Page 766: ...e USART is disabled or enters the Halt mode to avoid corrupting the last transmission Single byte communication The TXE bit is always cleared by a write to the data register The TXE bit is set by hardware and it indicates The data has been moved from TDR to the shift register and the data transmission has started The TDR register is empty The next data can be written in the USART_DR register witho...

Page 767: ...on Figure 280 TC TXE behavior when transmitting Break characters Setting the SBK bit transmits a break character The break frame length depends on the M bit see Figure 278 If the SBK bit is set to 1 a break character is sent on the TX line after completing the current character transmission This bit is reset by hardware when the break character is completed during the stop bit of the break charact...

Page 768: ...th and 10th bits also finds the 3 bits at 0 The start bit is validated RXNE flag set interrupt generated if RXNEIE 1 but the NE noise flag is set if for both samplings at least 2 out of the 3 sampled bits are at 0 sampling on the 3rd 5th and 7th bits and sampling on the 8th 9th and 10th bits If this condition is not met the start detection aborts and the receiver returns to the idle state no flag ...

Page 769: ...been received and can be read as well as its associated error flags An interrupt is generated if the RXNEIE bit is set The error flags can be set if a frame error noise or an overrun error has been detected during reception In multibuffer RXNE is set after every byte received and is cleared by the DMA read to the Data Register In single buffer mode clearing the RXNE bit is performed by a software ...

Page 770: ... register read operation Note The ORE bit when set indicates that at least 1 data has been lost There are two possibilities if RXNE 1 then the last valid data is stored in the receive register RDR and can be read if RXNE 0 then it means that the last valid data has already been read and thus there is nothing to be read in the RDR This case can occur when the last valid data is read in the RDR at t...

Page 771: ...en The stop bit is not recognized on reception at the expected time following either a de synchronization or excessive noise When the framing error is detected The FE bit is set by hardware The invalid data is transferred from the Shift register to the USART_DR register No interrupt is generated in case of single byte communication However this bit rises at the same time as the RXNE bit which itse...

Page 772: ...op bit The 1 5 stop bit can be decomposed into 2 parts one 0 5 baud clock period during which nothing happens followed by 1 normal stop bit period during which sampling occurs halfway through Refer to Section 27 3 11 Smartcard on page 782 for more details 4 2 stop bits Sampling for 2 stop bits is done on the 8th 9th and 10th samples of the first stop bit If a framing error is detected during the f...

Page 773: ...articular Baud rate The upper limit of the achievable baud rate can be fixed with this data 2 Only USART1 is clocked with PCLK2 72 MHz Max Other USARTs are clocked with PCLK1 36 MHz Max Table 191 Error calculation for programmed baud rates Baud rate fPCLK 36 MHz fPCLK 72 MHz S No in Kbps Actual Value programmed in the Baud Rate register Error Calculated Desired B Rate Desired B Rate Actual Value p...

Page 774: ...racter length defined by the M bit in the USART_CR1 register use of fractional baud rate or not Table 192 USART receiver s tolerance when DIV_Fraction is 0 Table 193 USART receiver s tolerance when DIV_Fraction is different from 0 Note The figures specified in Table 192 and Table 193 may slighly differ in the special case when the received frames contain some Idle frames of exactly 10 bit times wh...

Page 775: ...n Address mark detection WAKE 1 In this mode bytes are recognized as addresses if their MSB is a 1 else they are considered as data In an address byte the address of the targeted receiver is put on the 4 LSB This 4 bit word is compared by the receiver with its own address which is programmed in the ADD bits in the USART_CR2 register The USART enters mute mode when an address character is received ...

Page 776: ...e the frame made of the 7 or 8 LSB bits depending on whether M is equal to 0 or 1 and the parity bit Ex data 00110101 4 bits set parity bit will be 1 if odd parity is selected PS bit in USART_CR1 1 Transmission mode If the PCE bit is set in USART_CR1 then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit even number of 1s if even parity is selecte...

Page 777: ...ters or data After a start bit has been detected the circuit samples the next bits exactly like for the data on the 8th 9th and 10th samples If 10 when the LBDL 0 in USART_CR2 or 11 when LBDL 1 in USART_CR2 consecutive bits are detected as 0 and are followed by a delimiter character the LBD flag is set in USART_SR If the LBDIE bit 1 an interrupt is generated Before validating the break the delimit...

Page 778: ...8 Bit9 Idle Idle Read Samples Bit0 0 0 0 0 0 0 0 0 0 1 Bit10 Break frame RX line Break State machine Capture Strobe 0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Idle Idle Read Samples Bit0 0 0 0 0 0 0 0 0 0 0 B10 Case 2 break signal just long enough break detected LBD is set LBD Break frame RX line Break State machine Capture Strobe 0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Idle Idle Read S...

Page 779: ...the user to select the clock polarity and the CPHA bit in the USART_CR2 register allows the user to select the phase of the external clock see Figure 287 Figure 288 Figure 289 During idle preamble and send break the external CK clock is not activated In synchronous mode the USART transmitter works exactly like in asynchronous mode But as CK is synchronized with TX according to CPOL and CPHA the da...

Page 780: ...hile the transmitter or the receiver is enabled 3 It is advised that TE and RE are set in the same instruction in order to minimize the setup and the hold time of the receiver 4 The USART supports master mode only it cannot receive or send data related to an input clock CK is always an output Figure 287 USART example of synchronous transmission Figure 288 USART data clock timing diagram M 0 RX TX ...

Page 781: ...ns are connected internally The selection between half and full duplex communication is made with a control bit HALF DUPLEX SEL HDSEL in USART_CR3 As soon as HDSEL is written to 1 RX is no longer used TX is always released when no data is transmitted Thus it acts as a standard IO in idle or in reception It means that the IO must be configured so that TX is configured as floating input or output hi...

Page 782: ... register 1 5 stop bits when transmitting and receiving where STOP 11 in the USART_CR2 register Note It is also possible to choose 0 5 stop bit for receiving but it is recommended to use 1 5 stop bits for both transmitting and receiving to avoid switching between the two configurations Figure 291 shows examples of what can be seen on the data line with and without parity error Figure 291 ISO 7816 ...

Page 783: ... normal operation TC is asserted when the transmit shift register is empty and no further transmit requests are outstanding In Smartcard mode an empty transmit shift register triggers the guard time counter to count up to the programmed value in the Guard Time register TC is forced low during this time When the guard time counter reaches the programmed value TC is asserted high The de assertion of...

Page 784: ...SIR physical layer specifies use of a Return to Zero Inverted RZI modulation scheme that represents logic 0 as an infrared light pulse see Figure 293 The SIR Transmit encoder modulates the Non Return to Zero NRZ transmit bit stream output from USART The output pulse stream is transmitted to an external output driver and infrared LED USART supports only bit rates up to 115 2Kbps for the SIR ENDEC I...

Page 785: ...scaler value programmed in the IrDA low power Baud Register USART_GTPR Pulses of width less than 1 PSC period are always rejected but those of width greater than one and less than two periods may be accepted or rejected those greater than 2 periods will be accepted as a pulse The IrDA encoder decoder doesn t work when PSC 0 The receiver can communicate with a low power transmitter In IrDA mode the...

Page 786: ...he USART as explained in Section 27 3 2 or 27 3 3 In the USART_SR register you can clear the TXE RXNE flags to achieve continuous communication Transmission using DMA DMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3 register Data is loaded from a SRAM area configured using the DMA peripheral refer to the DMA specification to the USART_DR register whenever the TXE bit i...

Page 787: ...s an interrupt on the DMA channel interrupt vector In transmission mode once the DMA has written all the data to be transmitted the TCIF flag is set in the DMA_ISR register the TC flag can be monitored to make sure that the USART communication is complete This is required to avoid corrupting the last transmission before disabling the USART or entering the Stop mode The software must wait until TC ...

Page 788: ... by the application 6 Activate the channel in the DMA control register When the number of data transfers programmed in the DMA Controller is reached the DMA controller generates an interrupt on the DMA channel interrupt vector Figure 296 Reception using DMA Error flagging and interrupt generation in multibuffer communication In case of multibuffer communication if any error occurs during the trans...

Page 789: ...th RTS flow control enabled Figure 298 RTS flow control CTS flow control If the CTS flow control is enabled CTSE 1 then the transmitter checks the nCTS input before transmitting the next frame If nCTS is asserted tied low then the next data is transmitted assuming that a data is to be transmitted in other words if TXE 0 else the transmission does not occur When nCTS is deasserted during a transmis...

Page 790: ...se events generate an interrupt if the corresponding Enable Control Bit is set Start Bit Stop Bit Data 2 Idle Start Bit Data 3 TX nCTS CTS Transmission of Data 3 Data 1 Stop Bit is delayed until nCTS 0 CTS Data 2 Data 3 empty empty Transmit data register TDR Writing data 3 in TDR Table 195 USART interrupt requests Interrupt event Event flag Enable Control bit Transmit data register empty TXE TXEIE...

Page 791: ... by half words 16 bit or words 32 bit TC TCIE TXE TXEIE IDLE IDLEIE RXNEIE ORE RXNEIE RXNE PE PEIE FE NE ORE EIE DMAR USART LBD LBDIE CTS CTSIE interrupt Table 196 USART mode configuration 1 1 X supported NA not applicable USART modes USART1 USART2 USART3 UART4 UART5 Asynchronous mode X X X X X Hardware Flow Control X X X NA NA Multibuffer Communication DMA X X X X NA Multiprocessor Communication ...

Page 792: ...the content of the TDR register has been transferred into the shift register An interrupt is generated if the TXEIE bit 1 in the USART_CR1 register It is cleared by a write to the USART_DR register 0 Data is not transferred to the shift register 1 Data is transferred to the shift register Note This bit is used during single buffer transmission Bit 6 TC Transmission complete This bit is set by hard...

Page 793: ...is cleared by a software sequence an read to the USART_SR register followed by a read to the USART_DR register 0 No noise is detected 1 Noise is detected Note This bit does not generate interrupt as it appears at the same time as the RXNE bit which itself generates an interrupting interrupt is generated on NE flag in case of Multi Buffer communication if the EIE bit is set Bit 1 FE Framing error T...

Page 794: ...eption RDR The TDR register provides the parallel interface between the internal bus and the output shift register see Figure 1 The RDR register provides the parallel interface between the input shift register and the internal bus When transmitting with the parity enabled PCE bit set to 1 in the USART_CR1 register the value written in the MSB bit 7 or bit 8 depending on the data length has no effe...

Page 795: ... Bit 11 WAKE Wakeup method This bit determines the USART wakeup method it is set or cleared by software 0 Idle Line 1 Address Mark Bit 10 PCE Parity control enable This bit selects the hardware parity control generation and detection When the parity control is enabled the computed parity is inserted at the MSB position 9th bit if M 1 8th bit if M 0 and parity is checked on the received data This b...

Page 796: ...e current word except in smartcard mode 2 When TE is set there is a 1 bit time delay before the transmission starts Bit 2 RE Receiver enable This bit enables the receiver It is set and cleared by software 0 Receiver is disabled 1 Receiver is enabled and begins searching for a start bit Bit 1 RWU Receiver wakeup This bit determines if the USART is in mute mode or not It is set and cleared by softwa...

Page 797: ... 1 5 Stop bit The 0 5 Stop bit and 1 5 Stop bit are not available for UART4 UART5 Bit 11 CLKEN Clock enable This bit allows the user to enable the CK pin 0 CK pin disabled 1 CK pin enabled This bit is not available for UART4 UART5 Bit 10 CPOL Clock polarity This bit allows the user to select the polarity of the clock output on the CK pin in synchronous mode It works in conjunction with the CPHA bi...

Page 798: ...L lin break detection length This bit is for selection between 11 bit or 10 bit break detection 0 10 bit break detection 1 11 bit break detection Bit 4 Reserved forced by hardware to 0 Bits 3 0 ADD 3 0 Address of the USART node This bit field gives the address of the USART node This is used in multiprocessor communication during mute mode for wake up with address mark detection 31 30 29 28 27 26 2...

Page 799: ...card mode 0 Smartcard Mode disabled 1 Smartcard Mode enabled This bit is not available for UART4 UART5 Bit 4 NACK Smartcard NACK enable 0 NACK transmission in case of parity error is disabled 1 NACK transmission during parity error is enabled This bit is not available for UART4 UART5 Bit 3 HDSEL Half duplex selection Selection of Single wire Half duplex mode 0 Half duplex mode is not selected 1 Ha...

Page 800: ... PSC 7 0 IrDA Low Power Baud Rate Used for programming the prescaler for dividing the system clock to achieve the low power frequency The source clock is divided by the value given in the register 8 significant bits 00000000 Reserved do not program this value 00000001 divides the source clock by 1 00000010 divides the source clock by 2 In normal IrDA mode PSC must be set to 00000001 In smartcard m...

Page 801: ... PE Reset value 0 0 1 1 0 0 0 0 0 0 0x04 USART_DR Reserved DR 8 0 Reset value 0 0 0 0 0 0 0 0 0 0x08 USART_BRR Reserved DIV_Mantissa 15 4 DIV_Fraction 3 0 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0C USART_CR1 Reserved UE M WAKE PCE PS PEIE TXEIE TCIE RXNEIE IDLEIE TE RE RWU SBK Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x10 USART_CR2 Reserved LINEN STOP 1 0 CLKEN CPOL CPHA LBCL Reserved LBDIE L...

Page 802: ...sys Inc All rights reserved Used with permission This section presents the architecture and the programming model of the OTG_FS controller The following acronyms are used throughout the section References are made to the following documents USB On The Go Supplement Revision 1 3 Universal Serial Bus Revision 2 0 Specification The OTG_FS is a dual role device DRD controller that supports both device...

Page 803: ... It supports dynamic host peripheral switch of role It is software configurable to operate as SRP capable USB FS Peripheral B device SRP capable USB FS LS host A device USB On The Go Full Speed Dual Role device It supports FS SOF and LS Keep alives with SOF pulse PAD connectivity SOF pulse internal connection to timer2 TIM2 Configurable framing period Configurable end of frame interrupt It include...

Page 804: ...quests in the non periodic hardware queue Management of a shared RX FIFO a periodic TX FIFO and a nonperiodic TX FIFO for efficient usage of the USB data RAM 28 2 3 Peripheral mode features The OTG_FS interface main features in peripheral mode are the following 1 bidirectional control endpoint0 3 IN endpoints EPs configurable to support Bulk Interrupt or Isochronous transfers 3 OUT endpoints confi...

Page 805: ... RAM There is one Tx FIFO push register for each in endpoint peripheral mode or out channel host mode The CPU receives the data from the USB by reading 32 bit words from dedicated OTG_FS addresses pop registers The data are then automatically retrieved from a shared Rx FIFO configured within the 1 25 KB USB data RAM There is one Rx FIFO pop register for each out endpoint or in channel The USB prot...

Page 806: ...ull up consists of 2 resistors controlled separately from the OTG_FS as per the resistor Enginering Change Notice applied to USB Rev2 0 The dynamic trimming of the DP pull up strength allows for better noise rejection and Tx Rx signal quality VBUS sensing comparators with hysteresis used to detect VBUS Valid A B Session Valid and session end voltage thresholds They are used to drive the session re...

Page 807: ...he Go A device of the On The Go Specification Rev1 3 supplement to the USB2 0 28 4 2 HNP dual role device The HNP capable bit in the Global USB configuration register HNPCAP bit in OTG_FS_ GUSBCFG enables the OTG_FS core to dynamically change its role from A host to A peripheral and vice versa or from B Peripheral to B host and vice versa according to the host negotiation protocol HNP The current ...

Page 808: ...ster FDMOD in OTG_FS_GUSBCFG is set to 1 forcing the OTG_FS core to work as a USB peripheral only see On The Go Rev1 3 par 6 8 3 In this case the ID line is ignored even if present on the USB connector Note 1 To build a bus powered device implementation in case of the B device or peripheral only configuration an external regulator has to be added that generates the VDD chip supply from VBUS 2 The ...

Page 809: ...mplete the enumeration done interrupt ENUMDNE bit in OTG_FS_GINTSTS is generated and the OTG_FS enters the Default state Soft disconnect The powered state can be exited by software with the soft disconnect feature The DP pull up resistor is removed by setting the soft disconnect bit in the device control register SDIS bit in OTG_FS_DCTL causing a device disconnect detection interrupt on the host s...

Page 810: ...s common interrupt mask register OTG_FS_DIEPMSK is available to enable disable a single kind of endpoint interrupt source on all of the IN endpoints EP0 included Support for incomplete isochronous IN transfer interrupt IISOIXFR bit in OTG_FS_GINTSTS asserted when there is at least one isochronous IN endpoint on which the transfer is not completed in the current frame This interrupt is asserted alo...

Page 811: ...llow the application to program the transfer size parameters and read the transfer status Programming must be done before setting the endpoint enable bit in the endpoint control register Once the endpoint is enabled these fields are read only as the OTG FS core updates them with the current transfer status The following transfer parameters can be programmed Transfer size in bytes Number of packets...

Page 812: ...e is present functional and connected to the A side of the USB cable and the HNP capable bit is cleared in the Global USB Configuration register HNPCAP bit in OTG_FS_GUSBCFG Integrated pull down resistors are automatically set on the DP DM lines Host only see figure Figure 304 USB host only connection The force host mode bit in the global USB configuration register FHMOD bit in OTG_FS_GUSBCFG forc...

Page 813: ...s to power on VBUS using the chosen GPIO it must also set the port power bit in the host port control and status register PPWR bit in OTG_FS_HPRT VBUS valid The VBUS input ensures that valid VBUS levels are supplied by the charge pump during USB operations Any unforeseen VBUS voltage drop below the VBUS valid threshold 4 25 V leads to an OTG interrupt triggered by the session end detected bit SEDE...

Page 814: ...ort speed field in the host port control and status register PSPD bit in OTG_FS_HPRT and that the host is starting to drive SOFs FS or Keep alives LS The host is now ready to complete the peripheral enumeration by sending peripheral configuration commands Host suspend The application decides to suspend the USB activity by setting the port suspend bit in the host port control and status register PS...

Page 815: ...st channel transfer size registers HCTSIZx allow the application to program the transfer size parameters and read the transfer status Programming must be done before setting the channel enable bit in the host channel characteristics register Once the endpoint is enabled the packet count field is read only as the OTG FS core updates it according to the current transfer status The following transfer...

Page 816: ...ransaction request from the application and holds the IN or OUT channel number along with other information to perform a transaction on the USB The order in which the requests are written to the queue determines the sequence of the transactions on the USB interface At the beginning of each frame the host processes the periodic request queue first followed by the nonperiodic request queue The host ...

Page 817: ...r and the time remaining until the next SOF are tracked in the host frame number register HFNUM An SOF pulse signal generated at any SOF starting token and with a width of 12 system clock cycles can be made available externally on the SOF pin using the SOFOUTEN bit in the global control and configuration register The SOF pulse is also internally connected to the input trigger of timer 2 TIM2 so th...

Page 818: ...s are available while in the USB suspended state when the USB session is not yet valid or the device is disconnected Stop PHY clock STPPCLK bit in OTG_FS_PCGCCTL When setting the stop PHY clock bit in the clock gating control register most of the 48 MHz clock domain internal to the OTG full speed core is switched off by clock gating The dynamic power consumption due to the USB clock switching acti...

Page 819: ...atures 1 25 Kbyte of dedicated RAM with a sophisticated FIFO control mechanism The packet FIFO controller module in the OTG_FS core organizes RAM space into Tx FIFOs into which the application pushes the data to be temporarily stored before the USB transmission and into a single Rx FIFO where the data received from the USB are temporarily stored before retrieval popped by the application The numbe...

Page 820: ... receive RAM buffer All OUT endpoints share the same RAM buffer shared FIFO The OTG FS core can fill in the receive FIFO up to the limit for any host sequence of OUT tokens The application keeps receiving the Rx FIFO non empty interrupt RXFLVL bit in OTG_FS_GINTSTS as long as there is at least one packet available for download It reads the packet information from the receive status read and pop re...

Page 821: ...of the received data are also stored into the FIFO The size of the receive FIFO is configured in the receive FIFO size register GRXFSIZ The single receive FIFO architecture makes it highly efficient for the USB host to fill in the receive data buffer All IN configured host channels share the same RAM buffer shared FIFO The OTG FS core can fill in the receive FIFO up to the limit for any sequence o...

Page 822: ...e is available in both the periodic Tx FIFO and the periodic request queue The host periodic transmit FIFO and queue status register HPTXSTS can be read to know how much space is available in both OTG_FS core issues the non periodic Tx FIFO empty interrupt NPTXFE bit in OTG_FS_GINTSTS as long as the nonperiodic Tx FIFO is half or completely empty depending on the non periodic Tx FIFO empty level b...

Page 823: ...mplete status information is also pushed to the FIFO So one location must be allocated for this Transmit FIFO RAM allocation The minimum amount of RAM required for the host Non periodic Transmit FIFO is the largest maximum packet size among all supported non periodic OUT channels Typically two Largest Packet Sizes worth of space is recommended so that when the current packet is under transfer to t...

Page 824: ...ng of data over the USB It has a lot of empty space available in the receive buffer to autonomously fill it in with the data coming from the USB As the OTG_FS core is able to fill in the 1 25 Kbyte RAM buffer very efficiently and as 1 25 Kbyte of transmit receive data is more than enough to cover a full speed frame the USB system is able to withstand the maximum full speed data rate for up to one ...

Page 825: ...e interrupt mask register OTG interrupt register Core interrupt register 1 Device IN OUT endpoint interrupt registers 0 to 3 Device all endpoints interrupt register 16 9 OUT endpoints 3 0 IN endpoints Interrupt sources Host port control and status register Host all channels interrupt register Host channels interrupt mask registers 0 to 7 Host all channels interrupt mask register Host channels inte...

Page 826: ... specific registers Power and clock gating registers Data FIFO DFIFO access registers Only the Core global Power and clock gating Data FIFO access and host port control and status registers can be accessed in both host and device modes When the OTG_FS controller is operating in one mode either device or host the application must not access registers from the other mode If an illegal access occurs ...

Page 827: ...annel 1 FIFO 4 Kbyte 3000h Device EP x 1 1 Host channel x 1 1 FIFO 4 Kbyte Device EP x 1 Host channel x 1 FIFO 4 Kbyte Reserved DFIFO push pop to this region 2 0000h 3 FFFFh Direct access to data FIFO RAM for debugging 128 Kbyte DFIFO debug read write to this region ai15615b Table 198 Core global control and status registers CSRs Acronym Address offset Register name OTG_FS_GOTGCTL 0x000 OTG_FS con...

Page 828: ...FS core ID register OTG_FS_CID on page 851 OTG_FS_HPTXFSIZ 0x100 OTG_FS Host periodic transmit FIFO size register OTG_FS_HPTXFSIZ on page 851 OTG_FS_DIEPTXFx 0x104 0x124 0x138 OTG_FS device IN endpoint transmit FIFO size register OTG_FS_DIEPTXFx x 1 3 where x is the FIFO_number on page 852 1 The general rule is to use OTG_FS_HNPTXFSIZ for host mode and OTG_FS_DIEPTXF0 for device mode Table 198 Cor...

Page 829: ...and status registers Acronym Offset address Register name OTG_FS_DCFG 0x800 OTG_FS device configuration register OTG_FS_DCFG on page 863 OTG_FS_DCTL 0x804 OTG_FS device control register OTG_FS_DCTL on page 864 OTG_FS_DSTS 0x808 OTG_FS device status register OTG_FS_DSTS on page 865 OTG_FS_DIEPMSK 0x810 OTG_FS device IN endpoint common interrupt mask register OTG_FS_DIEPMSK on page 866 OTG_FS_DOEPMS...

Page 830: ...fer size register OTG_FS_DIEPTSIZ0 on page 881 OTG_FS_DTXFSTSx 0x918 OTG_FS device IN endpoint transmit FIFO status register OTG_FS_DTXFSTSx x 0 3 where x Endpoint_number on page 884 OTG_FS_DIEPTSIZx 0x930 0x950 0xAF0 OTG_FS device OUT endpoint x transfer size register OTG_FS_DOEPTSIZx x 1 3 where x Endpoint_number on page 884 OTG_FS_DOEPCTL0 0xB00 OTG_FS device control OUT endpoint 0 control regi...

Page 831: ... register section Address range Access Device IN Endpoint 0 Host OUT Channel 0 DFIFO Write Access Device OUT Endpoint 0 Host IN Channel 0 DFIFO Read Access 0x1000 0x1FFC w r Device IN Endpoint 1 Host OUT Channel 1 DFIFO Write Access Device OUT Endpoint 1 Host IN Channel 1 DFIFO Read Access 0x2000 0x2FFC w r Device IN Endpoint x 1 Host OUT Channel x 1 DFIFO Write Access Device OUT Endpoint x 1 Host...

Page 832: ...de 1 The OTG_FS controller is in B device mode Note Accessible in both device and host modes Bits 15 12 Reserved Bit 11 DHNPEN Device HNP enabled The application sets this bit when it successfully receives a SetFeature SetHNPEnable command from the connected USB host 0 HNP is not enabled in the application 1 HNP is enabled in the application Note Only accessible in device mode Bit 10 HSHNPEN host ...

Page 833: ...ceiver interface to initiate the session request the application must wait until VBUS discharges to 0 2 V after the B Session Valid bit in this register BSVLD bit in OTG_FS_GOTGCTL is cleared This discharge time varies between different PHYs and can be obtained from the PHY vendor 0 No session request 1 Session request Note Only accessible in device mode Bit 0 SRQSCS Session request success The co...

Page 834: ...of a USB host negotiation request The application must read the host negotiation success bit of the OTG_FS_GOTGCTL register HNGSCS in OTG_FS_GOTGCTL to check for success or failure Note Accessible in both device and host modes Bits 7 3 Reserved Bit 8 SRSSCHG Session request success status change The core sets this bit on the success or failure of a session request The application must read the ses...

Page 835: ...rrupt indicates that the Periodic TxFIFO is completely empty Note Only accessible in host mode Bit 7 TXFELVL TxFIFO empty level In device mode this bit indicates when IN endpoint Transmit FIFO empty interrupt TXFE in OTG_FS_DIEPINTx is triggered 0 the TXFE in OTG_FS_DIEPINTx interrupt indicates that the IN Endpoint TxFIFO is half empty 1 the TXFE in OTG_FS_DIEPINTx interrupt indicates that the IN ...

Page 836: ...s the core to device mode irrespective of the OTG_FS_ID input pin 0 Normal mode 1 Force device mode After setting the force bit the application must wait at least 25 ms before the change takes effect Note Accessible in both device and host modes Bit 29 FHMOD Force host mode Writing a 1 to this bit forces the core to host mode irrespective of the OTG_FS_ID input pin 0 Normal mode 1 Force host mode ...

Page 837: ...select This bit is always 1 with write only access Bits 6 3 Reserved Bits 2 0 TOCAL FS timeout calibration The number of PHY clocks that the application programs in this field is added to the full speed interpacket timeout duration in the core to account for any additional delays introduced by the PHY This can be required because the delay introduced by the PHY in generating the line state conditi...

Page 838: ...IFO 15 flush in device mode 10000 Flush all the transmit FIFOs in device or host mode Note Accessible in both device and host modes Bit 5 TXFFLSH TxFIFO flush This bit selectively flushes a single or all transmit FIFOs but cannot do so if the core is in the midst of a transaction The application must write this bit only after checking that the core is neither writing to the TxFIFO nor reading from...

Page 839: ...lows Clears the interrupts and all the CSR register bits except for the following bits RSTPDMODL bit in OTG_FS_PCGCCTL GAYEHCLK bit in OTG_FS_PCGCCTL PWRCLMP bit in OTG_FS_PCGCCTL STPPCLK bit in OTG_FS_PCGCCTL FSLSPCS bit in OTG_FS_HCFG DSPD bit in OTG_FS_DCFG All module state machines except for the AHB slave unit are reset to the Idle state and all the transmit FIFOs and the receive FIFO are flu...

Page 840: ...F NPTXFE RXFLVL SOF OTGINT MMIS CMOD rc_w1 r r r Res rc_w1 r r rc_w1 r r r r rc_w1 r rc_w1 r Bit 31 WKUPINT Resume remote wakeup detected interrupt In device mode this interrupt is asserted when a resume is detected on the USB In host mode this interrupt is asserted when a remote wakeup is detected on the USB Note Accessible in both device and host modes Bit 30 SRQINT Session request new session d...

Page 841: ...er Bit 20 IISOIXFR Incomplete isochronous IN transfer The core sets this interrupt to indicate that there is at least one isochronous IN endpoint on which the transfer is not completed in the current frame This interrupt is asserted along with the End of periodic frame interrupt EOPF bit in this register Note Only accessible in device mode Bit 19 OEPINT OUT endpoint interrupt The core sets this bi...

Page 842: ...he OTG_FS_DCTL register SGONAK bit in OTG_FS_DCTL set by the application has taken effect in the core This bit can be cleared by writing the Clear global OUT NAK bit in the OTG_FS_DCTL register CGONAK bit in OTG_FS_DCTL Note Only accessible in device mode Bit 6 GINAKEFF Global IN non periodic NAK effective Indicates that the Set global non periodic IN NAK bit in the OTG_FS_DCTL register SGINAK bit...

Page 843: ...nt The application must read the OTG Interrupt Status OTG_FS_GOTGINT register to determine the exact event that caused this interrupt The application must clear the appropriate status bit in the OTG_FS_GOTGINT register to clear this bit Note Accessible in both host and device modes Bit 1 MMIS Mode mismatch interrupt The core sets this bit when the application is trying to access A host mode regist...

Page 844: ... rw r rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 31 WUIM Resume remote wakeup detected interrupt mask 0 Masked interrupt 1 Unmasked interrupt Note Accessible in both host and device modes Bit 30 SRQIM Session request new session detected interrupt mask 0 Masked interrupt 1 Unmasked interrupt Note Accessible in both host and device modes Bit 29 DISCINT Disconnect detected interrupt m...

Page 845: ...accessible in device mode Bit 18 IEPINT IN endpoints interrupt mask 0 Masked interrupt 1 Unmasked interrupt Note Only accessible in device mode Bit 17 EPMISM Endpoint mismatch interrupt mask 0 Masked interrupt 1 Unmasked interrupt Note Only accessible in device mode Bit 16 Reserved Bit 15 EOPFM End of periodic frame interrupt mask 0 Masked interrupt 1 Unmasked interrupt Note Only accessible in dev...

Page 846: ...d interrupt 1 Unmasked interrupt Note Only accessible in device mode Bit 5 NPTXFEM Non periodic TxFIFO empty mask 0 Masked interrupt 1 Unmasked interrupt Note Only accessible in Host mode Bit 4 RXFLVLM Receive FIFO non empty mask 0 Masked interrupt 1 Unmasked interrupt Note Accessible in both device and host modes Bit 3 SOFM Start of frame mask 0 Masked interrupt 1 Unmasked interrupt Note Accessib...

Page 847: ...lication must only pop the Receive Status FIFO when the Receive FIFO non empty bit of the Core interrupt register RXFLVL bit in OTG_FS_GINTSTS is asserted Host mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PKTSTS DPID BCNT CHNUM r r r r Bits 31 21 Reserved Bits 20 17 PKTSTS Packet status Indicates the status of the received packet 0010 IN data ...

Page 848: ... the received packet 0001 Global OUT NAK triggers an interrupt 0010 OUT data packet received 0011 OUT transfer completed triggers an interrupt 0100 SETUP transaction completed triggers an interrupt 0110 SETUP data packet received Others Reserved Bits 16 15 DPID Data PID Indicates the Data PID of the received OUT data packet 00 DATA0 10 DATA1 01 DATA2 11 MDATA Bits 14 4 BCNT Byte count Indicates th...

Page 849: ...5 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NPTXFD TX0FD NPTXFSA TX0FSA r rw r rw Bits 31 16 NPTXFD Non periodic TxFIFO depth This value is in terms of 32 bit words Minimum value is 16 Maximum value is 256 Bits 15 0 NPTXFSA Non periodic transmit RAM start address This field contains the memory start address for non periodic transmit FIFO RAM Bits 31 16 TX0FD Endpoint 0 TxFIF...

Page 850: ...e has only IN requests 00 Non periodic transmit request queue is full 01 dx1 location available 10 dx2 locations available bxn dxn locations available 0 n dx8 Others Reserved Bits 15 0 NPTXFSAV Non periodic TxFIFO space available Indicates the amount of free space available in the non periodic TxFIFO Values are in terms of 32 bit words 00 Non periodic TxFIFO is full 01 dx1 word available 10 dx2 wo...

Page 851: ...6 5 4 3 2 1 0 PRODUCT_ID rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 0 PRODUCT_ID Product ID field Application programmable ID field 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PTXFSIZ PTXSA r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w...

Page 852: ...1 0 INEPTXFD INEPTXSA r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w r r w Bits 31 16 INEPTXFD IN endpoint TxFIFO depth This value is in terms of 32 bit words Minimum value is 16 The power on reset value of this register is specified as the largest IN endpoint ...

Page 853: ...t be performed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FRIVL rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 16 Reserved Bits 15 0 FRIVL Frame interval The value that the application programs to this field specifies the interval between two consecutive SOFs FS or Keep Alive tokens LS This field contains the number of PHY clocks that co...

Page 854: ... time remaining in the current frame in terms of PHY clocks This field decrements on each PHY clock When it reaches zero this field is reloaded with the value in the Frame interval register and a new SOF is transmitted on the USB Bits 15 0 FRNUM Frame number This field increments when a new SOF is transmitted on the USB and is cleared to 0 when it reaches 0x3FFF 31 30 29 28 27 26 25 24 23 22 21 20...

Page 855: ...ailable Indicates the number of free locations available to be written in the periodic transmit request queue This queue holds both IN and OUT requests 00 Periodic transmit request queue is full 01 dx1 location available 10 dx2 locations available bxn dxn locations available 0 dxn 8 Others Reserved Bits 15 0 PTXFSAVL Periodic transmit data FIFO space available Indicates the number of free location...

Page 856: ...interrupt to the application through the host port interrupt bit of the core interrupt register HPRTINT bit in OTG_FS_GINTSTS On a Port Interrupt the application must read this register and clear the bit that caused the interrupt For the rc_w1 bits the application must write a 1 to the bit to clear the interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...

Page 857: ...is bit after the reset sequence is complete 0 Port not in reset 1 Port in reset The application must leave this bit set for a minimum duration of at least 10 ms to start a reset on the port The application can leave it set for another 10 ms in addition to the required minimum duration before clearing the bit even though there is no maximum limit set by the USB standard Bit 7 PSUSP Port suspend The...

Page 858: ...OCA Port overcurrent active Indicates the overcurrent condition of the port 0 No overcurrent condition 1 Overcurrent condition Bit 3 PENCHNG Port enable disable change The core sets this bit when the status of the Port enable bit 2 in this register changes Bit 2 PENA Port enable A port is enabled only by the core after a reset sequence and is disabled by an overcurrent condition a disconnect condi...

Page 859: ...l as disabled Bit 29 ODDFRM Odd frame This field is set reset by the application to indicate that the OTG host must perform a transfer in an odd frame This field is applicable for only periodic isochronous and interrupt transactions 0 Even frame 1 Odd frame Bits 28 22 DAD Device address This field selects the specific device serving as the data source or sink Bits 21 20 MCNT Multicount This field ...

Page 860: ...n the OTG_FS_HAINT and OTG_FS_GINTSTS registers Bit 15 EPDIR Endpoint direction Indicates whether the transaction is IN or OUT 0 OUT 1 IN Bits 14 11 EPNUM Endpoint number Indicates the endpoint number on the device serving as the data source or sink Bits 10 0 MPSIZ Maximum packet size Indicates the maximum packet size of the associated endpoint 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14...

Page 861: ... 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DTERRM FRMORM BBERRM TXERRM NYET ACKM NAKM STALLM Reserved CHHM XFRCM rw rw rw rw rw rw rw rw rw rw Bits 31 11 Reserved Bit 10 DTERRM Data toggle error mask 0 Masked interrupt 1 Unmasked interrupt Bit 9 FRMORM Frame overrun mask 0 Masked interrupt 1 Unmasked interrupt Bit 8 BBERRM Babble error mask 0 Masked interrupt 1 Unmasked interrupt Bit 7 TXERRM Tr...

Page 862: ...eld with the type of PID to use for the initial transaction The host maintains this field for the rest of the transfer 00 DATA0 01 DATA2 10 DATA1 11 MDATA non control SETUP control Bits 28 19 PKTCNT Packet count This field is programmed by the application with the expected number of packets to be transmitted OUT or received IN The host decrements this count on every successful transmission or rece...

Page 863: ...f the frame interval Bits 10 4 DAD Device address The application must program this field after every SetAddress control command Bit 3 Reserved Bit 2 NZLSOHSK Non zero length status OUT handshake The application can use this field to select the handshake the core sends on receiving a nonzero length data packet during the OUT transaction of a control transfer s Status stage 1 Send a STALL handshake...

Page 864: ... after making sure that the Global OUT NAK effective bit in the Core interrupt register GONAKEFF bit in OTG_FS_GINTSTS is cleared Bit 8 CGINAK Clear global IN NAK A write to this field clears the Global IN NAK Bit 7 SGINAK Set global IN NAK A write to this field sets the Global non periodic IN NAK The application uses this bit to send a NAK handshake on all non periodic IN endpoints The applicatio...

Page 865: ...at the device is connected and the device does not receive signals on the USB The core stays in the disconnected state until the application clears this bit 0 Normal operation When this bit is cleared after a soft disconnect the core generates a device connect event to the USB host When the device is reconnected the USB host restarts device enumeration 1 The core generates a device disconnect even...

Page 866: ...NUMSPD Enumerated speed Indicates the speed at which the OTG_FS controller has come up after speed detection through a chirp sequence 01 Reserved 10 Reserved 11 Full speed PHY clock is running at 48 MHz Others reserved Bit 0 SUSPSTS Suspend status In device mode this bit is set as long as a Suspend condition is detected on the USB The core enters the Suspended state when there is no activity on th...

Page 867: ...interrupt Bit 2 Reserved Bit 1 EPDM Endpoint disabled interrupt mask 0 Masked interrupt 1 Unmasked interrupt Bit 0 XFRCM Transfer completed interrupt mask 0 Masked interrupt 1 Unmasked interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OTEPDM STUPM Reserved EPDM XFRCM rw rw rw rw Bits 31 5 Reserved Bit 4 OTEPDM OUT token received when endpoint ...

Page 868: ...or OUT endpoints and 16 bits for IN endpoints For a bidirectional endpoint the corresponding IN and OUT interrupt bits are used Bits in this register are set and cleared when the application sets and clears bits in the corresponding Device Endpoint x interrupt register OTG_FS_DIEPINTx OTG_FS_DOEPINTx 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OEPINT IEPIN...

Page 869: ...18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OEPM IEPM rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 16 OEPM OUT EP interrupt mask bits One per OUT endpoint Bit 16 for OUT EP 0 bit 18 for OUT EP 3 0 Masked interrupt 1 Unmasked interrupt Bits 15 0 IEPM IN EP interrupt mask bits One bit per IN endpoint Bit 0 for IN EP 0 bit 3 for IN EP 3 0 ...

Page 870: ...23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DVBUSP rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 12 Reserved Bits 11 0 DVBUSP Device VBUS pulsing time Specifies the VBUS pulsing time during SRP This value equals VBUS pulsing time in PHY clocks 1 024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved INEPTXFEM rw rw rw rw rw rw rw...

Page 871: ...that endpoint is complete The application must wait for the Endpoint disabled interrupt before treating the endpoint as disabled The core clears this bit before setting the Endpoint disabled interrupt The application must set this bit only if Endpoint enable is already set for this endpoint Bits 29 28 Reserved Bit 27 SNAK Set NAK A write to this bit sets the NAK bit for the endpoint Using this bit...

Page 872: ...kets with an ACK handshake Bit 16 Reserved Bit 15 USBAEP USB active endpoint This bit is always set to 1 indicating that control endpoint 0 is always active in all configurations and interfaces Bits 14 2 Reserved Bits 1 0 MPSIZ Maximum packet size The application must program this field with the maximum packet size for the current logical endpoint 00 64 bytes 01 32 bytes 10 16 bytes 11 8 bytes 31 ...

Page 873: ... on an endpoint The core can also set this bit for OUT endpoints on a Transfer completed interrupt or after a SETUP is received on the endpoint Bit 26 CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint Bits 25 22 TXFNUM TxFIFO number These bits specify the FIFO number associated with this endpoint Each active IN endpoint must be programmed to a separate FIFO number This field i...

Page 874: ... frame number in which it intends to transmit receive isochronous data for this endpoint using the SEVNFRM and SODDFRM fields in this register 0 Even frame 1 Odd frame DPID Endpoint data PID Applies to interrupt bulk IN endpoints only Contains the PID of the packet to be received or transmitted on this endpoint The application must program the PID of the first packet to be received or transmitted ...

Page 875: ...able control OUT endpoint 0 Bits 29 28 Reserved Bit 27 SNAK Set NAK A write to this bit sets the NAK bit for the endpoint Using this bit the application can control the transmission of NAK handshakes on an endpoint The core can also set this bit on a Transfer completed interrupt or after a SETUP is received on the endpoint Bit 26 CNAK Clear NAK A write to this bit clears the NAK bit for the endpoi...

Page 876: ...ackets with an ACK handshake Bit 16 Reserved Bit 15 USBAEP USB active endpoint This bit is always set to 1 indicating that a control endpoint 0 is always active in all configurations and interfaces Bits 14 2 Reserved Bits 1 0 MPSIZ Maximum packet size The maximum packet size for control OUT endpoint 0 is the same as what is programmed in control IN endpoint 0 00 64 bytes 01 32 bytes 10 16 bytes 11...

Page 877: ...he endpoint Using this bit the application can control the transmission of NAK handshakes on an endpoint The core can also set this bit for OUT endpoints on a Transfer Completed interrupt or after a SETUP is received on the endpoint Bit 26 CNAK Clear NAK A write to this bit clears the NAK bit for the endpoint Bits 25 22 Reserved Bit 21 STALL STALL handshake Applies to non control non isochronous O...

Page 878: ...s data for this endpoint using the SEVNFRM and SODDFRM fields in this register 0 Even frame 1 Odd frame DPID Endpoint data PID Applies to interrupt bulk OUT endpoints only Contains the PID of the packet to be received or transmitted on this endpoint The application must program the PID of the first packet to be received or transmitted on this endpoint after the endpoint is activated The applicatio...

Page 879: ...d when the TxFIFO for this endpoint is either half or completely empty The half or completely empty status is determined by the TxFIFO Empty Level bit in the OTG_FS_GAHBCFG register TXFELVL bit in OTG_FS_GAHBCFG Bit 6 INEPNE IN endpoint NAK effective This bit can be cleared when the application clears the IN endpoint NAK by writing to the CNAK bit in OTG_FS_DIEPCTLx This interrupt indicates that t...

Page 880: ... 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved B2BSTUP Reserved OTEPDIS STUP Reserved EPDISD XFRC rc_ w1 rw rc_ w1 rc_ w1 rc_ w1 rc_ w1 Bits 31 7 Reserved Bit 6 B2BSTUP Back to back SETUP packets received Applies to control OUT endpoint only This bit indicates that the core has received more than three back to back SETUP packets for this particular endpoint Bit 5 Reserved Bit 4 OTEPDIS OUT token receiv...

Page 881: ...3 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PKTCNT Reserved XFRSIZ rw rw rw rw rw rw rw rw rw Bits 31 21 Reserved Bits 20 19 PKTCNT Packet count Indicates the total number of USB packets that constitute the Transfer Size amount of data for endpoint 0 This field is decremented every time a packet maximum size or short packet is read from the TxFIFO Bits 18 7 Reserved Bits ...

Page 882: ...6 5 4 3 2 1 0 Reserved STUPC NT Reserved PKTCNT Reserved XFRSIZ rw rw rw rw rw rw rw rw rw rw Bit 31 Reserved Bits 30 29 STUPCNT SETUP packet count This field specifies the number of back to back SETUP data packets the endpoint can receive 01 1 packet 10 2 packets 11 3 packets Bits 28 20 Reserved Bit 19 PKTCNT Packet count This field is decremented to zero after a packet is written into the RxFIFO...

Page 883: ...rw rw rw rw rw rw Bit 31 Reserved Bits 30 29 MCNT Multi count For periodic IN endpoints this field indicates the number of packets that must be transmitted per frame on the USB The core uses this field to calculate the data PID for isochronous IN endpoints 01 1 packet 10 2 packets 11 3 packets Bit 28 19 PKTCNT Packet count Indicates the total number of USB packets that constitute the Transfer Size...

Page 884: ...ion can only read this register once the core has cleared the Endpoint enable bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved INEPTFSAV r r r r r r r r r r r r r r r r 31 16 Reserved 15 0 INEPTFSAV IN endpoint TxFIFO space available Indicates the amount of free space available in the Endpoint TxFIFO Values are in terms of 32 bit words 0x0 Endpoint...

Page 885: ...e transfer size can be set to the maximum packet size of the endpoint to be interrupted at the end of each packet The core decrements this field every time a packet is read from the RxFIFO and written to the external memory 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PHYSUSP Reserved GATEHCLK STPPCLK rw rw rw Bit 31 5 Reserved Bit 4 PHYSUSP PHY Su...

Page 886: ...CHG Reserved PTXFE HCINT HPRTINT Reserved IPXFR INCOMPISOOUT IISOIXFR OEPINT IEPINT Reserved EOPF ISOODRP ENUMDNE USBRST USBSUSP ESUSP Reserved GOUTNAKEFF GINAKEFF NPTXFE RXFLVL SOF OTGINT MMIS CMOD Reset value 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0x018 OTG_FS_GINT MSK WUIM SRQIM DISCINT CIDSCHGM Reserved PTXFEM HCIM PRTIM Reserved IPXFRM IISOOXFRM IISOIXFRM OEPINT IEPINT EPMISM Reser...

Page 887: ...4 OTG_FS_HFIR Reserved FRIVL Reset value 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0 0 0x408 OTG_FS_HFNU M FTREM FRNUM Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x410 OTG_FS_HPTX STS PTXQTOP PTXQSAV PTXFSAVL Reset value 0 0 0 0 0 0 0 0 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 0x414 OTG_FS_HAIN T Reserved HAINT Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x418 OTG_FS_HAIN...

Page 888: ... TXERR Reserved ACK NAK STALL Reserved CHH XFRC Reset value 0 0 0 0 0 0 0 0 0 0x548 OTG_FS_HCIN T2 Reserved DTERR FRMOR BBERR TXERR Reserved ACK NAK STALL Reserved CHH XFRC Reset value 0 0 0 0 0 0 0 0 0 0x568 OTG_FS_HCIN T3 Reserved DTERR FRMOR BBERR TXERR Reserved ACK NAK STALL Reserved CHH XFRC Reset value 0 0 0 0 0 0 0 0 0 0x588 OTG_FS_HCIN T4 Reserved DTERR FRMOR BBERR TXERR Reserved ACK NAK S...

Page 889: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x530 OTG_FS_HCTS IZ1 Reserved DPID PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x550 OTG_FS_HCTS IZ2 Reserved DPID PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x570 OTG_FS_HCTS IZ3 Reserved DPID PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 890: ...0 0x834 OTG_FS_DIEP EMPMSK Reserved INEPTXFEM Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x900 OTG_FS_DIEP CTL0 EPENA EPDIS Reserved SNAK CNAK TXFNUM Stall Reserved EPTY P NAKSTS Reserved USBAEP Reserved MPSI Z Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0x918 TG_FS_DTXFS TS0 Reserved INEPTFSAV Reset value 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0x920 OTG_FS_DIEP CTL1 EPENA EPDIS SODDFRM SD1PID SD0PID SEVN...

Page 891: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xB60 OTG_FS_DOEP CTL3 EPENA EPDIS SODDFRM SD0PID SEVNFRM SNAK CNAK Reserved Stall SNPM EPTYP NAKSTS EONUM DPID USBAEP Reserved MPSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x908 OTG_FS_DIEPI NT0 Reserved TXFE INEPNE Reserved ITTXFE TOC Reserved EPDISD XFRC Reset value 1 0 0 0 0 0 0x928 OTG_FS_DIEPI NT1 Reserved TXFE INEPNE Reserved IT...

Page 892: ...eset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x950 OTG_FS_DIEP TSIZ2 Reserved MCNT PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x970 OTG_FS_DIEP TSIZ3 Reserved MCNT PKTCNT XFRSIZ Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0xB10 OTG_FS_DOEP TSIZ0 Reserved STUP CNT Reserved PKTCNT Reserved XFRSIZ R...

Page 893: ... fields in the OTG_FS_GAHBCFG register Global interrupt mask bit GINTMSK 1 RxFIFO non empty RXFLVL bit in OTG_FS_GINTSTS Periodic TxFIFO empty level 2 Program the following fields in the OTG_FS_GUSBCFG register HNP capable bit SRP capable bit FS timeout calibration field USB turnaround time field 3 The software must unmask the following bits in the OTG_FS_GINTMSK register OTG interrupt mask Mode m...

Page 894: ... FIFO 13 Program the OTG_FS_HNPTXFSIZ register to select the size and the start address of the Non periodic transmit FIFO for non periodic transactions 14 Program the OTG_FS_HPTXFSIZ register to select the size and start address of the periodic transmit FIFO for periodic transactions To communicate with devices the system software must initialize and enable at least one channel 28 17 3 Device init...

Page 895: ...es and the expected number of packets including short packets The application must program the PID field with the initial data PID to be used on the first OUT transaction or to be expected from the first IN transaction 6 Program the OTG_FS_HCCHARx register of the selected channel with the device s endpoint characteristics such as type speed direction and so forth The channel can be enabled by sett...

Page 896: ...s Writing the transmit FIFO The OTG_FS host automatically writes an entry OUT request to the periodic non periodic request queue along with the last Word write of a packet The application must ensure that at least one free space is available in the periodic non periodic request queue before starting to write to the transmit FIFO The application must always write to the transmit FIFO in Words If th...

Page 897: ...ulk and control OUT SETUP transactions A typical bulk or control OUT SETUP pipelined transaction level operation is shown in Figure 313 See channel 1 ch_1 Two bulk OUT packets are transmitted A control RXFLVL interrupt Read the received packet from the Receive FIFO Read OTG_FS_GRXSTSP PKTSTS 0b0010 Yes Yes Unmask RXFLVL interrupt BCNT 0 No Mask RXFLVL interrupt Yes Unmask RXFLVL interrupt No No St...

Page 898: ...ETUP operations The sequence of operations in channel 1 is as follows a Initialize channel 1 b Write the first packet for channel 1 c Along with the last Word write the core writes an entry to the non periodic request queue d As soon as the non periodic queue becomes non empty the core attempts to send an OUT token in the current frame e Write the second last packet for channel 1 f The core genera...

Page 899: ...K ACK Host Application Device AHB USB OUT DATA0 MPS 1 MPS 1 MPS write_tx_fifo ch_1 init_reg ch_1 set_ch_en ch_2 init_reg ch_2 write_tx_fifo ch_1 set_ch_en ch_2 ch_2 ch_2 ch_1 ch_1 De allocate ch_1 IN ch_2 ch_2 ch_2 ch_1 ACK OUT set_ch_en ch_2 Non Periodic Request Queue Assume that this queue can hold 4 entries 4 1 6 ACK DATA0 IN ACK read_rx_sts read_rx_fifo 1 MPS set_ch_en ch_2 1 MPS read_rx_stsre...

Page 900: ... Mask CHH if Transfer Done or Error_count 3 De allocate Channel else Re initialize Channel else if ACK Reset Error Count Mask ACK The application is expected to write the data packets into the transmit FIFO as and when the space is available in the transmit FIFO and the Request queue The application can make use of the NPTXFE interrupt in OTG_FS_GINTSTS to find the transmit FIFO space b Bulk Contr...

Page 901: ... Count The application is expected to write the requests as and when the Request queue space is available and until the XFRC interrupt is received Bulk and control IN transactions A typical bulk or control IN pipelined transaction level operation is shown in Figure 314 See channel 2 ch_2 The assumptions are The application is attempting to receive two maximum packet size packets transfer size 1 02...

Page 902: ...ine the number of bytes received then read the receive FIFO accordingly Following this unmask the RXFLVL interrupt ACK Host Application Device AHB USB OUT DATA0 MPS 1 MPS 1 MPS write_tx_fifo ch_1 init_reg ch_1 set_ch_en ch_2 init_reg ch_2 write_tx_fifo ch_1 set_ch_en ch_2 ch_2 ch_2 ch_1 ch_1 De allocate ch_1 IN ch_2 ch_2 ch_2 ch_1 ACK OUT set_ch_en ch_2 Non Periodic Request Queue Assume that this ...

Page 903: ... transfers Setup Data or Status stage OUT transactions are performed similarly to the bulk OUT transactions explained previously Data or Status stage IN transactions are performed similarly to the bulk IN transactions explained previously For all three stages the application is expected to set the EPTYP field in OTG_FS_HCCHAR1 to Control During the Setup stage the application is expected to set th...

Page 904: ...lication Device AHB USB OUT DATA0 MPS 1 MPS 1 MPS write_tx_fifo ch_1 init_reg ch_1 set_ch_en ch_2 init_reg ch_2 write_tx_fifo ch_1 IN OUT DATA1 MPS Periodic Request Queue Assume that this queue can hold 4 entries 1 5 DATA0 IN RXFLVL interrupt 1 MPS read_rx_sts read_rx_fifo read_rx_sts 1 2 3 4 6 2 3 6 7 8 9 Odd micro frame Even micro frame init_reg ch_1 set_ch_en ch_2 init_reg ch_2 write_tx_fifo ch...

Page 905: ...if Transfer Done or Error_count 3 De allocate Channel else Re initialize Channel in next b_interval 1 Frame else if ACK Reset Error Count Mask ACK The application uses the NPTXFE interrupt in OTG_FS_GINTSTS to find the transmit FIFO space b Interrupt IN Unmask NAK TXERR XFRC BBERR STALL FRMOR DTERR if XFRC Reset Error Count Mask ACK if OTG_FS_HCTSIZx PKTCNT 0 De allocate Channel else Transfer Done...

Page 906: ...sable Channel if STALL or BBERR Reset Error Count Transfer Done 1 else if FRMOR Reset Error Count else if TXERR Increment Error Count Unmask ACK Unmask CHH Disable Channel else if CHH Mask CHH if Transfer Done or Error_count 3 De allocate Channel else Re initialize Channel in next b_interval 1 Frame else if ACK Reset Error Count Mask ACK ...

Page 907: ...ket is received and written to the receive FIFO the OTG_FS host generates an RXFLVL interrupt f In response to the RXFLVL interrupt read the received packet status to determine the number of bytes received then read the receive FIFO accordingly The application must mask the RXFLVL interrupt before reading the receive FIFO and unmask after reading the entire packet g The core generates the RXFLVL i...

Page 908: ...est queue depth 4 The sequence of operations is as follows a Initialize and enable channel 1 The application must set the ODDFRM bit in OTG_FS_HCCHAR1 b Write the first packet for channel 1 c Along with the last Word write of each packet the OTG_FS host writes an entry to the periodic request queue d The OTG_FS host attempts to send the OUT token in the next frame odd e The OTG_FS host generates t...

Page 909: ... AHB USB OUT DATA0 MPS 1 MPS 1 MPS write_tx_fifo ch_1 init_reg ch_1 set_ch_en ch_2 init_reg ch_2 write_tx_fifo ch_1 IN OUT DATA1 MPS Periodic Request Queue Assume that this queue can hold 4 entries 1 5 DATA0 IN RXFLVL interrupt 1 MPS read_rx_sts read_rx_fifo read_rx_sts 1 2 3 4 6 2 3 6 7 8 9 Odd micro frame Even micro frame init_reg ch_1 set_ch_en ch_2 init_reg ch_2 write_tx_fifo ch_1 init_reg ch_...

Page 910: ...us IN Unmask TXERR XFRC FRMOR BBERR if XFRC or FRMOR if XFRC and OTG_FS_HCTSIZx PKTCNT 0 Reset Error Count De allocate Channel else Unmask CHH Disable Channel else if TXERR or BBERR Increment Error Count Unmask CHH Disable Channel else if CHH Mask CHH if Transfer Done or Error_count 3 De allocate Channel else Re initialize Channel ...

Page 911: ...must read and ignore the receive packet status when the receive packet status is not an IN data packet PKTSTS bit in OTG_FS_GRXSTSR 0b0010 h The core generates an XFRC interrupt as soon as the receive packet status is read i In response to the XFRC interrupt read the PKTCNT field in OTG_FS_HCTSIZ2 If PKTCNT 0 in OTG_FS_HCTSIZ2 disable the channel before re initializing the channel for the next tra...

Page 912: ... bits INEP0 1 in OTG_FS_DAINTMSK control 0 IN endpoint OUTEP0 1 in OTG_FS_DAINTMSK control 0 OUT endpoint STUP 1 in DOEPMSK XFRC 1 in DOEPMSK XFRC 1 in DIEPMSK TOC 1 in DIEPMSK 3 Set up the Data FIFO RAM for each of the FIFOs Program the OTG_FS_GRXFSIZ register to be able to receive control OUT data and setup data If thresholding is not enabled at a minimum this must be equal to 1 max packet size ...

Page 913: ...ion or alternate setting are not valid in the new configuration or alternate setting These invalid endpoints must be deactivated 4 Unmask the interrupt for each active endpoint and mask the interrupts for all inactive endpoints in the OTG_FS_DAINTMSK register 5 Set up the Data FIFO RAM for each FIFO 6 After all required endpoints are configured the application must program the core to send a statu...

Page 914: ...cket s byte count is not 0 the byte count amount of data is popped from the receive Data FIFO and stored in memory If the received packet byte count is 0 no data is popped from the receive data FIFO 4 The receive FIFO s packet status readout indicates one of the following a Global OUT NAK pattern PKTSTS Global OUT NAK BCNT 0x000 EPNUM Don t Care 0x0 DPID Don t Care 0b00 These data indicate that th...

Page 915: ...ence for handling SETUP transactions Application requirements 1 To receive a SETUP packet the STUPCNT field OTG_FS_DOEPTSIZx in a control OUT endpoint must be programmed to a non zero value When the application programs the STUPCNT field to a non zero value the core receives SETUP packets and writes them to the receive FIFO irrespective of the NAK status and EPENA bit setting in OTG_FS_DOEPCTLx Th...

Page 916: ...he core internally sets the IN NAK and OUT NAK bits for the control IN OUT endpoints on which the SETUP packet was received 6 For every SETUP packet received on the USB 3 Words of data are written to the receive FIFO and the STUPCNT field is decremented by 1 The first Word contains control information used internally by the core The second Word contains the first 4 bytes of the SETUP command The t...

Page 917: ...of the space availability in the receive FIFO non isochronous OUT tokens receive a NAK handshake response and the core ignores isochronous OUT data packets 2 The core writes the Global OUT NAK pattern to the receive FIFO The application must reserve enough receive FIFO space to write this data pattern 3 When the application pops the Global OUT NAK pattern Word from the receive FIFO the core sets t...

Page 918: ...CTL 1 in CGONAK 6 If the application has masked this interrupt earlier it must be unmasked as follows GINAKEFFM 1 in GINTMSK Disabling an OUT endpoint The application must use this sequence to disable an OUT endpoint that it has enabled Application programming sequence 1 Before disabling any OUT endpoint the application must enable Global OUT NAK mode in the core SGONAK 1 in OTG_FS_DCTL 2 Wait for...

Page 919: ...d its status are written to the receive FIFO Every packet maximum packet size or short packet written to the receive FIFO decrements the packet count field for that endpoint by 1 OUT data packets received with bad data CRC are flushed from the receive FIFO automatically After sending an ACK for the packet on the USB the core discards non isochronous OUT data packets that the host which cannot dete...

Page 920: ...a transfer This section describes a regular isochronous OUT data transfer Application requirements 1 All the application requirements for non isochronous OUT data transfers also apply to isochronous OUT data transfers 2 For isochronous OUT data transfers the transfer size and packet count fields must always be set to the number of maximum packet size packets that can be received in a single frame ...

Page 921: ... conditions is met RXDPID D0 in OTG_FS_DOEPTSIZx and the number of USB packets in which this payload was received 1 RXDPID D1 in OTG_FS_DOEPTSIZx and the number of USB packets in which this payload was received 2 RXDPID D2 in OTG_FS_DOEPTSIZx and the number of USB packets in which this payload was received 3 The number of USB packets in which this payload was received Application programmed initia...

Page 922: ...f both the following conditions are met EONUM bit in OTG_FS_DOEPCTLx SOFFN 0 in OTG_FS_DSTS EPENA 1 in OTG_FS_DOEPCTLx 4 The previous step must be performed before the SOF interrupt in OTG_FS_GINTSTS is detected to ensure that the current frame number is not changed 5 For isochronous OUT endpoints with incomplete transfers the application must discard the data in the memory and disable the endpoin...

Page 923: ...e there 3 After writing the complete packet in the RxFIFO the core then asserts the RXFLVL interrupt in OTG_FS_GINTSTS 4 On receiving the PKTCNT number of USB packets the core internally sets the NAK bit for this endpoint to prevent it from receiving any more packets 5 The application processes the interrupt and reads the data from the RxFIFO 6 When the application has read all the data equivalent...

Page 924: ...fore writing the data into the data FIFO Typically the application must do a read modify write on the OTG_FS_DIEPCTLx register to avoid modifying the contents of the register except for setting the Endpoint Enable bit The application can write multiple packets for the same endpoint into the transmit FIFO if space is available For periodic IN endpoints the application must write packets only for on...

Page 925: ... Application programming sequence 1 The application must stop writing data on the AHB for the IN endpoint to be disabled 2 The application must set the endpoint in NAK mode SNAK 1 in OTG_FS_DIEPCTLx 3 Wait for the INEPNE interrupt in OTG_FS_DIEPINTx 4 Set the following bits in the OTG_FS_DIEPCTLx register for the endpoint that must be disabled EPDIS 1 in OTG_FS_DIEPCTLx SNAK 1 in OTG_FS_DIEPCTLx 5...

Page 926: ... the application must read the Transfer size register to determine how much data posted in the transmit FIFO have already been sent on the USB 4 Data fetched into transmit FIFO Application programmed initial transfer size core updated final transfer size Data transmitted on USB application programmed initial packet count Core updated final packet count MPSIZ EPNUM Data yet to be transmitted on USB...

Page 927: ...the CNAK and EPENA Endpoint Enable bits 3 When transmitting non zero length data packet the application must poll the OTG_FS_DTXFSTSx register where x is the FIFO number associated with that endpoint to determine whether there is enough space in the data FIFO The application can optionally use TXFE in OTG_FS_DIEPINTx before writing the data Generic periodic IN data transfers This section describes...

Page 928: ...ted transmit FIFO for the endpoint 3 Every time the application writes a packet to the transmit FIFO the transfer size for that endpoint is decremented by the packet size The data are fetched from application memory until the transfer size for the endpoint becomes 0 4 When an IN token is received for a periodic endpoint the core transmits the data in the FIFO if available If the complete data payl...

Page 929: ...sochronous IN transfer IISOIXFR interrupt in OTG_FS_GINTSTS with none of the aforementioned interrupts indicates the core did not receive at least 1 periodic IN token in the current frame Incomplete isochronous IN data transfers This section describes what the application must do on an incomplete isochronous IN data transfer Internal data flow 1 An isochronous IN transfer is treated as incomplete ...

Page 930: ...the application can stall a non isochronous endpoint Application programming sequence 1 Disable the IN endpoint to be stalled Set the STALL bit as well 2 EPDIS 1 in OTG_FS_DIEPCTLx when the endpoint is already enabled STALL 1 in OTG_FS_DIEPCTLx The STALL bit always takes precedence over the NAK bit 3 Assertion of the Endpoint Disabled interrupt in OTG_FS_DIEPINTx indicates to the application that ...

Page 931: ...s IN OUT packets were dropped Choosing the value of TRDT in OTG_FS_GUSBCFG The value in TRDT OTG_FS_GUSBCFG is the time it takes for the MAC in terms of PHY clocks after it has received an IN token to get the FIFO status and thus the first data from the PFC block This time involves the synchronization delay between the PHY and AHB clocks The worst case delay for this is when the AHB clock is the s...

Page 932: ...ce to turn on VBUS power A device must perform both data line pulsing and VBUS pulsing but a host can detect either data line pulsing or VBUS pulsing for SRP HNP is a method by which the B device negotiates and switches to host role In Negotiated mode after HNP the B device suspends the bus and reverts to the device role A device session request protocol The application must set the SRP capable bi...

Page 933: ...es VBUS above the A device session valid 2 0 V minimum for VBUS pulsing The OTG_FS controller interrupts the application on detecting SRP The Session request detected bit is set in Global interrupt status register SRQINT set in OTG_FS_GINTSTS 6 The application must service the Session request detected interrupt and turn on the port power bit by writing the port power bit in the host port control a...

Page 934: ... must wait until VBUS discharges to 0 2 V after BSVLD in OTG_FS_GOTGCTL is deasserted This discharge time can be obtained from the transceiver vendor and varies from one transceiver to another 3 The application initiates SRP by writing the session request bit in the OTG Control and status register The OTG_FS controller perform data line pulsing followed by VBUS pulsing 4 The host detects SRP from ...

Page 935: ...d status register 3 When the B device observes a USB suspend it disconnects indicating the initial condition for HNP The B device initiates HNP only when it must switch to the host role otherwise the bus continues to be suspended The OTG_FS controller sets the host negotiation detected interrupt in the OTG interrupt status register indicating the start of HNP The OTG_FS controller deasserts the DM...

Page 936: ...LLDOWN signal from core to PHY to enable disable the pull down on the DP line inside the PHY DMPULLDOWN signal from core to PHY to enable disable the pull down on the DM line inside the PHY 1 The A device sends the SetFeature b_hnp_enable descriptor to enable HNP support The OTG_FS controller s ACK response indicates that it supports HNP The application must set the device HNP enable bit in the OT...

Page 937: ...TS to determine host mode operation 3 The application sets the reset bit PRST in OTG_FS_HPRT and the OTG_FS controller issues a USB reset and enumerates the A device for data traffic 4 The OTG_FS controller continues the host role of initiating traffic and when done suspends the bus by writing the Port suspend bit in the host port control and status register 5 In Negotiated mode when the A device ...

Page 938: ...xx connectivity line devices 29 1 Ethernet introduction Portions Copyright c 2004 2005 Synopsys Inc All rights reserved Used with permission The Ethernet peripheral enables the STM32F107xx to transmit and receive data over Ethernet in compliance with the IEEE 802 3 2002 standard The Ethernet provides a configurable flexible peripheral to meet the needs of various applications and customers It supp...

Page 939: ...k with masks for each byte 64 bit Hash filter optional for multicast and unicast DA addresses Option to pass all multicast addressed frames Promiscuous mode support to pass all frames without any filtering for network monitoring Passes all incoming packets as per filter with a status report Separate 32 bit status returned for transmission and reception packets Supports IEEE 802 1Q VLAN tag detecti...

Page 940: ...terface Software can select the type of AHB burst fixed or indefinite burst in the AHB Master interface Option to select address aligned bursts from AHB master port Optimization for packet oriented DMA transfers with frame delimiters Byte aligned addressing for data buffer support Dual buffer ring or linked list chained descriptor chaining Descriptor architecture allowing large blocks of data tran...

Page 941: ...TH_MII_COL COL PA3 Floating input reset state ETH_MII_RX_DV ETH_RMII_CRS_DV RX_DV CRS_DV PA7 Floating input reset state ETH_MII_RXD0 ETH_RMII_RXD0 RXD0 RXD0 PC4 Floating input reset state ETH_MII_RXD1 ETH_RMII_RXD1 RXD1 RXD1 PC5 Floating input reset state ETH_MII_RXD2 RXD2 PB0 Floating input reset state ETH_MII_RXD3 RXD3 PB1 Floating input reset state ETH_MII_RX_ER RX_ER PB10 Floating input reset ...

Page 942: ...nsferred to system memory by the DMA The Ethernet peripheral also includes an SMI to communicate with external PHY A set of configuration registers permit the user to select the wanted mode and features for the MAC and the DMA controller Note The AHB clock frequency must be at least 25 MHz when the Ethernet is used Figure 325 ETH block diagram 1 For AHB connections please refer to Figure 1 System ...

Page 943: ...e consists of eight fields Preamble each transaction read or write can be initiated with the preamble field that corresponds to 32 contiguous logic one bits on the MDIO line with 32 corresponding cycles on MDC This field is used to establish synchronization with the PHY device Start the start of frame is defined by a 01 pattern to verify transitions on the line from the default logic one state to ...

Page 944: ...s ongoing Write operations to the MII Address register or the MII Data Register during this period are ignored the Busy bit is high and the transaction is completed without any error After the Write operation has completed the SMI indicates this by resetting the Busy bit Figure 327 shows the frame format for the write operation Figure 327 MDIO timing and frame structure Write cycle SMI read operat...

Page 945: ...ble 207 shows how to set the clock ranges 29 4 2 Media independent interface MII The media independent interface MII defines the interconnection between the MAC sublayer and the PHY for data transfer at 10 Mbit s and 100 Mbit s Table 207 Clock range Selection HCLK clock MDC clock 0000 60 72 MHz AHB clock 42 0001 Reserved 0010 20 35 MHz AHB clock 16 0011 35 60 MHz AHB clock 26 0100 0101 0110 0111 R...

Page 946: ...are idle The PHY must ensure that the MII_CS signal remains asserted throughout the duration of a collision condition This signal is not required to transition synchronously with respect to the TX and RX clocks In full duplex mode the state of this signal is don t care for the MAC sublayer MII_COL collision detection must be asserted by the PHY upon detection of a collision on the medium and must ...

Page 947: ...ith an external 25 MHz as shown in Figure 330 Instead of using an external 25 MHz quartz to provide this clock the STM32F107xx microcontroller can output this signal on its MCO pin In this case the PLL multiplier has to be configured so as to get the desired frequency on the MCO pin from the 25 MHz external quartz Table 208 TX interface signal encoding MII_TX_EN MII_TXD 3 0 Description 0 0000 thro...

Page 948: ...2 5 decrease in pin count The RMII is instantiated between the MAC and the PHY This helps translation of the MAC s MII into the RMII The RMII block has the following characteristics It supports 10 Mbit s and 100 Mbit s operating rates The clock reference must be doubled to 50 MHz The same clock reference must be sourced externally to both MAC and external Ethernet PHY It provides independent 2 bit...

Page 949: ...r before enabling the clocks MII RMII internal clock scheme The clock scheme required to support both the MII and RMII as well as 10 and 100 Mbit s operations is described in Figure 333 Figure 333 Clock scheme 1 The MII RMII selection is controlled through bit 23 MII_RMII_SEL in the AFIO_MAPR register STM32 REF_CLK 50 MHz 50 MHz MCO 25 MHz PLL For 10 100 Mbit s External PHY ai15625 802 3 MAC GPIO ...

Page 950: ... associated with a data link control procedure Data encapsulation transmit and receive Framing frame boundary delimitation frame synchronization Addressing handling of source and destination addresses Error detection Media access management Medium allocation collision avoidance Contention resolution collision handling Basically there are two operating modes of the MAC sublayer Half duplex mode the...

Page 951: ...cast addresses this bit is also 1 Each byte of each address field must be transmitted least significant bit first The address designation is based on the following types Individual address this is the physical address associated with a particular station on the network Group address A multidestination address associated with one or more stations on a given network There are two kinds of multicast ...

Page 952: ...or may not be passed by the MAC sublayer Data and PAD fields n byte data field Full data transparency is provided it means that any arbitrary sequence of byte values may appear in the data field The size of the PAD if any is determined by the size of the data field Max and min length of the data and PAD field are Maximum length 1500 bytes Minimum length for untagged MAC frames 46 bytes Minimum len...

Page 953: ...tra bits The CRC value computed on the incoming frame does not match the included FCS Preamble SFD Destination address Source address MAC client length type MAC client data PAD Frame check sequence 7 bytes 1 byte 6 bytes 6 bytes 2 bytes 46 1500 bytes 4 bytes MSB LSB Bit transmission order right to left Bytes within frame transmitted top to bottom ai15629 Preamble SFD Destination address Source add...

Page 954: ...d and the new frame is considered as the continuation of the previous frame There are two modes of operation for popping data towards the MAC core In Threshold mode as soon as the number of bytes in the FIFO crosses the configured threshold level or when the end of frame is written before the threshold is crossed the data is ready to be popped out and forwarded to the MAC core The threshold level ...

Page 955: ...s the deferral mechanism for flow control back pressure in Half duplex mode When the application requests to stop receiving frames the MAC sends a JAM pattern of 32 bytes whenever it senses the reception of a frame provided that transmit flow control is enabled This results in a collision and the remote station backs off The application requests flow control by setting the BPA bit bit 0 in the ETH...

Page 956: ...me in the generated frame is the programmed pause time value in ETH_MACFCR If the receive FIFO remains full at a configurable number of slot times PLT bits in ETH_MACFCR before this Pause time runs out a second Pause frame is transmitted The process is repeated as long as the receive FIFO remains full If this condition is no more satisfied prior to the sampling time the MAC transmits a Pause frame...

Page 957: ...nsmit status words are transferred to the application for the number of frames that is flushed including partial frames Frames that are completely flushed have the Frame flush status bit TDES0 13 set The Flush operation is completed when the application DMA has accepted all of the Status words for the frames that were flushed The Transmit FIFO Flush control register bit is then cleared At this poi...

Page 958: ...calculation is indicated by the IP Header Error status bit in the Transmit status Bit 16 This status bit is set whenever the values of the Ethernet Type field and the IP header s Version field are not consistent or when the Ethernet frame does not have enough data as indicated by the IP header Length field In other words this bit is set when an IP header error is asserted under the following circu...

Page 959: ...nserted into the packet The result of this operation is indicated by the payload checksum error status bit in the Transmit Status vector bit 12 The payload checksum error status bit is set when either of the following is detected the frame has been forwarded to the MAC transmitter in Store and forward mode without the end of frame being written to the FIFO the packet ends before the number of byte...

Page 960: ...iming diagrams Figure 338 Transmission with no collision Figure 339 Transmission with collision Figure 340 shows a frame transmission in MII and RMII MII_TX_CLK MII_TX_EN MII_TXD 3 0 PR EA MB LE MII_CS MII_COL ai15631 Low MII_TX_CLK MII_TX_EN MII_TXD 3 0 PR EAM BLE SFD MII_CS MII_COL ai15651 DA DA JAM JAM JAM JAM ...

Page 961: ... after being written completely into the Receive FIFO In this mode all error frames are dropped if the core is configured to do so such that only valid frames are read out and forwarded to the application In Cut through mode some error frames are not dropped because the error status is received at the end of the frame by which time the start of that frame has already been read out of the FIFO A re...

Page 962: ...ctively in the received Ethernet frame Type field This identification applies to VLAN tagged frames as well The receive checksum offload calculates IPv4 header checksums and checks that they match the received IPv4 header checksums The IP Header Error bit is set for any mismatch between the indicated payload type Ethernet Type field and the IP header version or when the received frame does not hav...

Page 963: ...ulticast address of the control frame 0x0180 C200 0001 If a match is detected the destination address of the received frame matches the reserved control frame destination address the MAC then decides whether or not to transfer the received control frame to the application based on the level of the PCF bit in ETH_MACFFR The MAC also decodes the type opcode and Pause Timer fields of the receiving co...

Page 964: ...using the FEF and FUGF bits in ETH_DMAOMR If the Receive FIFO is configured to operate in Store and forward mode all error frames can be filtered and dropped In Cut through mode if a frame s status and length are available when that frame s SOF is read from the Rx FIFO then the complete erroneous frame can be dropped The DMA can flush the error frame being read from the FIFO by enabling the receiv...

Page 965: ... order Figure 342 Reception with no error Figure 343 Reception with errors D0 D1 D2 D3 LSB MII_RXD 3 0 MSB D0 D1 LSB MSB RMII_RXD 1 0 Di bit stream Nibble stream ai15633 MII_RX_CLK MII_RX_DV MII_RXD 3 0 PREAMBLE SFD MII_RX_ERR ai15634 FCS MII_RX_CLK MII_RX_DV MII_RXD 3 0 PREAMBLE SFD MII_RX_ERR ai15635 DA DA XX XX XX ...

Page 966: ...le bit 3 of the Interrupt register set high indicates that the Magic packet or Wake on LAN frame is received in Power down mode You must read the ETH_MACPMTCSR Register to clear this interrupt event Figure 345 MAC core interrupt masking scheme 29 5 5 MAC filtering Address filtering Address filtering checks the destination and source addresses on all received frames and the address filtering status...

Page 967: ...rame reception Multicast destination address filter The MAC can be programmed to pass all multicast frames by setting the PAM bit in the Frame filter register If the PAM bit is reset the MAC performs the filtering for multicast addresses based on the HM bit in the Frame filter register In Perfect filtering mode the multicast address is compared with the programmed MAC destination address registers...

Page 968: ... needs to be forwarded This means that either of the filter fail result will drop the frame Both filters have to pass the frame for the frame to be forwarded to the application Inverse filtering operation For both destination and source address filtering there is an option to invert the filter match result at the final output These are controlled by the DAIF and SAIF bits in the Frame filter regis...

Page 969: ... X Pass all frames 0 X X 0 0 0 X Pass on Perfect Group filter match and drop PAUSE control frames if PCF 0x 0 0 X 0 1 0 X Pass on hash filter match and drop PAUSE control frames if PCF 0x 0 1 X 0 1 0 X Pass on hash or perfect Group filter match and drop PAUSE control frames if PCF 0x 0 X X 1 0 0 X Fail on perfect Group filter match and drop PAUSE control frames if PCF 0x 0 0 X 1 1 0 X Fail on hash...

Page 970: ...an maximum size MII_RXER Input error The maximum frame size depends on the frame type as follows Untagged frame maxsize 1518 VLAN Frame maxsize 1522 29 5 8 Power management PMT This section describes the power management PMT mechanisms supported by the MAC PMT supports the reception of network remote wakeup frames and Magic Packet frames PMT generates interrupts for wakeup frames and Magic Packets...

Page 971: ...ffset value 0 refers to the first byte of the frame Filter i CRC 16 This register contains the CRC_16 value calculated from the pattern as well as the byte mask programmed to the wakeup filter register block Remote wakeup frame detection When the MAC is in sleep mode and the remote wakeup bit is enabled in the ETH_MACPMTCSR register normal operation is resumed after receiving a remote wakeup frame...

Page 972: ...titions of the MAC address without any breaks or interruptions In case of a break in the 16 repetitions of the address the 0xFFFF FFFF FFFF pattern is scanned for again in the incoming frame The 16 repetitions can be anywhere in the frame but must be preceded by the synchronization stream 0xFFFF FFFF FFFF The device also accepts a multicast frame as long as the 16 duplications of the MAC address a...

Page 973: ...ode 11 On receiving a valid wakeup frame the Ethernet peripheral exits the power down mode 12 Read the ETH_MACPMTCSR to clear the power management event flag enable the MAC transmitter state machine and the receive and transmit DMA 13 Configure the system clock enable the HSE and set the clocks 29 5 9 Precision time protocol IEEE1588 PTP The IEEE 1588 standard defines a protocol that allows precis...

Page 974: ...4 to synchronize its local timing reference to the master s timing reference Most of the protocol implementation occurs in the software above the UDP layer As described above however hardware support is required to capture the exact time when specific PTP packets enter or leave the Ethernet port at the MII This timing information has to be captured and returned to the software for a proper high ac...

Page 975: ...the IEEE 1588 time stamping feature is enabled the Ethernet MAC captures the time stamp of all frames received on the MII The MAC provides the time stamp as soon as the frame reception is complete Captured time stamps are returned to the application in the same way as the frame status is provided The time stamp is sent back along with the Receive status of the frame inside the corresponding receiv...

Page 976: ... to 67 MHz for example the addend register must be set to 0xBF0 B7672 When the clock drift is zero the default addend value of 0xC1F0 7C1F 232 1 32 should be programmed In Figure 348 the constant value used to increment the subsecond register is 0d43 This makes an accuracy of 20 ns in the system time in other words it is incremented by 20 ns steps The software has to calculate the drift in frequen...

Page 977: ...ithm is self correcting if for any reason the slave clock is initially set to a value from the master that is incorrect the algorithm corrects it at the cost of more Sync cycles Programming steps for system time generation initialization The time stamping feature can be enabled by setting bit 0 in the Time stamp control register ETH__PTPTSCR However it is essential to initialize the time stamp cou...

Page 978: ...the required target time in the Target time high and low registers Unmask the Time stamp interrupt by clearing bit 9 in the ETH_MACIMR register 5 Set Time stamp control register bit 4 TSARU 6 When this trigger causes an interrupt read the ETH_MACSR register 7 Reprogram the Time stamp addend register with the old value and set ETH_TPTSCR bit 5 again PTP trigger internal connection with TIM2 The MAC...

Page 979: ...status registers are described in detail in Section 29 8 on page 1002 Descriptors are described in detail in Section on page 987 The DMA transfers the received data frames to the receive buffer in the STM32F107xx memory and transmits data frames from the transmit buffer in the STM32F107xx memory Descriptors that reside in the STM32F107xx memory act as pointers to these buffers There are two descri...

Page 980: ...ive and transmit engines then begin processing receive and transmit operations The transmit and receive processes are independent of each other and can be started or stopped separately 29 6 2 Host bus burst access The DMA attempts to execute fixed length burst transfers on the AHB master interface if configured to do so FB bit in ETH_DMABMR The maximum burst length is indicated and limited by the ...

Page 981: ...ta for the byte lanes not required This typically happens during the transfer of the beginning or end of an Ethernet frame Example of buffer read If the Transmit buffer address is 0x0000 0FF2 and 15 bytes need to be transferred then the DMA will read five full words from address 0x0000 0FF0 but when transferring data to the Transmit FIFO the extra bytes the first two bytes will be dropped or ignor...

Page 982: ...cesses to the AHB master interface Two types of arbitrations are possible round robin and fixed priority When round robin arbitration is selected DA bit in ETH_DMABMR is reset the arbiter allocates the databus in the ratio set by the RTPR bits in ETH_DMABMR when both transmit and receive DMAs request access simultaneously When the DA bit is set the receive DMA always gets priority over the transmi...

Page 983: ...ion is complete if IEEE 1588 time stamping was enabled for the frame as indicated in the transmit status the time stamp value is written to the transmit descriptor TDES2 and TDES3 that contains the end of frame buffer The status information is then written to this transmit descriptor TDES0 Because the OWN bit is cleared during this step the CPU now owns this descriptor If time stamping was not ena...

Page 984: ...the transmit descriptor list for the second frame If the second frame is valid the transmit process transfers this frame before writing the first frame s status information In OSF mode the Run state transmit DMA operates according to the following sequence Start TxDMA Re fetch next descriptor Write status word to TDES0 Wait for Tx status Transfer data from buffer s AHB error Own bit set AHB error ...

Page 985: ...p to TDES2 and TDES3 if such time stamp was captured as indicated by a status bit The DMA then writes the status with a cleared OWN bit to the corresponding TDES0 thus closing the descriptor If time stamping was not enabled for the previous frame the DMA does not alter the contents of TDES2 and TDES3 6 If enabled the Transmit interrupt is set the DMA fetches the next descriptor then proceeds to St...

Page 986: ... are transferred from the memory buffer to the Transmit FIFO Concurrently if the last descriptor TDES0 29 of the current frame is cleared the transmit process attempts to acquire the next descriptor The transmit process expects TDES0 28 to be cleared in this descriptor If TDES0 29 is cleared it indicates an intermediary buffer If TDES0 29 is set it Previous frame status available Start TxDMA Re fe...

Page 987: ...nd then issue a Poll Demand command A frame transmission is aborted when a transmit error due to underflow is detected The appropriate Transmit Descriptor 0 TDES0 bit is set If the second condition occurs both the Abnormal Interrupt Summary in ETH_DMASR register 15 and Transmit Underflow bits in ETH_DMASR register 5 are set and the information is written to Transmit Descriptor 0 causing the suspen...

Page 988: ...en set this bit indicates that the buffer contains the first segment of a frame Bit 27 DC Disable CRC When this bit is set the MAC does not append a cyclic redundancy check CRC to the end of the transmitted frame This is valid only when the first segment TDES0 28 is set Bit 26 DP Disable pad When set the MAC does not automatically add padding to a frame shorter than 64 bytes When this bit is reset...

Page 989: ...th the packet For IPv4 frames an error status is also indicated if the Header Length field has a value less than 0x5 Bit 15 ES Error summary Indicates the logical OR of the following bits TDES0 14 Jabber timeout TDES0 13 Frame flush TDES0 11 Loss of carrier TDES0 10 No carrier TDES0 9 Late collision TDES0 8 Excessive collision TDES0 2 Excessive deferral TDES0 1 Underflow error TDES0 16 IP header e...

Page 990: ...it 2 ED Excessive deferral When set this bit indicates that the transmission has ended because of excessive deferral of over 24 288 bit times if the Deferral check DC bit in the MAC Control register is set high Bit 1 UF Underflow error When set this bit indicates that the MAC aborted the frame because data arrived late from the RAM memory Underflow error indicates that the DMA encountered an empty...

Page 991: ...nt bits of the time stamp captured for the corresponding transmit frame overwriting the value for TBAP1 This field has the time stamp only if time stamping is activated for this frame see TTSE TDES0 bit 25 and if the Last segment control bit LS in the descriptor is set 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TBAP2 TBAP2 TTSH rw Bits 31 0 TBAP2 Transmit...

Page 992: ...he current descriptor as intermediate and returns to step 4 7 If IEEE 1588 time stamping is enabled the DMA writes the time stamp if available to the current descriptor s RDES2 and RDES3 It then takes the received frame s status and writes the status word to the current descriptor s RDES0 with the OWN bit cleared and the Last segment bit set 8 The Receive engine checks the latest descriptor s OWN ...

Page 993: ...for frame data Write data to buffer s Yes Yes Fetch next descriptor Yes No Frame transfer complete No Set descriptor error Yes Time stamp present No Close RDES0 as last descriptor Write time stamp to RDES2 RDES3 No AHB error Yes Close RDES0 as intermediate descriptor Frame transfer complete No Flush disabled No Flush the remaining frame Yes Yes No No No Yes Yes Poll demand new frame available No Y...

Page 994: ...MA sets the first descriptor RDES0 9 after the DMA AHB Interface becomes ready to receive a data transfer if DMA is not fetching transmit data from the memory to delimit the frame The descriptors are released when the OWN RDES0 31 bit is reset to 0 either as the data buffer fills up or as the last segment of the frame is transferred to the receive buffer If the frame is contained in a single descr...

Page 995: ... FL ES DE SAF LE OE VLAN FS LS IPHCE LCO FT RWT RE DE CE PCE rw Bit 31 OWN Own bit When set this bit indicates that the descriptor is owned by the DMA of the MAC Subsystem When this bit is reset it indicates that the descriptor is owned by the Host The DMA clears this bit either when it completes the frame reception or when the buffers that are associated with this descriptor are full Bit 30 AFM D...

Page 996: ...cates that the frame pointed to by this descriptor is a VLAN frame tagged by the MAC core Bit 9 FS First descriptor When set this bit indicates that this descriptor contains the first buffer of the frame If the size of the first buffer is 0 the second buffer contains the beginning of the frame If the size of the second buffer is also 0 the next descriptor contains the beginning of the frame Bit 8 ...

Page 997: ...ulated TCP UDP or ICMP segment s Checksum field This bit is also set when the received number of payload bytes does not match the value indicated in the Length field of the encapsulated IPv4 or IPv6 datagram in the received Ethernet frame Table 213 Receive descriptor 0 Bit 5 frame type Bit 7 IPC checksum error Bit 0 payload checksum error Frame status 0 0 0 IEEE 802 3 Type frame Length field value...

Page 998: ...aligned to bus width If the buffer size is not an appropriate multiple of 4 8 or 16 the resulting behavior is undefined This field is not valid if RDES1 14 is set Bit 15 RER Receive end of ring When set this bit indicates that the descriptor list reached its final descriptor The DMA returns to the base address of the list creating a descriptor ring Bit 14 RCH Second address chained When set this b...

Page 999: ...he moment that the OWN bit is set to 1 in RDES0 these bits indicate the physical address of Buffer 1 There are no limitations on the buffer address alignment except for the following condition the DMA uses the configured value for its address generation when the RDES2 value is used to store the start of frame Note that the DMA performs a write operation with the RDES2 3 2 1 0 bits as 0 during the ...

Page 1000: ...MASR register Next receive buffer unavailable ETH_DMASR register 7 occurs The driver clears the Receive 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RBP2 RTSH rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 0 RBAP2 RTSH Receive buffer 2 address pointer next descriptor address Receive frame time stamp h...

Page 1001: ...wer mode and generates an interrupt When an Ethernet wakeup event mapped on EXTI Line19 occurs and the MAC PMT interrupt is enabled and the EXTI Line19 interrupt with detection on rising edge is also enabled both interrupts are generated A watchdog timer see ETH_DMARSWTR register is given for flexible control of the RS bit ETH_DMASR register When this watchdog timer is programmed with a non zero v...

Page 1002: ...nd to be at 0 29 8 Ethernet register descriptions The peripheral registers can be accessed by bytes 8 bit half words 16 bot or words 32 bits 29 8 1 MAC register description Ethernet MAC configuration register ETH_MACCR Address offset 0x0000 Reset value 0x0000 8000 The MAC configuration register is the operation mode register of the MAC It establishes receive and transmit operating modes 31 30 29 2...

Page 1003: ...t the MAC receives all packets that are given by the PHY while transmitting This bit is not applicable if the MAC is operating in Full duplex mode Bit 12 LM Loopback mode When this bit is set the MAC operates in loopback mode at the MII The MII receive clock input RX_CLK is required for the loopback to work properly as the transmit clock is not looped back internally Bit 11 DM Duplex mode When thi...

Page 1004: ... the excessive deferral error bit set in the transmit frame status when the transmit state machine is deferred for more than 24 288 bit times in 10 100 Mbit s mode Deferral begins when the transmitter is ready to transmit but is prevented because of an active CRS carrier sense signal on the MII Defer time is not cumulative If the transmitter defers for 10 000 bit times then transmits collides back...

Page 1005: ... if the HU or HM bit is set only frames that match the Hash filter are passed Bit 9 SAF Source address filter The MAC core compares the SA field of the received frames with the values programmed in the enabled SA registers If the comparison matches then the SAMatch bit in the RxStatus word is set high When this bit is set high and the SA filter fails the MAC drops the frame When this bit is reset ...

Page 1006: ...e it is rejected If the PAM pass all multicast bit is set in the ETH_MACFFR register then all multicast frames are accepted regardless of the multicast hash values Bit 4 PAM Pass all multicast When set this bit indicates that all received frames with a multicast destination address first bit in the destination address field is 1 are passed When reset filtering of multicast frame depends on the HM ...

Page 1007: ...TH rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 0 HTH Hash table high This field contains the upper 32 bits of Hash table 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HTL rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 0 HTL Hash table low This...

Page 1008: ... MDC clock Selection HCLK MDC Clock 000 60 72 MHz HCLK 42 001 Reserved 010 20 35 MHz HCLK 16 011 35 60 MHz HCLK 26 100 101 110 111 Reserved Bit 1 MW MII write When set this bit tells the PHY that this will be a Write operation using the MII Data register If this bit is not set this will be a Read operation placing the data in the MII Data register Bit 0 MB MII busy This bit should read a logic 0 b...

Page 1009: ...Pause Time configured in bits 31 16 For example if PT 100H 256 slot times and PLT 01 then a second PAUSE frame is automatically transmitted if initiated at 228 256 28 slot times after the first PAUSE frame is transmitted Selection Threshold 00 Pause time minus 4 slot times 01 Pause time minus 28 slot times 10 Pause time minus 144 slot times 11 Pause time minus 256 slot times Slot time is defined a...

Page 1010: ... TFCE is set back pressure is asserted by the MAC core During back pressure when the MAC receives a new frame the transmitter starts sending a JAM pattern resulting in a collision When the MAC is configured to Full duplex mode the BPA is automatically disabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved VLANTC VLANTI rw rw rw rw rw rw rw rw rw rw ...

Page 1011: ...address with the offset 0x0028 will read all wakeup frame filter registers This register contains the higher 16 bits of the 7th MAC address Refer to Remote wakeup frame filter register section for additional information Figure 358 Ethernet MAC remote wakeup frame filter register ETH_MACRWUFFR Filter 0 Byte Mask Filter 1 Byte Mask Filter 2 Byte Mask Filter 3 Byte Mask RSVD Filter 3 Command RSVD Fil...

Page 1012: ...6 WFR Wakeup frame received When set this bit indicates the power management event was generated due to reception of a wakeup frame This bit is cleared by a read into this register Bit 5 MPR Magic packet received When set this bit indicates the power management event was generated by the reception of a Magic Packet This bit is cleared by a read into this register Bits 4 3 Reserved Bit 2 WFE Wakeup...

Page 1013: ...This bit is set high whenever an interrupt is generated in the ETH_MMCTIR Register This bit is cleared when all the bits in this interrupt register ETH_MMCTIR are cleared Bit 5 MMCRS MMC receive status This bit is set high whenever an interrupt is generated in the ETH_MMCRIR register This bit is cleared when all the bits in this interrupt register ETH_MMCRIR are cleared Bit 4 MMCS MMC status This ...

Page 1014: ...s the destination address then the MAC address 0 register 47 0 is compared with 0x6655 4433 2211 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TSTIM Reserved PMTIM Reserved rw rw Bits 15 10 Reserved Bit 9 TSTIM Time stamp trigger interrupt mask When set this bit disables the time stamp interrupt generation Bits 8 4 Reserved Bit 3 PMTIM PMT interrupt mask When set this bit disables the assertion o...

Page 1015: ... the transmit flow control Pause frames 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AE SA MBC Reserved MACA1H rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 31 AE Address enable When this bit is set the address filters use the MAC address1 for perfect filtering When this bit is cleared the address filters ignore the address for...

Page 1016: ... The content of this field is undefined until loaded by the application after the initialization process 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AE SA MBC Reserved MACA2H rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 31 AE Address enable When this bit is set the address filters use the MAC address2 for perfect filtering Wh...

Page 1017: ... rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 0 MACA2L MAC address2 low 31 0 This field contains the lower 32 bits of the 6 byte second MAC address2 The content of this field is undefined until loaded by the application after the initialization process 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AE SA MB...

Page 1018: ...tents of the MAC address 3 registers Each bit controls the masking of the bytes as follows Bit 29 ETH_MACA3HR 15 8 Bit 28 ETH_MACA3HR 7 0 Bit 27 ETH_MACA3LR 31 24 Bit 24 ETH_MACA3LR 7 0 Bits 23 16 Reserved Bits 15 0 MACA3H MAC address3 high 47 32 This field contains the upper 16 bits 47 32 of the 6 byte MAC address3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ...

Page 1019: ...d MCF ROR CSR CR rw rw rw rw Bits 31 4 Reserved Bit 3 MCF MMC counter freeze When set this bit freezes all the MMC counters to their current value None of the MMC counters are updated due to any transmitted or received frame until this bit is cleared to 0 If any MMC counter is read with the Reset on Read bit set then that counter is also cleared in this mode Bit 2 ROR Reset on read When this bit i...

Page 1020: ...h alignment error counter reaches half the maximum value Bit 5 RFCES Received frames CRC error status This bit is set when the received frames with CRC error counter reaches half the maximum value Bits 4 0 Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TGFS Reserved TGFMSCS TGFSCS Reserved rc_r rc_r rc_r Bits 31 22 Reserved Bit 21 TGFS Trans...

Page 1021: ...8 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RGUFM Reserved RFAEM RFCEM Reserved rw rw rw Bits 31 18 Reserved Bit 17 RGUFM Received good unicast frames mask Setting this bit masks the interrupt when the received good unicast frames counter reaches half the maximum value Bits 16 7 Reserved Bit 6 RFAEM Received frames alignment error mask Setting this bit masks the interrupt when the recei...

Page 1022: ...s the interrupt when the transmitted good frames after more than a single collision counter reaches half the maximum value Bit 14 TGFSCM Transmitted good frames single collision mask Setting this bit masks the interrupt when the transmitted good frames after a single collision counter reaches half the maximum value Bits 13 0 Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 1...

Page 1023: ... This register contains the number of frames received with alignment dribble error 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TGFC r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r Bits 31 0 TGFC Transmitted good frames counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFCEC r r r r r r r r r r r r...

Page 1024: ...w rw rw rw Bits 31 5 Reserved Bit 5 TSARU Time stamp addend register update When this bit is set the Time stamp addend register s contents are updated to the PTP block for fine correction This bit is cleared when the update is completed This register bit must be read as zero before you can set it Bit 4 TSITE Time stamp interrupt trigger enable When this bit is set a time stamp interrupt is generat...

Page 1025: ... to be updated using the Fine Update method When cleared it indicates the system time stamp is to be updated using the Coarse method Bit 0 TSE Time stamp enable When this bit is set time stamping is enabled for transmit and receive frames When this bit is cleared the time stamp function is suspended and time stamps are not added for transmit and receive frames Because the maintained system time is...

Page 1026: ...STI or TSSTU bits in the Time stamp control register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STPNS STSS r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r Bit 31 STPNS System time positive or negative sign This bit indicates a positive or negative time value When set the bit indicates that time representation is negative When cleared it in...

Page 1027: ...w rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 31 TSUPNS Time stamp update positive or negative sign This bit indicates positive or negative time value When set the bit indicates that time representation is negative When cleared it indicates that time representation is positive When TSSTI is set system time initialization this bit should be zero If this b...

Page 1028: ...register description This section defines the bits for each DMA register Non 32 bit accesses are allowed as long as the address is word aligned 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TTSH rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31 0 TTSH Target time stamp high This register stores the time i...

Page 1029: ...Bit 23 USP Use separate PBL When set high it configures the RxDMA to use the value configured in bits 22 17 as PBL while the PBL value in bits 13 8 is applicable to TxDMA operations only When this bit is cleared the PBL value in bits 13 8 is applicable for both DMA engines Bits 22 17 RDP Rx DMA PBL These bits indicate the maximum number of beats to be transferred in one RxDMA transaction This is t...

Page 1030: ... maximum number of beats PBL possible is limited by the size of the Tx FIFO and Rx FIFO The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO If the PBL is common for both transmit and receive DMA the minimum Rx FIFO and Tx FIFO depths must be considered Do not program out of range PBL values because the system may not behave properly Bit 7 Reserved Bits 6 2 DSL D...

Page 1031: ...ptor list address register ETH_DMATDLAR Address offset 0x1010 Reset value 0x0000 0000 The Transmit descriptor list address register points to the start of the transmit descriptor list The descriptor lists reside in the STM32F107xx s physical memory space and must be word aligned The DMA internally converts it to bus width aligned address by taking the corresponding LSB to low Writing to the ETH_DM...

Page 1032: ...he LSB bits 1 2 3 0 for 32 64 128 bit bus width are internally ignored and taken as all zero by the DMA Hence these LSB bits are read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TSTS PMTS MMCS Reserved EBS TPS RPS NIS AIS ERS FBES Reserved ETS RWTS RPSS RBUS RS TUS ROS TJTS TBUS TPSS TS r r r r r r r r r r r r rc w1 rc w1 rc w1 rc w1 rc w1 rc...

Page 1033: ...ture use 110 Suspended Transmit descriptor unavailable or transmit buffer underflow 111 Running Closing transmit descriptor Bits 19 17 RPS Receive process state These bits indicate the Receive DMA FSM state This field does not generate an interrupt 000 Stopped Reset or Stop Receive Command issued 001 Running Fetching receive transfer descriptor 010 Reserved for future use 011 Running Waiting for r...

Page 1034: ...me to be transmitted was fully transferred to the Transmit FIFO Bit 9 RWTS Receive watchdog timeout status This bit is asserted when a frame with a length greater than 2 048 bytes is received Bit 8 RPSS Receive process stopped status This bit is asserted when the receive process enters the Stopped state Bit 7 RBUS Receive buffer unavailable status This bit indicates that the next descriptor in the...

Page 1035: ...ission is stopped Bit 0 TS Transmit status This bit indicates that frame transmission is finished and TDES1 31 is set in the first descriptor 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DTCEFD RSF DFRF Reserved TSF FTF Reserved TTC ST Reserved FEF FUGF Reserved RTC OSF SR Reserved rw rw rw rw rs rw rw rw rw rw rw rw rw rw rw Bits 31 27 Reserved Bi...

Page 1036: ... transmit list at the current position for a frame to be transmitted Descriptor acquisition is attempted either from the current position in the list which is the transmit list base address set by the ETH_DMATDLAR register or from the position retained when transmission was stopped previously If the current descriptor is not owned by the DMA transmission enters the Suspended state and the transmit...

Page 1037: ...rame When this bit is set this bit instructs the DMA to process a second frame of Transmit data even before status for first frame is obtained Bit 1 SR Start stop receive When this bit is set the receive process is placed in the Running state The DMA attempts to acquire the descriptor from the receive list and processes incoming frames Descriptor acquisition is attempted from the current position ...

Page 1038: ...n this bit is set an abnormal interrupt is enabled When this bit is cleared an abnormal interrupt is disabled This bit enables the following bits ETH_DMASR 1 Transmit process stopped ETH_DMASR 3 Transmit jabber timeout ETH_DMASR 4 Receive overflow ETH_DMASR 5 Transmit underflow ETH_DMASR 7 Receive buffer unavailable ETH_DMASR 8 Receive process stopped ETH_DMASR 9 Receive watchdog timeout ETH_DMASR...

Page 1039: ... cleared the receive interrupt is disabled Bit 5 TUIE Underflow interrupt enable When this bit is set with the abnormal interrupt summary enable bit ETH_DMAIER register 15 the transmit underflow interrupt is enabled When this bit is cleared the underflow interrupt is disabled Bit 4 ROIE Overflow interrupt enable When this bit is set with the abnormal interrupt summary enable bit ETH_DMAIER registe...

Page 1040: ...transmit descriptor read by the DMA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OFOC MFA OMFC MFC rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r Bits 31 29 Reserved Bit 28 OFOC Overflow bit for FIFO overflow counter Bits 2...

Page 1041: ...st receive buffer address register points to the current receive buffer address being read by the DMA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HRDAP r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r Bits 31 0 HRDAP Host receive descriptor address pointer Cleared on Reset Pointer updated by DMA during operation 31 30 29 28 27 26 25 24 23 22...

Page 1042: ... TFCE FCB BPA Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x1C ETH_MACVL ANTR Reserved VLANTC VLANTI Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x28 ETH_MACRW UFFR Frame filter reg0 Frame filter reg1 Frame filter reg2 Frame filter reg3 Frame filter reg4 Frame filter reg7 Reset value 0 0x2C ETH_MACPM TCSR WFFRPR Reserved GU Reserved WFR MPR Reserved WFE MPE PD Reset value 0 0 0 0 0...

Page 1043: ...R TGFC Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x194 ETH_MMCRF CECR RFCEC Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x198 ETH_MMCRF AECR RFAEC Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x1C4 ETH_MMCR GUFCR RGUFC Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x700 ET...

Page 1044: ...MASR Reserved TSTS PMTS MMCS Reserved EBS TPS RPS NIS AIS ERS FBES Reserved ETS RWTS RPSS RBUS RS TUS ROS TJTS TBUS TPSS TS Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x1018 ETH_DMAOM R Reserved DTCEFD RSF DFRF Reserved TSF FTF Reserved TTC ST Reserved FEF FUGF Reserved RTC OSF SR Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x101C ETH_DMAIE R Reserved NISE AISE ERIE F...

Page 1045: ...bytes and 1 Mbyte Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers This Section applies to the whole STM32F10xxx family unless otherwise specified The electronic signature is stored in the System memory area in the Flash memory module and can be read using the JTAG SWD or the CPU It contains factory programmed identification data that allow the user firmware or other exte...

Page 1046: ...device identifier can also be read in single bytes half words words in different ways and then be concatenated using a custom algorithm Base address 0x1FFF F7E8 Address offset 0x00 Read only 0xXXXX where X is factory programmed Address offset 0x02 Read only 0xXXXX where X is factory programmed Address offset 0x04 Read only 0xXXXX XXXX where X is factory programmed 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 1047: ...ffset 0x08 Read only 0xXXXX XXXX where X is factory programmed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 U_ID 95 80 r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 U_ID 79 64 r r r r r r r r r r r r r r r r Bits 31 0 U_ID 95 64 95 64 Unique ID bits ...

Page 1048: ... ranges between 768 Kbytes and 1 Mbyte Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers This section applies to the whole STM32F10xxx family unless otherwise specified 31 1 Overview The STM32F10xxx are built around a Cortex M3 core which contains hardware extensions for advanced debugging features The debug extensions allow the core to be stopped either on a given instruc...

Page 1049: ...ailable on larger packages where the corresponding pins are mapped It also includes debug features dedicated to the STM32F10xxx Flexible debug pinout assignment MCU debug box support for low power modes control over peripheral clocks etc Note For further information on debug functionality supported by the ARM Cortex M3 core refer to the Cortex M3 r1p1 Technical Reference Manual and to the CoreSigh...

Page 1050: ...vides a 5 pin standard JTAG interface to the AHP AP port The Serial Wire Debug Port SW DP provides a 2 pin clock data interface to the AHP AP port In the SWJ DP the two JTAG pins of the SW DP are multiplexed with some of the five JTAG pins of the JTAG DP Figure 360 SWJ debug port Figure 360 shows that the asynchronous TRACE output TRACESWO is multiplexed with TDO This means that the asynchronous t...

Page 1051: ...e to activate the SWDP using only the SWCLK and SWDIO pins This sequence is 1 Send more than 50 TCK cycles with TMS SWDIO 1 2 Send the 16 bit sequence on TMS SWDIO 0111100111100111 MSB transmitted first 3 Send more than 50 TCK cycles with TMS SWDIO 1 31 4 Pinout and debug port pins The STM32F10xxx MCUs are available in various packages with different numbers of available pins As a result some func...

Page 1052: ...ger host Three control bits allow the configuration of the SWJ DP pin assignments These bits are reset by the System Reset AFIO_MAPR 0x40010004 in the STM32F10xxx MCU READ APB No Wait State WRITE APB 1 Wait State if the write buffer of the AHB APB bridge is full Bit 26 24 SWJ_CFG 2 0 Set and cleared by software These bits are used to configure the number of pins assigned to the SWJ debug port The ...

Page 1053: ... IO levels the device embeds internal pull ups and pull downs on the JTAG input pins NJTRST Internal pull up JTDI Internal pull up JTMS SWDIO Internal pull up TCK SWCLK Internal pull down Once a JTAG IO is released by the user software the GPIO controller takes control again The reset states of the GPIO control registers put the IOs in the equivalent state NJTRST Input pull up JTDI Input pull up J...

Page 1054: ...er that they will be first configured either in input pull up nTRST TMS TDI or pull down TCK or output tristate TDO for a certain duration after reset until the instant when the user software releases the pins When debug pins JTAG or SW or TRACE are mapped changing the corresponding IO pin configuration in the IOPORT controller has no effect 31 5 STM32F10xxx JTAG TAP connection The STM32F10xxx MCU...

Page 1055: ...s part of the DBG_MCU component and is mapped on the external PPB bus see Section 31 16 on page 1068 This code is accessible using the JTAG debug port 4 to 5 pins or the SW debug port two pins or by the user software It is even accessible while the MCU is under system reset DBGMCU_IDCODE Address 0xE0042000 Only 32 bits access supported Read only Boundary scan TAP NJTRST Cortex M3 TAP JTMS TMS nTRS...

Page 1056: ...evision identifier This field indicates the revision of the device In low density devices 0x1000 Revision A In medium density devices 0x0000 Revision A 0x2000 Revision B 0x2001 Revision Z 0x2003 Revision Y In high density devices 0x1000 Revision A 0x1001 Revision Z 0x1003 Revision Y In XL density devices 0x1000 Revision A In connectivity line devices 0x1000 Revision A 0x1001 Revision Z Bits 15 12 ...

Page 1057: ...debug port A standard JTAG state machine is implemented with a 4 bit instruction register IR and five data registers for full details refer to the Cortex M3 r1p1 Technical Reference Manual TRM for references please see Section 31 2 Reference ARM documentation Table 217 JTAG debug port data registers IR 3 0 Data register Details 1111 BYPASS 1 bit 1110 IDCODE 32 bits ID CODE 0x3BA00477 ARM Cortex M3...

Page 1058: ...s 31 1 Reserved Bit 0 DAPABORT write 1 to generate a DAP abort Table 218 32 bit debug port registers addressed through the shifted value A 3 2 Address A 3 2 value Description 0x0 00 Reserved 0x4 01 DP CTRL STAT register Used to Request a system or debug power up Configure the transfer operation for AP accesses Control the pushed compare and pushed verify operations Read some status flags overrun p...

Page 1059: ... this can be adjusted by configuring the SWCLK frequency 31 8 2 SW protocol sequence Each sequence consist of three phases 1 Packet request 8 bits transmitted by the host 2 Acknowledge response 3 bits transmitted by the target 3 Data transfer phase 33 bits transmitted by the host or the target Refer to the Cortex M3 r1p1 TRM for a detailed description of DPACC and APACC registers The packet reques...

Page 1060: ...ID CODE register Otherwise the target will issue a FAULT acknowledge response on another transactions Further details of the SW DP state machine can be found in the Cortex M3 r1p1 TRM and the CoreSight Design Kit r1p0 TRM 31 8 4 DP and AP read write accesses Read accesses to the DP are not posted the target response can be immediate if ACK OK or can be delayed if ACK WAIT Read accesses to the AP a...

Page 1061: ...tes 00 Read IDCODE The manufacturer code is not set to ST code 0x1BA01477 identifies the SW DP 00 Write ABORT 01 Read Write 0 DP CTRL STAT Purpose is to request a system or debug power up configure the transfer operation for AP accesses control the pushed compare and pushed verify operations read some status flags overrun power up acknowledges 01 Read Write 1 WIRE CONTROL Purpose is to configure t...

Page 1062: ...o 64 words or 256 bytes and consists of c Bits 7 4 the bits 7 4 APBANKSEL of the DP SELECT register d Bits 3 2 the 2 address bits of A 3 2 of the 35 bit packet request for SW DP The AHB AP of the Cortex M3 includes 9 x 32 bits registers Refer to the Cortex M3 r1p1 TRM for further details Table 223 Cortex M3 AHB AP registers Address offset Register name Notes 0x00 AHB AP Control and Status Word Con...

Page 1063: ...tex M3 differentiates the reset of the debug part generally PORRESETn and the other one SYSRESETn This way it is possible for the debugger to connect under System Reset programming the Core Debug Registers to halt the core when fetching the reset vector Then the host can release the system reset and the core will immediately halt without having executed any instructions In addition it is possible ...

Page 1064: ...ral loads from Code Space and remapping to a corresponding area in the System Space 6 instruction comparators for matching against instruction fetches from Code Space They can be used either to remap to a corresponding area in the System Space or to generate a Breakpoint Instruction to the core 31 13 DWT data watchpoint trigger The DWT unit consists of four comparators They are configurable as a h...

Page 1065: ...it TRCEN of the Debug Exception and Monitor Control Register must be enabled before you program or use the ITM 31 14 2 Time stamp packets synchronization and overflow packets Time stamp packets encode time stamp information generic control and synchronization It uses a 21 bit timestamp counter with possible prescalers which is reset at each time stamp packet emission This counter can be either clo...

Page 1066: ...k access Write 0xC5ACCE55 to unlock Write Access to the other ITM registers E0000E80 ITM trace control Bits 31 24 Always 0 Bits 23 Busy Bits 22 16 7 bits ATB ID which identifies the source of the trace data Bits 15 10 Always 0 Bits 9 8 TSPrescale Time Stamp Prescaler Bits 7 5 Reserved Bit 4 SWOENA Enable SWV behavior to clock the timestamp counter by the SWV clock Bit 3 DWTENA Enable the DWT Stimu...

Page 1067: ...ace Unit The formatter of the TPIU adds some extra packets refer to Section 31 17 TPIU trace port interface unit and then outputs the complete packet sequence to the debugger host 31 15 2 Signal protocol packet types This part is described in the chapter 7 ETMv3 Signal Protocol of the ARM IHI 0014N document 31 15 3 Main ETM registers For more information on registers refer to the chapter 3 of the ...

Page 1068: ...des which can either deactivate the CPU clock or reduce the power of the CPU The core does not allow FCLK or HCLK to be turned off during a debug session As these are required for the debugger connection during a debug they must remain active The MCU integrates special means to allow the user to debug software in low power modes For this the debugger host must first set some debug configuration re...

Page 1069: ... TIMEOUT rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DBG_I2C1 _SMBUS_ TIMEOUT DBG_ CAN1_ STOP DBG_ TIM4_ STOP DBG_ TIM3_ STOP DBG_ TIM2_ STOP DBG_ TIM1_ STOP DBG_ WWDG_ STOP DBG_ IWDG STOP TRACE_ MODE 1 0 TRACE_ IOEN Reserved DBG_ STAND BY DBG_ STOP DBG_ SLEEP rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 31 Reserved must be kept cleared Bits 30 25 DBG_TIMx_STOP TIMx ...

Page 1070: ... for Asynchronous Mode TRACE_MODE 01 TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 TRACE_MODE 10 TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 TRACE_MODE 11 TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 Bits 4 3 Reserved must be kept cleared Bit 2 DBG_STANDBY Debug Standby mode 0 FCLK Off HCLK Off The whole digital part is unpowe...

Page 1071: ...hile HCLK is disabled In Sleep mode the clock controller configuration is not reset and remains in the previously programmed state Consequently when exiting from Sleep mode the software does not need to reconfigure the clock controller 1 FCLK On HCLK On In this case when entering Sleep mode HCLK is fed by the same clock that is provided to FCLK system clock as previously configured by the software...

Page 1072: ...xtra pin and is available on all packages It is only available if using Serial Wire mode not in JTAG mode Synchronous mode The synchronous mode requires from 2 to 6 extra pins depending on the data trace size and is only available in the larger packages In addition it is available in JTAG mode and in Serial Wire mode and provides better bandwidth output capabilities than asynchronous trace formatt...

Page 1073: ...1 2 or 4 TRACECK TRACED 0 if port size is configured to 1 2 or 4 TRACED 1 if port size is configured to 2 or 4 TRACED 2 if port size is configured to 4 TRACED 3 if port size is configured to 4 To assign the TRACE pin the debugger host must program the bits TRACE_IOEN and TRACE_MODE 1 0 of the Debug MCU configuration Register DBGMCU_CR By default the TRACE pins are not assigned This register is map...

Page 1074: ...a DATA byte 0 or an ID byte 1 7 bits MSB which can be data or change of source ID trace one byte of auxiliary bits where each bit corresponds to one of the eight mixed use bytes if the corresponding byte was a data this bit gives bit0 of the data if the corresponding byte was an ID change this bit indicates when that ID change takes effect Note Refer to the ARM CoreSight Architecture Specification...

Page 1075: ... the registers DWT Control Register bits SYNCTAP 11 10 and the DWT Current PC Sampler Cycle Count Register The TPUI Frame synchronization packet 0x7F_FF_FF_FF is emitted after each TPIU reset release This reset is synchronously released with the rising edge of the TRACECLKIN clock This means that this packet is transmitted when the TRACE_IOEN bit in the DBGMCU_CFG register is set In this case the ...

Page 1076: ...n the STM32F10xxx this TRACECLKIN input is internally connected to HCLK This means that when in asynchronous trace mode the application is restricted to use to time frames where the CPU frequency is stable Note Important when using asynchronous trace it is important to be aware that The default clock of the STM32F10xxx MCUs is the internal RC oscillator Its frequency under reset is different from ...

Page 1077: ... Trace Port Mode 01 Serial Wire Output manchester default value 10 Serial Wire Output NRZ 11 reserved 0xE0040304 Formatter and flush control Bit 31 9 always 0 Bit 8 TrigIn always 1 to indicate that triggers are indicated Bit 7 4 always 0 Bit 3 2 always 0 Bit 1 EnFCont In Sync Trace mode Select_Pin_Protocol register bit1 0 00 this bit is forced to 1 the formatter is automatically enabled in continu...

Page 1078: ...mulus register to output a value 31 18 DBG register map The following table summarizes the Debug registers Table 231 DBG register map and reset values Addr Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0xE0042000 DBGMCU_ IDCODE REV_ID Reserved DEV_ID Reset value 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0xE0042004 DBGMCU_CR Reserved ...

Page 1079: ... map on page 39 and Table 3 Register boundary addresses Note added to Section 23 2 USB main features on page 599 and Section 24 2 bxCAN main features on page 630 Figure 4 Power supply overview and On 100 pin and 144 pin packages modified Formula added to Bits 25 24 description in CAN bit timing register CAN_BTR on page 659 Section Figure 28 DMA block diagram in high density STM32L15xxx devices on ...

Page 1080: ...tion modified in Table 14 Stop mode Clock control register RCC_CR reset value modified Note added in ASOS and ASOE bit descriptions in 6 4 2 on page 81 Section 31 16 2 Debug support for timers watchdog bxCAN and I2C modified Table 231 DBG register map and reset values updated Section 23 5 3 Buffer descriptor table clarified Center aligned mode up down counting on page 289 and Center aligned mode u...

Page 1081: ...AN_BTR bit 8 is reserved in Table 180 bxCAN register map and reset values CAN master control register CAN_MCR on page 650 corrected VREF range corrected in Table 65 ADC pins and in On 100 pin and 144 pin packages on page 66 Start condition on page 733 updated Note removed in Table 34 CAN1 alternate function remapping Note added in Table 43 TIM4 alternate function remapping In Section 9 4 2 AF rema...

Page 1082: ...added Appendix A Important notes removed 22 May 2008 4 continued on next page Reference manual updated to apply to devices containing up to 512 Kbytes of Flash memory High density devices Document restructured Small text changes Definitions of Medium density and High density devices added to all sections In Section 3 Memory and bus architecture on page 47 Figure 1 System architecture on page 47 Fi...

Page 1083: ...terrupt event GPIO mapping In Section 13 DMA controller DMA on page 263 number of DMA controllers and configurable DMA channels updated Figure 48 DMA block diagram in connectivity line devices on page 264 updated notes added Note updated in Section 13 3 2 Arbiter on page 266 Note updated in Section 13 3 6 Interrupts on page 269 Figure 50 DMA1 request mapping on page 270 updated DMA2 controller on ...

Page 1084: ...view on page 66 modified Section 5 1 2 Battery backup domain on page 67 modified Section 7 2 5 LSI clock on page 93 specified Section 9 1 4 Alternate functions AF on page 157 clarified Note added to Table 45 TIM2 alternate function remapping on page 173 Bits are write only in Section 13 4 2 DMA interrupt flag clear register DMA_IFCR on page 274 Register name modified in Section 11 3 1 ADC on off c...

Page 1085: ... specified NWE signal behavior corrected in Figure 203 Synchronous multiplexed write mode PSRAM CRAM on page 519 The FSMC interface does not support COSMO RAM and OneNAND devices and it does not support the asynchronous wait feature SRAM and ROM 32 memory data size removed from Table 107 NOR Flash PSRAM supported memories and transactions on page 497 Data latency versus NOR Flash latency on page 5...

Page 1086: ... definition in PC Card NAND Flash control registers 2 4 FSMC_PCR2 4 on page 535 Bit definitions updated in FIFO status and interrupt register 2 4 FSMC_SR2 4 on page 536 Note modified in ADDHLD and ADDSET bit definitions in SRAM NOR Flash chip select timing registers 1 4 FSMC_BTR1 4 on page 523 Bit 8 is reserved in PC Card NAND Flash control registers 2 4 FSMC_PCR2 4 on page 535 MEMWAIT 15 8 bit de...

Page 1087: ...receiver modified Overrun underrun error OVR on page 740 clarified Section 26 3 7 DMA requests and Section 26 3 8 Packet error checking updated In Section 26 6 1 Control register 1 I2C_CR1 note modified under STOP bit and notes modified under POS bit Receiver mode modified in DR bit description in Section 26 6 5 Data register I2C_DR Note added to TxE and RxNE bit descriptions in Section 26 6 6 Sta...

Page 1088: ... PSRAM supported memories and transactions on page 497 and Single burst transfer modified Register numbering and address offset corrected in Section 22 9 6 SDIO response 1 4 register SDIO_RESPx on page 585 In Section 24 Controller area network bxCAN DBF bit reset value and access type modified small text changes SPI section note added in Section 25 2 2 I2S features Slave select NSS pin management ...

Page 1089: ..._BTR in Section 21 Flexible static memory controller FSMC Section 25 Serial peripheral interface SPI structure revised NSS description clarified in Section 25 3 1 General description Section 25 2 2 I2S features modified Note added to Section 25 3 2 Configuring the SPI in slave mode Figure 239 Data clock timing diagram modified Section 25 3 4 Configuring the SPI for Simplex communication clarified ...

Page 1090: ... bit description modified in TDES0 Transmit descriptor Word0 and TDES0 Transmit descriptor Word0 Transmit time stamp control and status on page 967 Ethernet MAC hash table high register ETH_MACHTHR description clarified Description of bits 6 2 modified in Ethernet DMA bus mode register ETH_DMABMR Peripheral register access specified in Section 29 8 Ethernet register descriptions 23 Apr 2010 11 XL ...

Page 1091: ...f the manual Added FSMC boundary addresses to Table 3 on page 50 Added paragraph on HSI to Programming and erasing the Flash memory on page 59 Updated Table 11 12 12 ADC injected sequence register ADC_JSQR on page 240 Added VREF shared with ADC in Section 12 1 DAC introduction on page 243 Updated example in Section 14 4 19 TIM1 TIM8 DMA control register TIMx_DCR on page 343 and other timer section...

Page 1092: ... 666 CAN_RDLxR 666 CAN_RDTxR 665 CAN_RF0R 655 CAN_RF1R 656 CAN_RIxR 664 CAN_TDHxR 663 CAN_TDLxR 663 CAN_TDTxR 662 CAN_TIxR 661 CAN_TSR 653 CRC_DR 63 CRC_IDR 63 D DBGMCU_CR 1069 DBGMCU_IDCODE 1055 DMA_CCRx 275 DMA_CMARx 277 DMA_CNDTRx 276 DMA_CPARx 277 DMA_IFCR 274 DMA_ISR 273 E ETH_DMABMR 1029 ETH_DMACHRBAR 1041 ETH_DMACHRDR 1041 ETH_DMACHTBAR 1041 ETH_DMACHTDR 1040 ETH_DMAIER 1038 ETH_DMAMFBOCR 1...

Page 1093: ...LCKR 168 GPIOx_ODR 167 I I2C_CCR 756 I2C_CR1 747 I2C_CR2 749 I2C_DR 751 I2C_OAR1 750 I2C_OAR2 751 I2C_SR1 752 I2C_SR2 755 I2C_TRISE 757 IWDG_KR 479 IWDG_PR 479 IWDG_RLR 480 IWDG_SR 480 O OTG_FS_CID 851 OTG_FS_DAINT 868 OTG_FS_DAINTMSK 869 OTG_FS_DCFG 863 OTG_FS_DCTL 864 OTG_FS_DIEPCTL0 871 OTG_FS_DIEPEMPMSK 870 OTG_FS_DIEPINTx 879 OTG_FS_DIEPMSK 866 OTG_FS_DIEPTSIZ0 881 OTG_FS_DIEPTSIZx 883 OTG_FS...

Page 1094: ...594 SDIO_POWER 584 SDIO_RESPCMD 587 SDIO_RESPx 587 SDIO_STA 591 SPI_CR1 716 SPI_CR2 719 SPI_CRCPR 721 SPI_DR 721 SPI_I2SCFGR 723 SPI_I2SPR 724 SPI_RXCRCR 722 SPI_SR 720 SPI_TXCRCR 722 T TIMx_ARR 400 439 449 462 TIMx_BDTR 341 TIMx_CCER 335 398 438 448 TIMx_CCMR1 331 394 435 445 TIMx_CCMR2 334 397 TIMx_CCR1 339 401 440 450 TIMx_CCR2 340 401 440 TIMx_CCR3 340 402 TIMx_CCR4 341 402 TIMx_CNT 338 399 43...

Page 1095: ...RM0008 Index Doc ID 13902 Rev 12 1095 1096 W WWDG_CFR 486 WWDG_CR 485 WWDG_SR 486 ...

Page 1096: ...D WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLIC...

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