3. Serial RapidIO Electrical Interface > Programmable Transmit and Receive Equalization
76
Tsi574 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
Channels are numbered 0 through 3. Channels are never reordered. When lanes are not swapped, the
following mapping between channels and lanes is used:
•
Channel 0 maps to Lane A
•
Channel 1 maps to Lane B
•
Channel 2 maps to Lane C
•
Channel 3 maps to Lane D
When lanes are swapped, the following mapping between channels and lanes is used:
•
Channel 0 maps to Lane D
•
Channel 1 maps to Lane C
•
Channel 2 maps to Lane B
•
Channel 3 maps to Lane A
Even numbered ports in 4x mode are associated with lanes A-D. When an even numbered port is in 1x
mode, it is associated with lane A. Odd numbered ports are always associated with lane B.
3.6.2.3
Tx and Rx Swapping
The operations in the SMACx_DLOOP_CLK_SEL register are associated with lanes. When lanes are
swapped, the channels associated with these operations must change. The user can independently swap
only the Tx or Rx lanes.
Operations on channels, as supported by the MAC Channel Configuration registers always operate on
the specific channels regardless of the lane swap settings for a MAC (see
Configuration Channel 0” on page 355
). If lane swap functionality is enabled in the system, the proper
channels must also be configured. The channel number of a transmit lane and a receive lane differs
when Tx lanes are swapped and Rx lanes are not, or vice versa.
3.7
Programmable Transmit and Receive Equalization
The Tsi574 has programmable drive strengths and de-emphasis of a transmit lane. The Tsi574 also has
the ability to internally boost the received signal. This functionality is described in the following
sections.
3.7.1
Transmit Drive Level and Equalization
The Tsi574 has programmable drive strengths and de-emphasis of a transmit lane. This ability adjusts
for the electrical characteristics that can degrade the signal quality of a link which connects a device to
the Tsi574. Decreasing the drive strength of signals also provides the ability to reduce the power
consumption of a port.
Ti
p
The
RapidIO Interconnect Specification (Revision 1.3)
uses Lane 0, 1, 2, 3 terminology
instead of the IDT terminology of Lane A, B, C, D.
