3. Serial RapidIO Electrical Interface > Port Lanes
74
Tsi574 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
3.5.4.1
Signals Sampled After Reset
After a hardware reset is de-asserted, the Tsi574 samples the state of the SP{n}_PWRDN pins and only
powers up the ports that are enabled.
Each RapidIO port has a unique pin, SPn_PWRDN.
The sampled state of the pins is available in the
“SRIO MAC x Digital Loopback and Clock Selection
register. This register can be overwritten at any time — during boot-up through
the I
2
C interface, JTAG, or during normal operation through the RapidIO interfaces — allowing the
system software to override the pin-based configuration.
3.5.4.2
4x Mode and Odd Ports
When a pair of ports sharing the same MAC are configured in 4x mode, only the even-numbered port is
used. The odd numbered port should be powered down by software or configuration pins to minimize
power consumption.
3.6
Port Lanes
For ports that support both 1x and 4x mode functionality, even and odd number ports have different
capabilities. Even numbered ports can operate in either 4x or 1x mode, while odd numbered ports can
only operate in 1x mode. When the even numbered port is operating in 4x mode, it has control over all
four differential pairs (designated Lanes A, B, C and D).
In 4x mode, the default state of the odd numbered port is powered on. All registers in the even and odd
numbered port are accessible but the odd numbered port does not have access to the PHY. In order to
decrease the power dissipation of the port, the odd numbered port can be powered down in this
configuration. When the even numbered port is operating in 1x mode it uses only Lane A and the odd
numbered port is permitted to operate in 1x mode using Lane B.
For more information on lanes, refer to
“Lanes and Channels” on page 75
.
3.6.1
Lane Synchronization and Alignment
When coming out of reset, the transmit side of the port must continuously send out /K28.5/ code groups
on each lane to assist the receive side of its link partner to synchronize. Once a /K28.5/ code group is
detected by the receive port, another 127 /K28.5/ code groups must be received error free before the
receive port can declare that it is synchronized. No other useful information is communicated between
the link partners until the ports are synchronized.
For a 4x port, after lane synchronization is complete, lane alignment starts. The port transmits /A/’s
(||A||) on all four lanes, according to the
RapidIO Interconnect Specification (Revision 1.3)
idle
sequence generation rules. Reception of four ||A||’s without the intervening reception of a misaligned
column is the condition for achieving lane alignment. A misaligned column (that is a column with at
least one ||A|| but not all ||A||s in a row) causes the alignment process to restart. Bit errors, or receptions
of rows without all /A/’s, result in sampling/buffering adjustments in an attempt to achieve alignment.
For more information, see the
RapidIO Interconnect Specification (Revision 1.3).
Port 0 is the default port and can only be powered down through a direct register write.
