Renesas IDT Tsi574, User Manual

Page: 165 / 514

7. I
2
C Interface > Boot Load Sequence 165
Tsi574 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
Figure 36: Boot Load Sequence
I2C_SCLK
EEPROM “Reset” Sequence
Retry Up to 6 Times to Find EEPROM
Not Idle
R
Wait for Bus Idle S Boot Addr
A
N
Wr Idle Detect EEPROM Reset
Idle
PerAdr MSB A PerAdr LSB A Boot Addr Rd A
RegCnt MSB A RegCnt LSB A 0xFF A 0xFF A/N
1 2 8 9
I2C_SD
9 Clocks with I2C_SD released High
RegAdr MSB A RegAdr LSB A RegData MSB A RegData LSB A/N
S Boot Adr A Wr R PerAdr MSB A PerAdr LSB A Boot Addr Rd A
S Boot Addr A Wr
Set peripheral address and switch to read mode
Check validity of register count, exit if bad
If register count is zero (0), go to Chain Check Add 8 to peripheral address
If not at page_mode boundary*, go to Read Register Info
If at page_mode boundary, go to Set Reg Info Per Address
Select next device
Boot Init and Device Detect
Set Register Count Peripheral Address
Read Register Count (from the first 2 bytes of the EEPROM after reset.
Set Register Info Peripheral Address
Read Register Info
Write Data into internal register
Select Chained Device
Read eight (8) byte register count field
Chain Check
If last register load was to I2C_BOOT_CNTRL and CHAIN bit set goto Select Chained Device, else exit
Goto Set Register Count Peripheral Address
Set peripheral address and switch to read mode
Read 4-byte register address and 4-byte register data
Add 8 to peripheral address If register count is zero (0), go to Chain Check
Exit
P
Generate STOP Condition, set boot load status and interrupts
Device detection
2-byte PerAdr Only
2-byte PerAdr Only
After 6 NACKs, goto Exit
Collision
P
Hard Reset
9 Clocks with I2C_SD released High
* For information about page mode boundary, see PAGE_MODE in “I
2
C Boot Control
Register” . For information about PA_SIZE, see “I
2
C Master Configuration Register” .