7. I
2
C Interface > Tsi574 as I
2
C Slave
152
Tsi574 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
7.5.2
Slave Device Addressing
The Tsi574 supports 7-bit device addressing. The device address of the Tsi574 is set in the SLV_ADDR
field of the
C Slave Configuration Register”
. For the Tsi574 to respond to an external master, the
slave address on the bus must match either the address in the SLV_ADDR field, or the SMBus alert
response address (see
“SMBus Alert Response Protocol Support”
. However, an address of all zeros
(0000000) never triggers a response because this address is used for the START byte and General Call
protocol. Neither the START byte or General Call protocol are supported by the Tsi574.
The SLV_ADDR field can be changed at any time, either using the boot load sequence or by the
processor/host. At power-up, the lower 2 bits of the 7-bit device address (defined by SLV_ADDR) are
loaded from the PWRUP_I2C pin. This allows the user to support up to four separate Tsi574 devices on
the same I
2
C bus.Changing the SLV_ADDR field does not change the value of the lower 2 bits unless
those bits are unlocked by first setting the SLV_UNLK field in the
C Slave Configuration Register”
7.5.3
Slave Peripheral Addressing
The Tsi574 peripheral space comprises an addressable range of 256 bytes (from 0x00 to 0xFF) that can
be directly read and written by an external I
2
C master device. When an external master sets the
peripheral address, this sets a pointer (viewable in the SLV_PA field of the
) maintained in the Tsi574 that determines where bytes read and written by the external
master are within the peripheral address space.
This 256-byte space is mapped to the Externally Visible Registers within the I
2
C Interface; these
registers all start with EXI2C_ (see
C Internal Write Address Register”
registers can be accessed either directly by an external master using the addresses in the peripheral
address space, or by the processor/host using the internal register bus addresses. Depending on how the
registers are accessed also defines their properties: for example, some registers are read-only through
the peripheral address space but read/write through the internal register bus, and vice-versa.
The next section discusses the mapping between the peripheral address space and the externally visible
registers.
If the Tsi574 masters an I
2
C transaction and the device address matches the 7-bit address
programmed by SLV_ADDR, the Tsi574 will respond to its own transaction. This is the only
method that allows software to write to any of the externally visible registers that are
read-only from the internal register bus.
Ti
p
The Tsi574 only responds as a slave if the SLV_EN bit in the
is set to 1.
