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12. Serial RapidIO Registers > Serial Port Electrical Layer Registers

368

Tsi574 User Manual

June 6, 2016

Integrated Device Technology

www.idt.com

12.10.7

SRIO MAC x SerDes Configuration GlobalB

This register configures the SerDes of all four ports.

Register name: SMAC{0,2,4,6}_CFG_GBLB

Reset value: 0x0023_014F

Register offset: 130C4, 132C4, 134C4, 136C4

Bits

00:07

Reserved

08:15

Reserved

MPLL_PRESCALE[1:0]

Unused

16:23

Unused

24:31

Unused

Reserved

Bits

Name

Description

Type

Reset

Value

0:9

Reserved

10:11

MPLL_PRES

CALE[1:0]

Controls the MPLL’s REF_CLK prescaler.

Should be set to 2’b10 in Tsi574.

Mapping:

00 = Reserved

01 = Reserved

10 = Divide REF_CLK by 2

11 = Unused

Transition only during RESET or when the MPLL Is disabled.

R/W

0x2

12:25

Unused

N/A

R/W

0xC05

26:31

Reserved

N/A

0x0F

Summary of Contents for IDT Tsi574

Page 1: ...IDT Tsi574 Serial RapidIO Switch User Manual June 6 2016 Titl...

Page 2: ...n request Items identified herein as reserved or undefined are reserved for future definition IDT does not assume responsibility for conflicts or incompatibilities arising from the future definition o...

Page 3: ...bric ISF 30 1 6 Internal Register Bus AHB 30 1 7 I2 C Interface 30 1 8 JTAG Interface 32 2 Serial RapidIO Interface 35 2 1 Overview 35 2 1 1 Features 35 2 1 2 Transaction Flow Overview 36 2 1 3 Mainte...

Page 4: ...3 4 1 Changing the Clock Speed 70 3 4 2 Changing the Clock Speed Through I2C 71 3 5 Port Power Down 71 3 5 1 Default Configurations on Power Down 72 3 5 2 Special Conditions for Port 0 Power Down 72...

Page 5: ...verview 104 5 1 6 Multicast Work Queue 105 5 1 7 Broadcast Buffers 105 5 2 Multicast Group Tables 108 5 2 1 Configuring Basic Associations 110 5 2 2 Configuring Multicast Masks 111 5 2 3 Configuring M...

Page 6: ...aster Data Transactions 149 7 5 Tsi574 as I2C Slave 149 7 5 1 Slave Clock Stretching 151 7 5 2 Slave Device Addressing 152 7 5 3 Slave Peripheral Addressing 152 7 5 4 External I2 C Register Map 153 7...

Page 7: ...ments 190 8 3 1 Clock Speeds 190 8 3 2 Tsi574 ISF Arbitration Settings 190 8 3 3 Tsi574 RapidIO Transmission Scheduler Settings 191 8 3 4 Tsi574 RapidIO Buffer Watermark Selection Settings 191 8 4 Por...

Page 8: ...39 12 5 2 RapidIO Device Information CAR 240 12 5 3 RapidIO Assembly Identity CAR 241 12 5 4 RapidIO Assembly Information CAR 242 12 5 5 RapidIO Processing Element Features CAR 243 12 5 6 RapidIO Swit...

Page 9: ...and Debug 2 294 12 7 14 RapidIO Port x Packet Error Capture CSR 2 and Debug 3 294 12 7 15 RapidIO Port x Packet Error Capture CSR 3 and Debug 4 295 12 7 16 RapidIO Port x Error Rate CSR 296 12 7 17 Ra...

Page 10: ...C x SerDes Configuration Global 364 12 10 7 SRIO MAC x SerDes Configuration GlobalB 368 12 10 8 SRIO MAC x Digital Loopback and Clock Selection Register 369 12 11 Internal Switching Fabric ISF Registe...

Page 11: ...figuration Register 425 13 2 12 I2C Boot Control Register 428 13 2 13 Externally Visible I2C Internal Write Address Register 432 13 2 14 Externally Visible I2C Internal Write Data Register 433 13 2 15...

Page 12: ...l Protocol 470 B Clocking 475 B 1 Line Rate Support 475 B 1 1 Register Requirements Using 125 MHz S_CLK for a 3 125 Gbps Link Rate 476 B 2 P_CLK Programming 479 B 2 1 RapidIO Specifications Directly A...

Page 13: ...ket Queues in Tsi574 89 Figure 20 Multicast Operation Option 1 102 Figure 21 Multicast Operation Option 2 103 Figure 22 Multicast Packet Flow in the Tsi574 106 Figure 23 Relationship Representation 11...

Page 14: ...6 2016 Integrated Device Technology www idt com Figure 43 Congestion Example 198 Figure 44 Register Access From JTAG Serial Data In 200 Figure 45 Register Access From JTAG Serial Data Out 200 Figure 4...

Page 15: ...isible I2C Register Map 153 Table 18 Format for Boot Loadable EEPROM 169 Table 19 Sample EEPROM Loading Two Registers 169 Table 20 Sample EEPROM With Chaining 170 Table 21 I2C Error Handling 172 Table...

Page 16: ...e 47 AC JTAG level programmed by ACJT_LVL 4 0 366 Table 48 SerDes Register Map 390 Table 49 I2C Register Map 403 Table 50 Master Operation Sequence 412 Table 51 Special Characters and Encoding 471 Tab...

Page 17: ...ctive state of logic 0 or the lower voltage level and is denoted by a lowercase _b An active high signal has an active state of logic 1 or the higher voltage level and is not denoted by a special char...

Page 18: ...and is revised as required Formal Contains information about a final customer ready product and is available once the product is released to production Revision History June 6 2016 Formal Updated Res...

Page 19: ...xt Script May 25 2012 Formal Updated the second step in Removing a Destination ID to Multicast Mask Association Updated the second paragraph in Payload Updated Port writes and Multicast Updated the re...

Page 20: ...About this Document 20 Tsi574 User Manual June 6 2016 Integrated Device Technology www idt com...

Page 21: ...ng 40 Gbits s aggregate bandwidth The Tsi574 is part of a family of switches that enable customers to develop systems with robust features and high performance at low cost The Tsi574 provides designer...

Page 22: ...h improves system cost and product time to market Figure 2 Processor Farm Mezzanine Diagram 80B803B_BK001_03 Up to 2 Serial RapidIO Ports 1x 4x Mode or Up to 4 Serial RapidIO Ports 1x Mode Up to 2 Ser...

Page 23: ...in 1x Serial mode each 4x port can be configured independently as two 1x ports Operating baud rate per data lane 1 25 Gbit s 2 5 Gbit s or 3 125Gbit s Full duplex bandwidth 12 5 Gbit s inbound and 12...

Page 24: ...One multicast engine provides dedicated multicast resources without impacting throughput on the ports Eight multicast groups Sustained multicast output bandwidth up to 10 Gbit s per egress port 10 Gbi...

Page 25: ...nts head of line blocking on each port Eight packet buffers per ingress port Eight packet buffers per egress port Register Access Registers can be accessed from any RapidIO interface and both the JTAG...

Page 26: ...ebug packet generation and capture Multicast functionality described in RapidIO Interconnect Specification Revision 1 3 Part 11 Head of line blocking avoidance 1 2 2 Transaction Flow Overview Packets...

Page 27: ...e 1 3 Multicast Engine The Tsi574 multicast functionality is compliant to the RapidIO Version 1 3 Part 11 Multicast Specification 1 3 1 Multicast Operation In a multicast operation packets are receive...

Page 28: ...testing Each pair of ports share four differential transmit lanes and four differential receive lanes Even and odd number ports have different capabilities Even numbered ports can operate in either 4x...

Page 29: ...a port configured for 4x mode 3 125 Gbit s inbound and 3 125 Gbit s outbound bandwidth at 3 125 Gbps for a port configured for 1x mode Adjustable receive equalization that is programmable per lane Ser...

Page 30: ...s AHB allows any RapidIO port to configure and maintain the entire device When the Tsi574 receives a RapidIO maintenance packet destined for itself it translates the packet into register read or write...

Page 31: ...ROM or by software configuration Provides mailbox registers for communicating between maintenance software operating on RapidIO based processors and external I2 C masters Supports I2 C operations up t...

Page 32: ...its device address without consideration for any other meaning General Call The general call address will be NACK d and the remainder of the transaction ignored up to a subsequent Restart or Stop 1 8...

Page 33: ...1 Functional Overview JTAG Interface 33 Tsi574 User Manual June 6 2016 Integrated Device Technology www idt com Bypass Hi Z IDCODE Clamp User data select...

Page 34: ...1 Functional Overview JTAG Interface 34 Tsi574 User Manual June 6 2016 Integrated Device Technology www idt com...

Page 35: ...iant with the RapidIO Interconnect Specification Revision 1 3 This section describes the transport layer features common to all Tsi574 RapidIO interfaces The RapidIO interface has the following capabi...

Page 36: ...kets to be transmitted from the ISF The integrity of packets forwarded through the ISF is retained by sending the CRC code received with the packet For more information on the input and ouput queues r...

Page 37: ...ved However in both modes the egress port always operates in cut through mode the packet is immediately forwarded A copy of the packet is saved at the egress port so that it can be retransmitted shoul...

Page 38: ...O Route Configuration DestID CSR on page 253 using the LRG_CFG_DESTID and CFG_DESTID fields the upper seven bits of the destination ID in the LRG_CFG_DESTID field is truncated The LUT of all the ports...

Page 39: ...tID 15 8 BASE field in SPx_ROUTE_BASE Yes No Obtain egress port from GLOBAL LUT using DestID 15 8 Obtain egress port from LOCAL LUT using DestID 7 0 LUT entry mapped and egress port Port_Total Yes No...

Page 40: ...rt x Mode CSR on page 302 2 3 3 Flat Mode A flat mode LUT is a table that maps destination IDs 0 to 511 to user selectable egress ports Destination IDs that fall outside this range are sent to the egr...

Page 41: ...Attributes Default Port CSR on page 255 If the default port is unmapped the packet is discarded and the Tsi574 raises the IMP_SPEC_ERR bit in the RapidIO Port x Error Detect CSR on page 286 100 1FF 0...

Page 42: ...nto Global LUT through the PORT field in the RIO_ROUTE_CFG_PORT register Tsi57x Tsi57x Tsi57x DSP DSP DSP DSP DestID 0x13 DestID 0x11 DestID 0x12 DestID 0x10 DestIDs accessible through this link 0x02x...

Page 43: ...0x0002 or 0x02 is routed by the switch to output port 1 A destination ID of 0x0003 or 0x03 is routed out port 0 and destination IDs greater than 0x1FF are routed out port 4 Figure 8 Flat Mode LUT Conf...

Page 44: ...r write this register to change the configuration of the destination ID Example One Adding a Lookup Table Entry In the following example routing is added for all ports to route destination ID 0x98 to...

Page 45: ...0x54 2 3 4 Hierarchical Mode The hierarchical mode of operation of the LUT allows the full range of 65536 16 bit destination IDs to be mapped This mode is enabled by setting RIO_SP_MODE LUT_512 0 The...

Page 46: ...ly advertises the switch can map 512 destination IDs This is due to the fact that RIO_LUT_SIZE is a register with global scope but the ports can be independently configured for either flat mode or hie...

Page 47: ...ets A B C 00 FF 00 FF MSB of DestID Port LSB of DestID Port xx DestID LSB is loaded into Local LUT through the CFG_DESTID field in the RIO_ROUTE_CFG_DESTID register DestID MSB is loaded into Global LU...

Page 48: ...time before packet traffic starts w 0078 0x0A 3 Program the Global LUT with the MSB of the DEST_IDs to be routed using the following write operations W 11870 0x0 SP8_ROUTE_CFG_DESTID W 11874 0x9 SP8_...

Page 49: ...red mode of operation 2 3 6 Lookup Table Parity Each entry in the lookup table is parity protected A LUT parity error is detected in an entry when an incoming packet causes the ingress port to read th...

Page 50: ...the request queue The TEA error is reported through a port write and or an interrupt Programmable in the Fabric Control Register and the interrupt status can be checked in the Fabric Interrupt Status...

Page 51: ...table entries must be programmed to a known value after reset to achieve predictable operation When a lookup table entry s parity is incorrect the lookup table entry is in a parity error state Table 2...

Page 52: ...is to be sent parity errors are still detected and flagged if they occur Since the LUTs power up in a random state the occurrence of a LUT_PAR_ERR will be a random occurrence until all LUT entries ar...

Page 53: ...y data associated with the request The maintenance response packet is generated by the Tsi574 using the success or failure of the access and data from a read operation CRC is computed and the packet i...

Page 54: ...count is 0 Do not care Send port write and set interrupt if enabled Bit 8 in RapidIO Logical and Transport Layer Error Detect CSR Tsi574 is not an endpoint device Port Write Hop count is 0 Do not care...

Page 55: ...ol and Reset Control Symbol Interrupt CSR on page 304 Additionally the logical OR of all per port Multicast Event interrupt status is available in both the MCS field in the RapidIO Port x Multicast Ev...

Page 56: ...orts enabled to forward multicast control symbols then transmit an MCS see RapidIO Serial Port x Control CSR on page 273 The minimum time between two transitions on the MCES pin is 1 s For example whe...

Page 57: ...es With the exception of maintenance packets the Tsi574 does not re compute CRC codes for packets The CRC code is forwarded with the packet across the ISF and the packet is transmitted with the same C...

Page 58: ...of the inbound outbound and outstanding ACK_IDs 4 The system host instructs the Tsi574 to generate a link request to its link partner using the RapidIO Serial Port x Link Maintenance Request CSR on pa...

Page 59: ...er packets other than maintenance requests responses may be sent by the Tsi574 INPUT_EN Controls whether packets other than maintenance requests responses may be received by the Tsi574 In RapidIO Port...

Page 60: ...pendent Register to assert an interrupt or send port write transactions see RapidIO Port x Control Independent Register Once the system host is notified that a new component is inserted the LINK_INIT_...

Page 61: ...l packets arriving from the ISF for transmission to flush any existing packets in the transmit and receive queues of the port and to prevent new packets from being received from the device about to be...

Page 62: ...LINK_INIT_NOTIFICATION_EN in the RapidIO Port x Control Independent Register continues to be enabled When the component is removed lane synchronization and or lane alignment is lost The errors detect...

Page 63: ...tual duration of the LOLS condition has no impact on the process once the link is re acquired Any packets transmitted to the Tsi574 are not acknowledged because the port is in input error stopped stat...

Page 64: ...ed in the PORT_ERR bit in the RapidIO Port x Error and Status CSR When the PORT_ERR bit is set and port writes are enabled a port write is generated If the dead link timer expires which the link is no...

Page 65: ...rt and one odd numbered port Each port has flexible testing features including multiple loopback modes and bit error rate testing Each pair of ports share four differential transmit lanes and four dif...

Page 66: ...t configured for 4x mode 3 125 Gbit s inbound and 3 125 Gbit s outbound bandwidth at 3 125 Gbps for a port configured for 1x mode Adjustable receive equalization that is programmable per lane Serial l...

Page 67: ...er one 4x mode port or Port 0 and Port 1 can be dual 1x mode ports Figure 13 Port Configuration 3 3 Port Aggregation 1x and 4x Modes The RapidIO ports on the Tsi574 are grouped into pairs that share t...

Page 68: ...th a register write in order to restore the desired condition The PWRDNx4 and PWRDNx1 bits must both be asserted prior to changing the state of the MAC_MODE bit Therefore changing the MAC operation fr...

Page 69: ...in port mode by writing the OVER_PWIDTH field on either the Tsi574 or in its link partner see RapidIO Serial Port x Control CSR on page 273 The current operating link width is available in the INIT_PW...

Page 70: ...apidIO Interconnect Specification Revision 1 3 requires the receive and transmit signals must operate at the same baud rate This means a port must transmit at the same clock rate that it receives with...

Page 71: ...f the Tsi574 RapidIO ports can be powered down to minimize power consumption when the port is not required However port 0 has special power down requirements that must be followed see Special Conditio...

Page 72: ...that port is reset to the default value The port write destinationID must be re written for the whole device after a port is shut down and restored Similarly multicast settings for the entire device...

Page 73: ...r on page 369 To save power assert the SPn 1_PWRDN pin and or set the PWDN_X1 bit to 1 in the SRIO MAC x Digital Loopback and Clock Selection Register on page 369 If this bit is not set Port n 1 consu...

Page 74: ...the odd numbered port does not have access to the PHY In order to decrease the power dissipation of the port the odd numbered port can be powered down in this configuration When the even numbered port...

Page 75: ...lane swap setting for the entire device is controlled by two configuration pins SP_RX_SWAP and SP_TX_SWAP see Signals on page 213 Register fields SWAP_TX and SWAP_RX fields in the SRIO MAC x Digital L...

Page 76: ...Operations on channels as supported by the MAC Channel Configuration registers always operate on the specific channels regardless of the lane swap settings for a MAC see SRIO MAC x SerDes Configurati...

Page 77: ...a for calculating the TX_BOOST is shown in SRIO MAC x SerDes Configuration Channel 0 on page 355 Figure 14 Drive Strength and Equalization Waveform 3 7 2 Receive Equalization The received signal can b...

Page 78: ...here each loopback is implemented in the Tsi574 Figure 15 Tsi574 Loopbacks Internal Switching Fabric Serial RapidIO Physical and Transport Layers Even numbered Ports 4x mode or 1x mode Odd Numbered Po...

Page 79: ...o cause packets to loop back in this fashion configure the lookup tables LUTs so the destination IDs are destined for the incoming port For more information on LUT programming refer to Lookup Tables 3...

Page 80: ...es Framing Depending on the type of testing required in the system the SerDes framing function might need to be disabled in the Tsi574 For example framing must be disabled if a BERT test is performed...

Page 81: ...ixed Pattern based BERT Fixed pattern based BERT uses data in software configurable registers to send an alternating pattern of 10 bit 8B10B code groups Fixed pattern based BERT does not produce error...

Page 82: ...X_ALIGN_EN bit in the SMACx_CFG_CH 0 3 register 3 9 4 Using PRBS Scripts for the Transmitters and Receivers IDT provides PRBS scripts in PRBS Scripts All of the PRBS scripts affect all of the ports th...

Page 83: ...ge 86 4 1 Overview The Internal Switching Fabric ISF is the crossbar switching matrix at the core of the Tsi574 It transfers packets from ingress ports to egress ports and prioritizes traffic based on...

Page 84: ...attempt to send a packet to the same egress port queuing is required at the ingress ports Special arbitration algorithms at both the ingress and egress sides of the fabric ensure that head of line blo...

Page 85: ...ation appears near the front of a RapidIO packet Congestion Configuring a port for cut through mode does not guarantee that the packet is sent to the ISF immediately after the destination ID arrives f...

Page 86: ...Figure 17 Only HOL packets at the ingress queues or broadcast buffers are considered for arbitration Figure 17 Egress Arbitration Weighted Round Robin and Strict Priority 4 3 1 Strict Priority Arbitra...

Page 87: ...same arbiter exists for each Priority Group Depending on the setting of WRR_EN the Multicast Traffic can participate in the Round Robin arbiter The WRR arbiter consists of a Round Robin arbiter which...

Page 88: ...s not reached Once the WEIGHT value is reached a non chosen packet is selected instead and the Chose Packet Counter is reset In the case when no chosen packet is available when its opportunity arises...

Page 89: ...store the incoming packets when the egress port has a slower baud rate than the ingress port The depth of the buffer queue dictates the switch fabric flow control This flow control determines how man...

Page 90: ...free buffers is greater than the programmed watermark of the associated priority For example when the PRIO1WM field is programmed to three a priority 1 packet is accepted only when there are four or m...

Page 91: ...while one packet in the burst is being transmitted and is awaiting acknowledgment another packet in the burst cannot be accepted or transmitted Watermarks can be used to guarantee that two buffers ar...

Page 92: ...er to Loss of Lane Synchronization on page 62 4 4 2 Input Queue for the ISF Port Each ingress port has a queue that holds up to eight packets Buffering is required to deal with any congestion in the I...

Page 93: ...e HOL blocking can result HOL occurs when the packet at the head of a queue is blocked and the packets must remain in the same order This means that no packet in the queue can be sent across the ISF e...

Page 94: ...iter selects a packet to compete in egress arbitration based on the following rules Select the priority 3 packet that can be accepted by its destination fabric port and is closest to the head of the q...

Page 95: ...cket closest to the head of the queue Note that this packet cannot make progress Else if there are no such packets Select the priority 1 packet that can be accepted by its destination fabric port and...

Page 96: ...er than Y that appear ahead of packet X in the queue must also be 0 Reorder limiting is disabled by default and can be enabled by setting the RDR_LIMIT_EN bit to 1 in the Fabric Control Register on pa...

Page 97: ...rt on page 115 Any priority N packet is accepted before packets of priority N 1 Within each priority the multicast work queue uses the round robin algorithm The multicast work queue operates in strict...

Page 98: ...ace for 8 more bytes of data to be received the multicast work queue is signalled that no more packet data can be accepted by the broadcast buffer If there is sufficient space for 8 more bytes of data...

Page 99: ...idles whenever the ingress port has not yet received data for transmission However during the transfer the egress port cannot receive information from ports other than the egress port Therefore when...

Page 100: ...4 Internal Switching Fabric Packet Queuing 100 Tsi574 User Manual June 6 2016 Integrated Device Technology www idt com...

Page 101: ...estinationID and Transaction Type TT field value If no match is found for the destinationID and TT field then the ingress lookup tables are used to route the packet A maximum of eight different DestID...

Page 102: ...ultiple Tsi57x Switches Tsi57x multicast support is designed to allow information from a single source to be multicast efficiently over a tree topology within a RapidIO fabric see Figure 20 When two o...

Page 103: ...multicast group is associated with a unique destinationID and TT of a packet Note A packet is never multicast back out of the port that it is received on regardless of whether or not this port is incl...

Page 104: ...the Broadcast Buffers associated with the ports in the vector Transmission between the multicast work queue and the Broadcast Buffers uses a dedicated ISF path that is separate from those used to rout...

Page 105: ...y Timer on page 117 When the multicast work queue has computed the multicast vector it arbitrates to transmit packet copies to the broadcast buffers accordingly The work queue always operates in a cut...

Page 106: ...r a packet copy to the maximum value of seven For more information refer to Error Management of Multicast Packets on page 116 The following figure shows a step by step multicast operation through the...

Page 107: ...t work queue operates in cut through mode 5 By consulting the multicast group table Ports 0 1 2 and 7 are identified as members of the vector and as the receiving ports Because Port 1 is the ingress p...

Page 108: ...he 8 bit destination ID of five and the 16 bit destination ID of five requires two entries in the multicast group table If the destination ID contained in an incoming packet matches any of the eight e...

Page 109: ...O Multicast DestID Configuration Register on page 258 and RapidIO Multicast DestID Association Register on page 259 To execute either of the previous two operations port removal or group deletion the...

Page 110: ...r accesses are required 1 Set up the operation to associate destination ID 0x1234 with multicast mask 0 Write the value 0x1234_0000 to the RapidIO Multicast DestID Configuration Register on page 258 T...

Page 111: ...is example the state of the multicast masks is unknown and therefore the masks must be cleared before being configured In order to clear the masks the following register accesses are made 1 Remove all...

Page 112: ...Mask Configuration Register The following figure shows the completed configuration Figure 24 Completed Tables at the End of Configuration Port Participating in Vector 7 6 5 4 3 2 1 0 0 1 2 4 3 5 6 7...

Page 113: ...Write the value 0x0002_0100 to the Multicast Mask Configuration Register Read the value 0x0002_0101 from the Multicast Mask Configuration Register 3 Verify that port 2 is included in mask 2 Write the...

Page 114: ...ister 5 2 3 Configuring Multicast Masks Using the IDT Specific Registers The Tsi574 also has a device specific implementation to configuring the multicast masks This implementation allows the direct w...

Page 115: ...er to accept packets when available No one port can monopolize the RR arbiter When a port skips an opportunity to transmit because it carries no packet at the moment the RR arbiter does not compensate...

Page 116: ...rs operate in cut through mode It is possible for the ingress port s link partner to stomp a packet or terminate it due to some other error condition It is also possible for the ingress port to detect...

Page 117: ...the multicast latency timer expires are discarded A packet copy being transferred from the multicast work queue to the broadcast buffer when the multicast latency timer expires is also discarded Depen...

Page 118: ...issued No other information is latched regarding the packet s that were dropped 5 4 5 Port writes and Multicast Port writes can be multicast to multiple output links depending on the destinationID of...

Page 119: ...otifications on page 131 Interrupt Notifications on page 134 6 1 Overview The Tsi574 has the following ways to notify external devices about events occurring within the switch 1 Generate a RapidIO Por...

Page 120: ...d port receives a transaction with one of the following errors Unmapped entry in LUT Reserved TT field value for data packet or maintenance packet with a hop count not equal to zero The status of this...

Page 121: ...the RapidIO Port x Multicast Event Control Symbol and Reset Control Symbol Interrupt CSR on page 304 as well as the MCS bit in the Global Interrupt Status Register RapidIO Yes No Outbound Queue Thres...

Page 122: ...for link response The Dead Link Timer for a port has expired The Lane Sync Timer for at least one lane of the port has expired The status of this event is contained in the PORT_ERR bit of the RapidIO...

Page 123: ...o link request is outstanding The status of this event is contained in the PROT_ERR bit of the RapidIO Port x Error Detect CSR on page 286 RapidIO Yes Yes1 Delineation Error Error This event is raised...

Page 124: ...in the CS_NOT_ACC bit of the RapidIO Port x Error Detect CSR on page 286 RapidIO Yes Yes1 Packet CRC Error Error This event is raised when a RapidIO port receives a packet with a CRC error The status...

Page 125: ...ery tick of the Error Rate Bias Timer The counts do not decrement below 0 This field only tracks transmission errors that have been unmasked in the Port x Error Rate Enable CSR This counter does not m...

Page 126: ...r the method described in this section uses IDT specific functionality and control symbols to clear the errors by forcing a hardware recovery situation through software 6 4 1 Error Stopped States An I...

Page 127: ...lear error conditions is to create a situation that forces the hardware recovery process to run again This situation is created by sending a control symbol to a link partner that the partner can respo...

Page 128: ...r sends a Packet not accepted General Error Link Request Input Status control symbol To cause the transmission of the required control symbol write the value 0x40FC8000 to the RapidIO Port x Control S...

Page 129: ...any of the illegal transaction maximum retry lookup table parity error or time to live events occur regardless of whether they are enabled or not When most of the errors listed in Table 14 occur they...

Page 130: ...received not the packet that was retried Yes Received corrupt control symbol Received a control symbol with a bad CRC value The status of this error is contained in the CS_CRC_ERR bit in the RapidIO P...

Page 131: ...t does not have a guaranteed delivery and does not have an associated response see RapidIO Interconnect Specification Revision 1 3 Depending on system design a port write can be sent repeatedly until...

Page 132: ...untered the error condition and implementation specific information The layout of the port write packet is shown in the Table 15 on page 133 Port writes are sent at the priority defined in the PW_PRIO...

Page 133: ...s 6 7 and 29 RapidIO Port x Interrupt Status Register on page 318 Correct the error conditions and clear the error sources Clear the PORT_W_PEND bit in the RapidIO Port x Error and Status CSR on page...

Page 134: ...destinationID of the port write packet that is contained in the RapidIO Port Write Target Device ID CSR is also contained in a multicast group the port write will be routed to the multicast engine The...

Page 135: ...SP_CTL_INDEP OUTPUT_DEG bit 7 SP_ERR_STATUS OUTPUT_FAIL bit 6 SP_ERR_STATUS TEA bit 31 SP_INT_STATUS TEA_EN bit 31 SP_CTL_INDEP MCT_TEA bit 13 SP_INT_STATUS MCT_TEA_EN bit 13 SP_CTL_INDEP LINK_INIT_N...

Page 136: ...s not associated with any port Two functions that are port specific have separate indicator bits to allow for faster handling These functions are Multicast Event Control Symbol reception and reception...

Page 137: ...or and Status Register Status Status Bit Further Information Interrupt Enable Interrupt Clearing OUTPUT_DROP RIO Serial Port x Control CSR RIO Port x Error Rate CSR RIO Port x Error Rate Threshold CSR...

Page 138: ...ontrol Independent Register on page 311 controls whether any enabled interrupts are propagated to the Global Interrupt Status Register on page 377 to generate an interrupt If the IRQ_EN bit is disable...

Page 139: ...slave serial interface that can be used for the following purposes Initializing device registers from an EEPROM after reset Reading and writing external devices on the I2 C bus Reading and writing Tsi...

Page 140: ...r by software configuration Provides mailbox registers for communicating between maintenance software operating on RapidIO based processors and external I2 C masters Supports I2 C operations up to 100...

Page 141: ...nsmitted from one device to another across the I2C_SD bus with timing referenced to the I2C_SCLK bus With some exceptions each bus can be driven low to a logic 0 by any device but is pulled high to a...

Page 142: ...static signals from outside the block or connect to package pins for board level configuration The I2C_MA pin is a power up configuration pin that is latched during reset On the core side the I2C blo...

Page 143: ...ternal I2C Device External I2C Device I2C_SD I2C_SCLK Master Interface Digital Filter Digital Filter Boot Load Sequencer Slave Interface Internal Register Bus Master Externally Visible Registers Event...

Page 144: ...Rd 1 Slave Address Data Read from Device ReadData P R Restart loops to start of slave address sequence Stop ends the transaction bus is idle A Byte A Byte A Byte K A A K A A A A A N I2 C Write Data P...

Page 145: ...protocol used by memory oriented devices such as EEPROMs involves the master sending one or more bytes of memory address to the slave to position the slave s memory address or peripheral address then...

Page 146: ...rom I2C_MST_WDATA P S PerAdrMsb PerAdrLsb ReadData 7 Bit SlvAdr Wr 0 Slave Address Peripheral Address Data Read from Device ReadData A A A A A ReadData ReadData N A Arbitration Loss pa_size 2 pa_size...

Page 147: ...ROM This example is configured in the context of register writes that must be made during a boot load of the EEPROM 7 4 1 1 Write Example Write 8 bytes to the EEPROM w 1d114 0x0042FFFF load the write...

Page 148: ...Enable Register In this case the transaction is not automatically retried and it is up to software to retry if needed 7 4 5 Master Peripheral Addressing Some devices such as EEPROMs require a peripher...

Page 149: ...MA_OK of the I2C Interrupt Enable Register 7 5 Tsi574 as I2 C Slave The Tsi574 can operate as a slave device on the I2C bus An external master device places a transaction on the bus with a device add...

Page 150: ...ress space In addition either the SA_WRITE or SA_READ interrupt status is updated in the I2 C Interrupt Status Register if a read or write to the internal register space was triggered by the access An...

Page 151: ...e bytes no defined limit Write Transaction Matched to SLV_ADDR Sets SLV_PA Data Written to Peripheral Space P R ReadData ReadData A A ReadData N Read Transaction Setting Peripheral Address Readdress f...

Page 152: ...f 256 bytes from 0x00 to 0xFF that can be directly read and written by an external I2C master device When an external master sets the peripheral address this sets a pointer viewable in the SLV_PA fiel...

Page 153: ...R W EXI2C_REG_WDATA Specifies the data to write to the internal register address held in EXI2C_REG_WADDR Side effects When address 0x07 the MSB is written the data in this register is written to the i...

Page 154: ...ng mailboxes and on the state of the alert response flag 0x24 0x27 R W EXI2C_ACC_CNTRL Provides control information on how the Tsi574 handles internal register accesses through the EXI2C_REG_RDATA and...

Page 155: ...gister read operation is completed the data is first loaded into the Externally Visible I2C Internal Read Data Register then returned to the external I2C master byte by byte The Externally Visible I2C...

Page 156: ...transactions The following conditions pre exist ALERT_FLAG is set in the Externally Visible I2C Slave Access Status Register 1 External device reads Externally Visible I2C Slave Access Status Register...

Page 157: ...2 C Slave Access Status Register then does another Alert Response request The ALERT_FLAG is zero all enables were cleared so the alert response address is NACKed I2 C Sequence S SLVA W PA 0x84 A WD 0x...

Page 158: ...tic Timer I2C_BOOT_DIAG_TIMER is 0x8000BBCC reserved fields stay zero and interrupt status SA_OK and SA_WRITE assert An optional interrupt can also be sent to the Interrupt Controller if enabled in th...

Page 159: ...lly Visible I2 C Internal Read Address Register is0x001D354 and interrupt status SA_OK and SA_READ assert An optional interrupt can also be sent to the Interrupt Controller if enabled in SA_OK and SA_...

Page 160: ...registers are discussed further in the following sections EXI2C_MBOX_IN Writes to Mailbox 0100 000111 EXI2C_MBOX_IN EXTERNAL I2 C MASTER Flag Goes Up EXI2C_ACC_STAT IMB_FLAG Host is Interrupted IMB_F...

Page 161: ...ternally Visible I2C Slave Access Status Register which the external I2C master can poll through the slave interface When the flag goes up 1 the external I2 C master reads the outgoing mailbox registe...

Page 162: ...col as a SMBus host device in slave mode 7 7 2 SMBus Protocol Support The Tsi574 master interface functionality supports a subset of the SMBus Protocols see Figure 34 In all cases the Tsi574 masters a...

Page 163: ..._SIZE 0 SIZE 0 WRITE 0 SMBus Write Byte PA_SIZE 1 SIZE 1 DORDER 1 WRITE 1 SMBus Write Word PA_SIZE 1 SIZE 2 DORDER 1 WRITE 1 SMBus Read Byte PA_SIZE 1 SIZE 1 DORDER 1 WRITE 0 SMBus Read Word PA_SIZE 1...

Page 164: ...see Power up Options in this document This data initializes the Tsi574 s internal registers The boot load sequence occurs only after a full chip reset and follows the steps shown in Figure 36 The boo...

Page 165: ...Info Per Address Select next device Boot Init and Device Detect Set Register Count Peripheral Address Read Register Count from the first 2 bytes of the EEPROM after reset Set Register Info Peripheral...

Page 166: ...al low preventing the generation of a STOP or START condition To try to force these devices out of their hung state the Tsi574 allows the I2C_SD signal to stay high and generate 9 clock pulses on the...

Page 167: ...pt status is updated in the I2C Interrupt Status Register On these boot load status bits the optional interrupt can be forwarded to the Interrupt Controller if enabled in the I2C Interrupt Enable Regi...

Page 168: ...gister It may also be necessary to use the BOOT_UNLK field to change the lower 2 bits of the EEPROM address By default the BOOT_UNLK field is not set so if the BOOT_ADDR field is changed the lower 2 b...

Page 169: ...er Transmit Data Register at internal address 0x1D114 loaded with data value 0x0506_0708 Table 18 Format for Boot Loadable EEPROM PerAdr PerAdr 0 PerAdr 1 PerAdr 2 PerAdr 3 0x0 RegCnt MSB RegCnt LSB 0...

Page 170: ...haining operations The clocking speeds of the master devices Because many of these parameters are outside the control of the Tsi574 the boot time cannot be predicted with complete accuracy Table 20 Sa...

Page 171: ...ime is a design concern the following techniques may accelerate the boot load sequence 1 If the EEPROM supports reading of a large block of data sequentially change PAGE_MODE in I2C Boot Control Regis...

Page 172: ...d or write access during slave address phase or peripheral address phase or any write access during the data phase Access aborted STOP generated The I2C_ACC_STAT register indicates where transaction w...

Page 173: ...and another device holds the signal to 0 Slave releases I2C_SD and I2C_SCLK goes into wait state SA_FAIL SCOL Register Initialization Loader Errors Failed to find EEPROM Initialization read Read opera...

Page 174: ...t Generation The interrupt status bits are cleared by a write one to clear operation to the Interrupt Status Register provided the interrupt status register has first been read For test purposes bits...

Page 175: ...tatus bit The combined event state becomes the interrupt status bit in the Interrupt Status Register and is then anded with the corresponding enable in the I2C Interrupt Enable Register All the enable...

Page 176: ...FULL Incoming Mailbox Full IMBW Incoming Mailbox Write Event BL_FAIL Boot Load Fail BLTO Boot Load Timeout Error BLERR Boot Load Error Event BLSZ Boot Load Size Error Event BLNOD Boot Load No Device E...

Page 177: ...to their monitor for bus idle phase It is up to software to decide how to handle this error Because any operation was aborted without correct termination no Stop it is possible that the external devi...

Page 178: ...plete If an ACK or NACK is successfully received the master continues as if the timeout had not expired If another I2 C master collides with Slave Address the timeout immediately takes effect followin...

Page 179: ...has not completed in a reasonable time This could occur if the EEPROM was improperly programmed with an infinite chaining loop the bus ownership is held by some other device or some other anomalous si...

Page 180: ...ion Timeout Master or Slave PerAdr or Data A N R P Wait for Bus Idle S Boot Adr A N W Boot Timeout Master Only Load Regs P Idle Detect EEPROM Reset Chain Load Regs START PerAdr P From SCL sampled low...

Page 181: ...e not guaranteed to conform to the I2C Specification because of the absence of Schmitt triggers on the input of the I2C_SD and I2C_SCLK signals and the absence of slope controlled outputs for the I2C_...

Page 182: ...ams I2C_SCLK START RESTART Condition Setup I2C_SD Hold I2C_SCLK STOP Condition Setup I2C_SD I2C_SCLK I2C_SD Data Bit or Ack Nack Setup I2C_SD Hold SCL Minimum Low I2C_SCLK High Low Minimum High Nomina...

Page 183: ...re is no separate Stop Hold parameter as the only valid condition following a Stop would be a Start therefore the Start Setup fulfills the same use as a Stop Hold or Stop to Start buffer time This par...

Page 184: ...the low period than the nominal low period the high period nominal timer will likely expire early and the minimum high period timer will control the high period when the clock is finally released 7 1...

Page 185: ...fied for a single switch Performance for larger systems can be computed from this data 8 1 1 Throughput Throughput for packets is a measurement of the amount of packet data that can be transferred in...

Page 186: ...ency figure that each packet experiences difficult because the amount of contention that a packet experiences can vary widely As such these scenarios are not covered in this manual Figure 41 Latency I...

Page 187: ...rformance Statistics Counter 0 and 1 Control Register on page 324 RapidIO Port x Performance Statistics Counter 0 Register on page 336 Any of the performance statistics counter registers can be config...

Page 188: ...ket size is COUNTER A divided by the value in COUNTER B 3 Utilization packet rate packet size max capacity Utilization is calculated using parameter 1 and parameter 2 above These values are derived fr...

Page 189: ...Register on page 344 RapidIO Port x Transmitter Output Queue Congestion Period Register on page 346 The registers in the inbound direction are RapidIO Port x Receiver Input Queue Depth Threshold Regis...

Page 190: ...t the lower the throughput the higher the average latency and the greater the spread between minimum and maximum latency For ports operating in 1x mode performance measurements are specified for opera...

Page 191: ...pidIO egress buffer management For high priority configurations watermark settings should be used which deliver maximal throughput for the highest priority packets For ingress and egress ports a maxim...

Page 192: ...intain the line rates This means there is no retry of packets at the ingress ports and no bubbles will appear in the egress packet stream except for the idle sequence insertion every 5000 code groups...

Page 193: ...ance Under a non congested one port to many ports packet traffic scenario when the ingress line rate is the same as the total egress line rates for example one 4x mode 3 125 Gbaud ingress port splitti...

Page 194: ...st engine retries occur at the ingress port In this situation the egress port maintains its line rate For example when an egress port is set to 4x mode 2 5 Gbaud while the multicast engine is receivin...

Page 195: ...er by 1 Yes No Leak Rate timer expire Congestion Period timer expire Yes Yes No No Increment Congestion Period Counter by 1 Yes No Clear Congestion Period Counter Congestion Period Counter read by sof...

Page 196: ...CONG_PERIOD_CTR This is the Congestion Period Counter This counter is incremented at every tick whose period is set by the CONG_PERIOD field when the Congestion Counter is greater than zero This regis...

Page 197: ...status Both interrupts are located in the RapidIO Port x Interrupt Status Register on page 318 for the port The Congestion Counter and Congestion Period Counter fields must be polled in order to dete...

Page 198: ...ion Period Count value see RapidIO Port x Transmitter Output Queue Depth Threshold Register on page 342 and the Congestion Counter value see RapidIO Port x Transmitter Output Queue Congestion Status R...

Page 199: ...re are five standard pins associated with the interface TMS TCK TDI TDO and TRST_b which allow full control of the internal TAP Test Access Port controller The JTAG Interface has the following feature...

Page 200: ...ing down the normal traffic in the device or during initialization A user defined command is used to enable the read and write capabilities of the interface The command is in the IEEE 1149 1 Instructi...

Page 201: ...at are being shifted out as the first two bits shifted out 5 Go back to step two to perform another write 9 3 3 Read Access to Registers from the JTAG Interface The following steps are required in ord...

Page 202: ...9 JTAG Interface JTAG Register Access Details 202 Tsi574 User Manual June 6 2016 Integrated Device Technology www idt com...

Page 203: ...ation Clocks on page 203 Resets on page 207 Power up Options on page 210 10 1 Clocks The Tsi574 has three input clocks S_CLK_p n P_CLK and I2C_SCLK that are used to produce the Tsi574 s internal clock...

Page 204: ...r one RXCLKA or two RXCLKA B clocks are recovered On the transmit side the clock TX_CLK is derived from the SerDes An extra clock SYS_CLK is also sourced from the SerDes to the MAC The S_CLK_p n signa...

Page 205: ...1 3 Reference clocks The two reference clocks are described in Table 26 Tip For information on configuring the clock rate of RapidIO ports refer to Clocking on page 69 Table 26 Tsi574 Input Reference...

Page 206: ...o P_CLK Programming on page 479 100 MHz This clock domain includes all internal registers within each of the internal blocks as well as the bus that performs the register accesses The domain uses the...

Page 207: ...ble for performing automatic reads from an externally attached EEPROM device in order to load the initial configuration of the device For more details refer to I2C Interface on page 139 10 2 1 2 HARD_...

Page 208: ...tion of the self reset which is at least four P_CLK clock cycles If the SELF_RST field is not set an interrupt signal is asserted if RCS_INT_EN is also set in the RapidIO Port x Mode CSR on page 302 S...

Page 209: ...device is dropped and any traffic still in flight to the peer device is dropped 4 Use the RapidIO Serial Port x Link Maintenance Request CSR on page 265 to transmit four reset control symbols in a row...

Page 210: ...wer down SPn_PWRDN mode selection SPn_MODESEL lane swap SP_RX_SWAP and SP_TX_SWAP and I2 C pins I2c_DISABLE I2C_MA I2C_SA 1 0 I2C_SEL 10 3 1 Power up Option Signals Power up options are latched at res...

Page 211: ...put capability of this pin is only used in test mode SP n _PWRDN Port n Transmit and Receive Power Down Control This signal controls the state of Port n and Port n 1 The PWRDN controls the state of al...

Page 212: ...when driven low single byte peripheral address is assumed I2C_SA 1 0 I2 C Slave Address pins The values on these two pins represent the values for the lower 2 bits of the 7 bit address of Tsi574 when...

Page 213: ...fix _p are the positive half of a differential pair Signals with the suffix _n are the negative half of a differential pair Signals with the suffix _b are active low Signals are classified according t...

Page 214: ...s These port numbers are used within the destination ID lookup tables for ingress RapidIO ports and in numerous register configuration fields 11 4 Signal Groupings Core Power Core supply Core Ground G...

Page 215: ...inverting Transmit Data output 4x mode Port n 1 Lane B Differential Non inverting Transmit Data output 1x mode No termination required SP n _TB_n O SRIO Port n Lane B Differential Inverting Transmit D...

Page 216: ..._p I SRIO Port n Lane D Differential Non inverting Receive Data input 4x mode DC blocking capacitor of 0 1uF in series SP n _RD_n I SRIO Port n Lane D Differential Inverting Receive Data input 4x mode...

Page 217: ...configuration Either a 10K pull up to VDD_IO or a 10K pull down to VSS_IO Internal pull up can be used for logic 1 SP n 1 _PWRDN I O LVTTL PU Port n 1 Transmit and Receive Power Down Control This sign...

Page 218: ...er to be sampled correctly These signals are ignored after reset and software is able to over ride the port frequency setting in the SRIO MAC x Digital Loopback and Clock Selection Register on page 36...

Page 219: ...SWAP I LVTTL PD Configures the order of 4x transmit lanes on serial ports 0 A B C D 1 D C B A Must remain stable for 10 P_CLK cycles after HARD_RST_b is de asserted in order to be sampled correctly Th...

Page 220: ...RapidIO link If self reset is not selected this pin remains asserted until the reset request is cleared from the status registers If self reset is selected this pin remains asserted until the self re...

Page 221: ...signal does not control the slave accessibility of the interface This signal is ignored after reset No termination required Pull up to VDD_IO through a 10K resistor if I2 C loading is not required I2C...

Page 222: ...utput No connect if JTAG is not used Pull up to VDD_IO through a 10K resistor if used TMS I LVTTL PU IEEE 1149 1 1149 6 Test Access Port Test Mode Select Pull up to VDD_IO through a 10K resistor if no...

Page 223: ...Manual for more information Common Supply VDD_IO Common 3 3V supply for LVTTL I O Refer to decoupling recommendations in the Tsi574 Hardware Manual for more information VSS Common ground returns for d...

Page 224: ...11 Signals Pinlist and Ballmap 224 Tsi574 User Manual June 6 2016 Integrated Device Technology www idt com...

Page 225: ...egisters on page 372 Utility Unit Registers on page 377 Multicast Registers on page 383 SerDes Per Lane Register on page 390 12 1 Overview The application defined Tsi574 registers receive initial valu...

Page 226: ...8 to 13 2 a read modify write operation must be performed for register reserved fields that have an undefined reset value Other reserved fields should always be written as 0 unless otherwise noted Ta...

Page 227: ...TID S2_DESTID and so on In the second notation the names of the instances are explicitly listed For example S BC 0 2 _DESTID refers to registers SBC_DESTID S0_DESTID S1_DESTID and S2_DESTID Generally...

Page 228: ...Extension Registers on page 277 0x01000 0x0143C Reserved 0x014C0 0x0FFFF IDT Specific RapidIO Registers on page 299 and Serial Port Electrical Layer Registers 0x10000 0x14FFC Reserved 0x15000 0x1A9FC...

Page 229: ...ch Multicast Support CAR on page 248 00034 RIO_LUT_SIZE RapidIO Route LUT Size CAR on page 249 00038 RIO_SW_MC_INFO RapidIO Switch Multicast Information CAR on page 250 0003C 00064 Reserved 00068 RIO_...

Page 230: ...onse CSR on page 267 00148 SP0_ACKID_STAT RapidIO Serial Port x Local ackID Status CSR on page 268 0014C 00154 Reserved 00158 SP0_ERR_STATUS RapidIO Port x Error and Status CSR on page 270 0015C SP0_C...

Page 231: ..._DET RapidIO Port x Error Detect CSR on page 286 01044 SP0_RATE_EN RapidIO Port x Error Rate Enable CSR on page 289 01048 SP0_ERR_ATTR_CAPT_DBG0 RapidIO Port x Error Capture Attributes CSR and Debug 0...

Page 232: ...page 301 10004 SPBC_MODE RapidIO Port x Mode CSR on page 302 10008 SPBC_CS_INT_STATUS RapidIO Port x Multicast Event Control Symbol and Reset Control Symbol Interrupt CSR on page 304 1000C SPBC_RIO_W...

Page 233: ...Reserved 1300C SP0_SEND_MCS RapidIO Port x Send Multicast Event Control Symbol Register on page 314 13010 SP0_LUT_PAR_ERR_INFO RapidIO Port x LUT Parity Error Info CSR on page 315 13014 SP0_CS_TX Rap...

Page 234: ...age 344 13088 SP0_TX_Q_PERIOD RapidIO Port x Transmitter Output Queue Congestion Period Register on page 346 1308C Reserved 13090 SP0_RX_Q_D_THRESH RapidIO Port x Receiver Input Queue Depth Threshold...

Page 235: ...registers as for SP0 offsets 0x13000 0x130AC The registers at offsets 0x130B0 0x130FC are excluded 13600 136FC Serial Port 6 All registers as for SP0 offsets 0x13000 0x130FC 13700 137AC Serial Port 7...

Page 236: ...er Unicast and Multicast Packet Prio 1 Register on page 387 1B018 SP0_WRR_2 Port x Prefer Unicast and Multicast Packet Prio 2 Register on page 388 1B01C SP0_WRR_3 Port x Prefer Unicast and Multicast P...

Page 237: ...gister on page 396 1E074 SMAC 0 2 4 6 _FP_VAL_1 SerDes Lane 1 Frequency and Phase Value Register on page 400 1E078 1E07C Reserved 1E0A0 SMAC 0 2 4 6 _PG_CTL_2 SerDes Lane 2 Pattern Generator Control R...

Page 238: ...registers are organized and accessed in the same way as the CARs All of the registers in this section are defined in the RapidIO Interconnect Specification Revision 1 3 These registers are reset by th...

Page 239: ...egister name RIO_DEV_ID Reset value 0x0574_000D Register offset 00000 Bits 0 1 2 3 4 5 6 7 00 7 DEV_ID 07 15 DEV_ID 16 23 DEV_VEN_ID 24 31 DEV_VEN_ID Bits Name Description Type Reset Value 0 15 DEV_ID...

Page 240: ...ue 0x0000_0020 Register offset 00004 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 SILICON_REV METAL_REV Bits Name Description Type Reset Value 0 23 Reserved N A R 0 24 27 SI...

Page 241: ...O_ASBLY_ID Reset value 0x0001_000D Register offset 00008 Bits 0 1 2 3 4 5 6 7 00 07 ASBLY_ID 08 15 ASBLY_ID 16 23 ASBLY_VEN_ID 24 31 ASBLY_VEN_ID Bits Name Description Type Reset Value 0 15 ASBLY_ID A...

Page 242: ...SBLY_INFO Reset value 0x0000_0100 Register offset 0000C Bits 0 1 2 3 4 5 6 7 00 07 ASBLY_REV 08 15 ASBLY_REV 16 23 EXT_FEAT_PTR 24 31 EXT_FEAT_PTR Bits Name Description Type Reset Value 0 15 ASBLY_REV...

Page 243: ...reads and writes 1 The processing element has physically addressable local address space and can be accessed as an endpoint through non maintenance that is NREAD and NWRITE transactions R 0 2 PROC Pro...

Page 244: ...guration of the ingress port s lookup table This bit is not used in the control of any functionality in the Tsi574 0 Device supports 8 bit destination IDs only 1 Device supports 8 bit and 16 bit desti...

Page 245: ...Reserved 16 23 PORT_TOTAL 24 31 PORT_NUM Bits Name Description Type Reset Value 0 15 Reserved N A R 0x0000 16 23 PORT_TOTAL Port Total The total number of RapidIO ports on the device Note that the num...

Page 246: ...15 Reserved IMPLEMENT_DEF 16 23 READ WRITE STRM_WR WR_RES D_MSG DBELL Reserved A_TSWAP 24 31 A_INC A_DEC A_SET A_CLEAR Reserved PORT_WR Reserved Bits Name Description Type Reset Value 0 13 Reserved N...

Page 247: ...sters 247 Tsi574 User Manual June 6 2016 Integrated Device Technology www idt com 29 PORT_WR Port write operation The RapidIO ports support port write generation to report errors R 1 30 31 Reserved Im...

Page 248: ...oes not support the simple programming model for more information see the RapidIO Multicast Mask Configuration Register on page 256 Register name RIO_PE_MC_FEAT Reset value 0x0000_0000 Register offset...

Page 249: ...ination IDs with limited capabilities Register name RIO_LUT_SIZE Reset value 0x0000_01FF Register offset 0034 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 LUT_SIZE 0 7 24 31 LUT_SIZE 8 15...

Page 250: ...te write is required per association between a destinationID and a multicast mask 1 Block association is supported Not implemented in the Tsi574 R 0 1 ASSOC_SCOPE Defines the capabilities of a switch...

Page 251: ...FFF Note that writing 0xFFFF to this register does not result in a lock being obtained After writing the HOST_BASE_ID field a processing element must read the Host Base Device ID Lock CSR to verify th...

Page 252: ...dIO Component Tag CSR This register is written by software It is used for labeling and identifying the port write transactions to the host Register name RIO_COMP_TAG Reset value 0x0000_0000 Register o...

Page 253: ...per port configuration registers and they include an auto increment bit to increment the contents of SPx_ROUTE_CFG_DESTID after a read or write operation For details on how to configure the LUTs usin...

Page 254: ...ion registers and they include an auto increment bit to increment the contents of SPx_ROUTE_CFG_DESTID after a read or write operation For details on how to configure the LUTs using this register refe...

Page 255: ...078 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 DEFAULT_PORT Bits Name Description Type Reset Value 0 23 Reserved Reserved R 0 24 31 DEFAULT_ PORT Default Output Port All t...

Page 256: ...cription Type Reset Value 0 15 MC_MASK_NUM Specifies the multicast mask 0 7 which is to be modified when this register is written with the MASK_CMD field set to Add or Delete 0x0000 to 0x0007 Specifie...

Page 257: ...Multicast Mask 010 Delete the given Egress_Port_Number from the specified Multicast Mask 011 Reserved 100 Delete all egress ports from the specified Multicast Mask 101 Add all egress ports to the spec...

Page 258: ...ed Register name RIO_MC_DESTID_CFG Reset value 0x0000_0000 Register offset 00084 Bits 0 1 2 3 4 5 6 7 00 07 DESTID_BASE_LT 7 0 08 15 DESTID_BASE 7 0 16 23 MASK_NUM_BASE 15 8 24 31 MASK_NUM_BASE 7 0 Bi...

Page 259: ...ulticast mask or which association must be removed Register name RIO_MC_DESTID_ASSOC Reset value 0x0000_0000 Register offset 00088 Bits 0 1 2 3 4 5 6 7 00 07 ASSOC_BLK_SIZE 08 15 ASSOC_BLK_SIZE 16 23...

Page 260: ...on Register 11 Add Associations This register write adds associations between a destination ID and multicast mask number The multicast mask number and destination ID are specified by a prior write to...

Page 261: ...and some read only fields using the I2 C register loading capability on boot Refer to I2 C Interface on page 139 for more information on the use of I2 C controller register loading capability Reads t...

Page 262: ...block header information Register name RIO_SW_MB_HEAD Reset value 0x1000_0009 Register offset 100 Bits 0 1 2 3 4 5 6 7 00 07 EF_PTR 08 15 EF_PTR 16 23 EF_ID 24 31 EF_ID Bits Name Description Type Res...

Page 263: ...f 100 MHz When Link Time Out is expired the port enters the Output Error state as outlined in the RapidIO Interconnect Specification Revision 1 3 Register name RIO_SW_LT_CTL Reset value 0xFFFF_FF00 Re...

Page 264: ...le through the Port General Control CSR of any other physical layer implemented on a device Register name RIO_SW_GEN_CTL Reset value 0x0000_0000 Register offset 13C Bits 0 1 2 3 4 5 6 7 00 07 Reserved...

Page 265: ...est and if that request is outstanding and the CMD field is written to then the register write is ignored If this register is written twice in rapid succession it could cause a protocol violation If t...

Page 266: ...cal Layer Registers 266 Tsi574 User Manual June 6 2016 Integrated Device Technology www idt com Writing to this register on a port in normal operation affects traffic on that port This register should...

Page 267: ...Name Description Type Reset Value 0 RESP_VLD Response Valid 0 No link response control symbol received or no link request reset transmitted 1 If the link request was a link request input status this b...

Page 268: ...ement error recovery Note The INBOUND value can be initialized through the I2 C Interface Initializing the INBOUND value from I2 C is required for test purposes only Unless the INBOUND value is initia...

Page 269: ...his register is being processed the OUTBOUND value is not used for the next packet transmitted The new OUTBOUND value is always used when the port is operating normally and when the port is in an erro...

Page 270: ...PORT_ UNINIT Bits Name Description Type Reset Value 0 4 Reserved N A R 0 5 OUTPUT_DROP Output port has discarded a packet The packet is dropped when the Error Rate Threshold is reached when the time t...

Page 271: ...sibly recovered from a transmission error This bit is set when the Output Error stopped bit bit 15 is set R W1C 0 15 OUTPUT_ERR_ STOP Output Error stopped Outbound port is in the output error stopped...

Page 272: ...able to recover fatal error The following fatal errors cause a PORT_ERR Four link request tries with link response but no outstanding ackID Four link request tries with time out error for link respons...

Page 273: ...KOUT PORT_TYP E Bits Name Description Type Reset Value 0 1 PORT_WIDTH Port Width This field displays the port mode after reset 00 Single lane port the port is 1x mode only 01 Four lane port the port h...

Page 274: ...ependent Register on page 311 register Note Initial port width of the port is set by SPx_MODESEL pins at power up After reset release the SPx_MODESEL pins are ignored and configuration is controlled b...

Page 275: ...control symbols out this port R W 0 13 Reserved N A R 0 14 ENUM_B Enumeration boundary bit used in system discovery algorithms This bit does not control any functionality within the Tsi574 The reset v...

Page 276: ...orce the sending device to signal an error condition The receipt of a packet by the locked out port causes the assertion of the INPUT_ERR and INPUT_ERR_STOP bits in its RapidIO Port x Error and Status...

Page 277: ...for more information on the use of I2C controller register loading capability The Logical Transport Error Detect registers are not required for a switch However a switch s register bus access errors...

Page 278: ...s set and or if the Error Rate Failed threshold has been met or exceeded 0 1 The port discards packets that receive a Packet not accepted control symbol when the Error Rate Failed Threshold has been m...

Page 279: ...gement Extensions registers in the Tsi574 Register name RIO_ERR_RPT_BH Reset value 0x0000_0007 Register offset 1000 Bits 0 1 2 3 4 5 6 7 00 07 EF_PTR 08 15 EF_PTR 16 23 EF_ID 24 31 EF_ID Bits Name Des...

Page 280: ...No other packets reach the logical layer of a switch Register name RIO_LOG_ERR_DET Reset value 0x0000_0000 Register offset 1008 Bits 0 1 2 3 4 5 6 7 00 07 Reserved L_ILL_TRA NS Reserved 08 15 L_ILL_RE...

Page 281: ...rrupts can be generated for these sources No other packets reach the logical layer of a switch Register name RIO_LOG_ERR_DET_EN Reset value 0x0000_0000 Register offset 100C Bits 0 1 2 3 4 5 6 7 00 07...

Page 282: ...ta can be captured in this register for erroneous port writes and maintenance responses as these transactions reserve the address field If the TT code for an erroneous maintenance request is invalid t...

Page 283: ...t received For switches the errors detected are limited to maintenance packets maintenance requests maintenance responses and port writes with a hop count of 0 No other packets can reach the logical l...

Page 284: ...ing the FTYPE field in the packet Note that for switches the errors detected are limited to maintenance packets maintenance requests maintenance responses and port writes with a hop count of 0 No othe...

Page 285: ...its 0 1 2 3 4 5 6 7 00 07 DESTID_MSB 08 15 DESTID_LSB 16 23 LARGE_ DESTID Reserved 24 31 Reserved Bits Name Description Type Reset Value 0 7 DESTID_MSB Most Significant Byte of port write Target Devic...

Page 286: ...Enable CSR on page 289 When the threshold is reached hardware informs the system software of the error using its standard error reporting function After the error has been reported the system softwar...

Page 287: ...TEA MC_TEA LUT_PAR_ERR ILL_TRANS_ERR Caution The Error Capture register information is only valid for Reserved Transport Type Detected errors and Unmapped DestID errors For the Max Retry errors the in...

Page 288: ...a packet accepted control symbol for it and has moved to the next ACK_ID value This value can be found in the RapidIO Serial Port x Local ackID Status CSR on page 268 Therefore an ACK_ID mismatch has...

Page 289: ...1 2 3 4 5 6 7 00 07 IMP_SPEC _ERR Reserved 08 15 Reserved CS_CRC_E RR_EN CS_ILL_ID _EN CS_NOT_A CC_EN PKT_ILL_A CKID_EN PKT_CRC_ ERR_EN PKT_ILL_S IZE_EN Reserved 16 23 Reserved 24 31 Reserved LR_ ACK...

Page 290: ...bytes R W 0 15 25 Reserved N A R 0 26 LR_ACKID_ILL_ EN Enable error rate counting A received Link Response control symbol contains an ackID that is not outstanding R W 0 27 PROT_ERR_EN Enable error ra...

Page 291: ...ved 16 23 Reserved 24 31 Reserved VAL_CAPT Bits Name Description Type Reset Value 0 1 INFO_TYPE Type of information logged 00 Packet 01 Control Symbol and unaligned SC or PD or undefined code group 10...

Page 292: ...t Error No 00001 to 00111 Bit 1 8 Reserved 01000 Bit 9 CS_CRC_ERR Control Symbol CRC Error Yes 01001 Bit 10 CS_ILL_ID Control Symbol Illegal ID Yes 01011 Bit 11 CS_NOT_ACC Control Symbol Not Accepted...

Page 293: ...ebug of the system error recovery and threshold function the RapidIO Port x Error Detect CSR on page 286 and the Port x Error Capture registers are also writable Software must clear the Capture Valid...

Page 294: ...0000 Register offset 1050 1090 10D0 1110 1150 1190 11D0 1210 Bits 0 1 2 3 4 5 6 7 00 7 CAPT_1 0 7 8 15 CAPT_1 8 15 16 23 CAPT_1 16 23 24 31 CAPT_1 24 31 Bits Name Description Type Reset Value 0 31 CAP...

Page 295: ...7 15 RapidIO Port x Packet Error Capture CSR 3 and Debug 4 Register name SP 0 7 _ERR_CAPT_3_DBG4 Reset value 0x0000_0000 Register offset 1058 1098 10D8 1118 1158 1198 11D8 1218 Bits 0 1 2 3 4 5 6 7 0...

Page 296: ...ate Bias value Register bus frequency 100 MHz 00 Do not decrement error rate counter 01 Decrement every 1 31ms 02 Decrement every 10 48ms 04 Decrement every 83 88ms 08 Decrement every 1 342s 10 Decrem...

Page 297: ...rt This number is decremented by the Error Rate Bias function The counter cannot over or underflow and continue to increment or decrement as defined even if thresholds are met Software can reset this...

Page 298: ...Reserved Bits Name Description Type Reset Value 0 7 ERR_RFT Error Rate Failed Threshold These bits provide the threshold value for reporting an error condition due to a possibly broken link 00 Disabl...

Page 299: ...et values of writable fields and some read only fields using the I2C register loading capability on boot Refer to I2 C Interface on page 139 for more information on the use of I2 C controller register...

Page 300: ...y the RapidIO Interconnect Specification Revision 1 3 It is not possible to broadcast to these registers Table 42 IDT Specific Per Port Performance Registers Port Register Offset Description SP0 13000...

Page 301: ...ERY_ TIMER Discovery Timer This field is used by serial ports configured to operate in 4x mode The discovery timer allows time for the link partner to enter its discovery state and if the link partner...

Page 302: ...iption Type Reset Value 0 1 Reserved N A R 0 2 IDLE_ERR_DIS Idle Error Checking Disable 0 Error checking is enabled by default if one or more data characters are sent Dx y characters not delimited wit...

Page 303: ...f 256 destination IDs 1 One 512 entry local LUT R W 1 8 29 Reserved N A R 0 30 MCS_INT_EN Multicast Event Control Symbol Interrupt Enable 0 Disabled 1 Enabled The interrupt signal is high when the mul...

Page 304: ...s whether a multicast event control symbol has been received on the port Reading the MCS field using the BC offset gives the value of Port 0 All MCS interrupts from ports are ORed together The Global...

Page 305: ...packets are accepted if the number of free buffer is greater than this value This value must be smaller than PRIO1WM Note It is a programming error for this value to be either greater than or equal t...

Page 306: ...ID 8 15 Bits Name Description Type Reset Value 0 AUTO_INC Automatically post increment the destination ID when the destination ID is used to perform either a read or a write through the RapidIO Port x...

Page 307: ...ter a read or write operation Register name SP BC 0 7 _ROUTE_CFG_PORT Reset value Undefined Register offset 10074 11074 11174 11274 11374 11474 11574 11674 11774 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08...

Page 308: ...SP BC 0 7 _ROUTE_BASE Reset value 0x0000_0000 Register offset 10078 11078 11178 11278 11378 11478 11578 11678 11778 Bits 0 1 2 3 4 5 6 7 00 07 BASE 08 15 Reserved 16 23 Reserved 24 31 Reserved Bits N...

Page 309: ...EN LARGE_ SYS Reserved 8 15 Reserved 16 23 MC_ID 15 8 24 31 MC_ID 7 0 Bits Name Description Type Reset Value 0 MC_EN Multicast can be disabled by setting this bit 0 Disabled 1 Enabled R W 0 1 LARGE_ S...

Page 310: ...ent to all egress ports whose multicast select bit is set to 1 However the multicast packet is not sent to the port from which it was received regardless of the setting of that port s multicast select...

Page 311: ...2 SCRATCH Scratch Pad This bit controls no functionality It is a read write scratch pad bit for software use R W 0 3 4 Reserved N A R 0 5 FORCE_REINIT Force Link Re initialization Process This bit is...

Page 312: ...0 14 LINK_INIT_NOTIF ICATION_EN Enables interrupts and port writes for LINK_INIT_NOTIFICATION events 0 Interrupt and or port write disabled 1 Interrupt and or port write enabled R W 0 15 LUT_PAR_ERR_...

Page 313: ...pth Interrupt Enable An interrupt is generated when the OUTB_DEPTH bit is set in the RapidIO Port x Interrupt Status Register on page 318 R W 0 28 INB_DEPTH_EN Input Queue Depth Interrupt Enable An in...

Page 314: ...bound flow There can be only one outstanding request at a time Subsequent requests are ignored until the multicast control symbol is sent Register name SP 0 7 _SEND_MCS Reset value 0x0000_0002 Registe...

Page 315: ...me Description Type Reset Value 0 7 DESTID_MSB Most significant byte of a 16 bit destination ID used in the lookup operation which caused the error Only valid if the LG_DESTID field value is 1 and a L...

Page 316: ...e LUT entry is mapped The PORT_NUM field value is the port to which the packet could be routed 0x0 to 0xF Caution The value of this bit is unpredictable when there is a parity error in the LUT For mor...

Page 317: ...mbol This field uses the parameters PAR_0 and PAR_1 R W 0 3 7 PAR_0 Used in conjunction with stype0 encoding R W 0 8 12 PAR_1 Used in conjunction with stype0 encoding R W 0 13 15 STYPE_1 Encoding for...

Page 318: ...writing a 1 to it or by clearing all bits in the RapidIO Port x Error Detect CSR on page 286 R W1C 0 14 LINK_INIT_ NOTIFICATION Link Initialization Notification Once set the LINK_INIT_NOTIFICATION bit...

Page 319: ...ge 57 Once set the bit remains unchanged until all the error sources are cleared The setting of this bit generates an interrupt if the IRQ_EN bit in RapidIO Port x Control Independent Register on page...

Page 320: ...s set when Reordering Count reaches the maximum number defined in the Inbound Reordering Threshold field in the RapidIO Port x Reordering Counter Register on page 352 To get an interrupt in this statu...

Page 321: ..._GEN Reserved MAX_RET RY_GEN OUTB_DE PTH_GEN INB_DEPT H_GEN INB_RDR_ GEN Reserved TEA_GEN Bits Name Descriptiona Type Reset Value 0 12 Reserved N A R 0 13 MC_TEA_GEN Forces the MC_TEA bit to be set B...

Page 322: ...as zero R W1S 0 30 Reserved Reserved R W1S 0 31 TEA_GEN Forces the TEA bit to be set to 1 This bit always reads as zero R W1S 0 a All bits in this register set clear bits in the RapidIO Port x Interr...

Page 323: ...table shows the IDT specific per port registers not defined by the RapidIO Interconnect Specification Revision 1 3 It is not possible to broadcast to these registers Table 43 IDT Specific Per Port Per...

Page 324: ...er see RapidIO Port x Performance Statistics Counter 0 Register on page 336 and RapidIO Port x Performance Statistics Counter 1 Register on page 337 The SPx_PSCy can be disabled by selecting PSy_PRIO...

Page 325: ...Counter 0 Register on page 336 0 If all PS0_PRIO 0 3 are set to zero the RapidIO Port x Performance Statistics Counter 0 Register on page 336 is disabled 1 Count priority 1 packets R W 0 3 PS0_PRIO0...

Page 326: ...lticast packet including header R W 0 16 PS1_PRIO3 Performance Stats Reg PS1 Priority 3 Selection This value represents the packet priority 3 is selected for which performance stats are accumulated fo...

Page 327: ...rved N A R 0 29 31 PS1_TYPE Performance Stats Reg PS1 Type Selection This value determines the type of performance statistics that is collected in the RapidIO Port x Performance Statistics Counter 1 R...

Page 328: ...rformance Statistics Counter 2 Register on page 338 and RapidIO Port x Performance Statistics Counter 3 Register on page 339 The SPx_PSCy can be disabled by selecting PSy_PRIO 0 3 to be set to 0 Setti...

Page 329: ...rol Register on page 332 0 If all PS2_PRIO 0 3 are set to zero the RapidIO Port x Performance Statistics Counter 4 and 5 Control Register on page 332 is disabled 1 Count priority 1 packets R W 0 3 PS2...

Page 330: ...tire multicast packet including header R W 0 16 PS3_PRIO3 Performance Stats Reg PS3 Priority 3 Selection This value represents the packet priority 3 is selected for which performance stats are accumul...

Page 331: ...rved N A R 0 29 31 PS3_TYPE Performance Stats Reg PS3 Type Selection This value determines the type of performance statistics that is collected in the RapidIO Port x Performance Statistics Counter 3 R...

Page 332: ...pidIO Port x Performance Statistics Counter 4 Register on page 340 and RapidIO Port x Performance Statistics Counter 5 Register on page 341 The SPx_PSCy can be disabled by selecting PSy_PRIO 0 3 to be...

Page 333: ...Counter 4 Register on page 340 0 If all PS4_PRIO 0 3 are set to zero the RapidIO Port x Performance Statistics Counter 4 Register on page 340 is disabled 1 Count priority 1 packets R W 0 3 PS4_PRIO0...

Page 334: ...multicast packet including header R W 0 16 PS5_PRIO3 Performance Stats Reg PS5 Priority 3 Selection This value represents the packet priority 3 is selected for which performance stats are accumulated...

Page 335: ...5 Type Selection This value determines the type of performance statistics that is collected in the RapidIO Port x Performance Statistics Counter 5 Register on page 341 Retries are not counted as part...

Page 336: ...24 The PS0_CTR counter value is writable for testing purposes This counter saturates when it reaches its maximum value 0xFFFFFFFF and is cleared on a read The PS0_CTR is enabled when PS0_PRIO 0 3 valu...

Page 337: ...24 The PS1_CTR counter value is writable for testing purposes This counter saturates when it reaches its maximum value 0xFFFFFFFF and is cleared on a read The PS1_CTR is enabled when PS1_PRIO 0 3 valu...

Page 338: ...register The PS2_CTR counter value is writable for testing purposes This counter saturates when it reaches its maximum value 0xFFFFFFFF and is cleared on a read The PS2_CTR is enabled when PS2_PRIO 0...

Page 339: ...28 The PS3_CTR counter value is writable for testing purposes This counter saturates when it reaches its maximum value 0xFFFFFFFF and is cleared on a read The PS3_CTR is enabled when PS3_PRIO 0 3 valu...

Page 340: ...e PS4_CTR counter value is writable for testing purposes This counter saturates when it reaches its maximum value 0xFFFFFFFF and is cleared on a read The PS4_CTR is enabled when PS4_PRIO 0 3 value in...

Page 341: ...ster register The PS5_CTR counter value is writable for testing purposes This counter saturates when it reaches its maximum value 0xFFFFFFFF and is cleared on a read The PS5_CTR is enabled when PS5_PR...

Page 342: ...80 13480 13580 13680 13780 Bits 0 1 2 3 4 5 6 7 00 7 CONG_PERIOD 8 15 CONG_PERIOD 16 23 DEPTH Reserved LEAK_RT 24 31 LEAK_RT Bits Name Description Type Reset Value 0 15 CONG_PERIOD This value is progr...

Page 343: ...ill reaches or exceeds 3 7 the congestion counter increments when the buffer fill reaches 8 8 Reserved R W 0x0 20 Reserved N A R 0 21 31 LEAK_RT This value is the leak rate for both the receiver and t...

Page 344: ...in the Error Rate Bias frequency as specified by the ERR_RB field in the RapidIO Port x Error Rate CSR on page 296 If the CONG_CTR equals or exceeds the threshold CONG_THRESH the maskable OUTB_DEPTH i...

Page 345: ...CONG_THRESH Output Queue Depth Threshold If the CONG_CTR count is equal to the value in this field an interrupt is reported to the system through the OUTB_DEPTH status bit in the RapidIO Port x Interr...

Page 346: ...ch its maximum value Reading the CONG_PERIOD_CTR clears the counter value The CONG_PERIOD_CTR can be disabled when the CONG_PERIOD field in the RapidIO Port x Transmitter Output Queue Depth Threshold...

Page 347: ...SP 0 7 _RX_Q_D_THRESH Reset value 0x0000_0000 Register offset 13090 13190 13290 13390 13490 13590 13690 13790 Bits 0 1 2 3 4 5 6 7 00 7 CONG_PERIOD 8 15 CONG_PERIOD 16 23 DEPTH Reserved 24 31 Reserved...

Page 348: ...packets in the input queue meets or exceeds this number the congestion counter is incremented 0 Disables congestion monitoring 1 The congestion counter increments when the buffer fill reaches or exce...

Page 349: ...thin the Error Rate Bias frequency as specified by the ERR_RB field in the RapidIO Port x Error Rate CSR on page 296 If the CONG_CTR equals or exceeds the threshold CONG_THRESH the maskable INB_DEPTH...

Page 350: ...CONG_THRESH Input Queue Depth Threshold If the CONG_CTR count is equal to the value in this field an interrupt is reported to the system through the INB_DEPTH status bit in the RapidIO Port x Interru...

Page 351: ...mum value Reading the CONG_PRIOD_CTR clears the register The CONG_PERIOD_CTR can be disabled when the CONG_PERIOD field in the RapidIO Port x Receiver Input Queue Depth Threshold Register is set to 0...

Page 352: ...tatus Register on page 318 Register name SP 0 7 _REORDER_CTR Reset value 0x0000_FFFF Register offset 130A0 131A0 132A0 133A0 134A0 135A0 136A0 137A0 Bits 0 1 2 3 4 5 6 7 00 7 CTR 8 15 CTR 16 23 THRESH...

Page 353: ...me read only fields using the I2 C register loading capability on boot Refer to I2 C Interface on page 139 for more information on the use of I2C controller register loading capability The registers i...

Page 354: ...CFG_GBL register MPLL_PWRON in the SMACx_CFG_GBL register TX_EN in the SMACx_CFG_CH3 register TX_EN in the SMACx_CFG_CH2 register TX_EN in the SMACx_CFG_CH1 register TX_EN in the SMACx_CFG_CH0 registe...

Page 355: ...e Reset Value 0 HALF_RATE Baud Rate Control 0 Running at 2 5Gbps and 3 125Gbps 1 Running at 1 25Gbps This bit corresponds to the SerDes PLL divider setting selected by the IO_SPEED field in the SRIO M...

Page 356: ...s Configuration Global on page 364 is set to 1 R W 0x1 18 DPLL_RESE T A rising edge resets the frequency register of the DPLL The rising edge may be generated by writing a 0 and then a 1 to the regist...

Page 357: ...Serial Port Electrical Layer Registers 357 Tsi574 User Manual June 6 2016 Integrated Device Technology www idt com 31 Reserved N A Note Only write 1 to this reserved field R W 1 Continued Bits Name D...

Page 358: ...scription Type Reset Value 0 HALF_RATE Baud rate control 0 Running at 2 5 Gbps and 3 125 Gbps 1 Running at 1 25 Gbps This bit corresponds to the SerDes PLL divider setting selected by the IO_SPEED fie...

Page 359: ...ation Global on page 364 is set to 1 R W 0x1 18 DPLL_RESE T A rising edge resets the frequency register of the DPLL The rising edge can be generated by writing a 0 and then a 1 to the register bit R W...

Page 360: ...eserved Bits Name Description Type Reset Value 0 HALF_RATE Baud rate control 0 Running at 2 5 Gbps and 3 125 Gbps 1 Running at 1 25 Gbps This bit corresponds to the SerDes PLL divider setting selected...

Page 361: ...PLL_RESE T A rising edge resets the frequency register of the DPLL The rising edge can be generated by writing a 0 and then a 1 to the register bit R W 0x1 19 20 Reserved N A R W 0 21 23 RX_EQ_VAL 2 0...

Page 362: ...escription Type Reset Value 0 HALF_RATE Baud rate control 0 Running at 2 5Gbps and 3 125Gbps 1 Running at 1 25Gbps This bit corresponds to the SerDes PLL divider setting selected by the IO_SPEED field...

Page 363: ...nfiguration Global on page 364 is set to 1 R W 0x1 18 DPLL_RESE T A rising edge resets the frequency register of the DPLL The rising edge can be generated by writing a 0 and then a 1 to the register b...

Page 364: ...t to 1 R W 1 1 BYPASS_INI T Control bit to bypass initialization logic 0 default SerDes initialization is determined by SP_IO_SPEED 1 0 1 Bypass initialization logic set by the SP_IO_SPEED 1 0 pins an...

Page 365: ...K_O FF 0 Turns on the MPLL clock 1 Stops the reference clock This bit is read only unless BYPASS_INIT in is set to 1 R W 0 26 31 Reserved N A R W Undefined The reserved bits in this register are conne...

Page 366: ...5 b10101 1133 1 22 0x16 5 b10110 1142 8 23 0x17 5 b10111 1152 5 24 0x18 5 b11000 1162 2 25 0x19 5 b11001 1171 9 26 0x1A 5 b11010 1181 6 27 0x1B 5 b11011 1191 3 28 0x1C 5 b11100 1200 9 29 0x1D 5 b11101...

Page 367: ...www idt com 5 h07 521 133 5 h08 563 144 5 h09 605 155 5 h0A 648 165 5 h0B 692 176 5 h14 605 100 5 h15 670 111 5 h16 735 121 5 h17 800 133 5 h18 865 144 5 h19 932 155 5 h1A 997 165 5 h1B 1065 3176 Tabl...

Page 368: ...014F Register offset 130C4 132C4 134C4 136C4 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved MPLL_PRESCALE 1 0 Unused 16 23 Unused 24 31 Unused Reserved Bits Name Description Type Reset Value 0 9 R...

Page 369: ...a link is powered up and enabled but dead that is there is no link partner responding When a link is declared dead the transmitting port on the Tsi574 removes all packets from its transmit queue and...

Page 370: ...ation refer to Port Loopback Testing on page 78 R W 0 23 DLB_EVEN_ EN Digital Equipment Loopback Mode Even numbered Port Digital equipment loopback mode connects Tx data flow to Rx data flow before th...

Page 371: ...ng to this register overrides the configuration provided by the pin 0 Normal mode of operation 1 Port powered down R W Undefined 29 PWDN_X4 Power down control for even numbered ports using this MAC In...

Page 372: ...7 00 07 Reserved RDR_LIMIT 08 15 RDR_LIMIT _EN Reserved IN_ARB_MODE Reserved TEA_INT_E N TEA_EN 16 23 TEA_OUT 15 8 24 31 TEA_OUT 7 0 Bits Name Description Type Reset Value 0 3 Reserved N A R 0x0 4 7...

Page 373: ...rupt is produced when a TEA event occurs R W 0 15 TEA_EN TEA Enable 0 TEA timer is disabled similar to writing all 0s to the TEA_OUT field 1 TEA timer is enabled R W 1 16 31 TEA_OUT 1 5 0 TEA Period T...

Page 374: ...gister offset 1AA04 Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 PORT7_IR Q PORT6_IR Q PORT5_IR Q PORT4_IR Q PORT3_IR Q PORT2_IR Q PORT1_IR Q PORT0_IR Q Bits Name Descriptio...

Page 375: ...erved 08 15 Reserved 16 23 Reserved 24 31 P7_ERR P6_ERR P5_ERR P4_ERR P3_ERR P2_ERR P1_ERR P0_ERR Bits Name Description Type Reset Value 0 23 Reserved N A R 0 24 P7_ERR Port 7 violated the maximum mul...

Page 376: ...et value 0x0000_0000 Register offset 1AA0C Bits 0 1 2 3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 P7_SET P6_SET P5_SET P4_SET P3_SET P2_SET P1_SET P0_SET Bits Name Description Type Re...

Page 377: ...RT5 PORT4 PORT3 PORT2 PORT1 PORT0 Bits Name Description Type Reset Value 0 3 Reserved N A Note These upper 4 bits are reserved in order to be compatible with the I2C Interface R 0 4 RCS Combined four...

Page 378: ...ser Manual June 6 2016 Integrated Device Technology www idt com 27 PORT4 Port 4 Interrupt R 0 28 PORT3 Port 3 Interrupt R 0 29 PORT2 Port 2 Interrupt R 0 30 PORT1 Port 1 Interrupt R 0 31 PORT0 Port 0...

Page 379: ...T2_EN PORT1_EN PORT0_EN Bits Name Description Type Reset Value 0 3 Reserved N A R 0 4 RCS_EN Four Reset Control Symbols Interrupt Enable R W 0 5 MCS_EN Multicast Event Control Symbol Interrupt Enable...

Page 380: ...C14 Bits 0 1 2 3 4 5 6 7 00 07 PW_TIMER Reserved 08 15 Reserved 16 23 Reserved 24 31 Reserved Bits Name Description Type Reset Value 0 3 PW_TIMER Port write Timer This field defines the time period to...

Page 381: ...a port write is sent any remaining port write requests from any port sets a bit in the register Register name RIO_PW_OREQ_STATUS Reset value 0x0000_0000 Register offset 1AC18 Bits 0 1 2 3 4 5 6 7 00...

Page 382: ...erved MCES_CTRL Reserved 08 15 Reserved 16 23 Reserved 24 31 Reserved Bits Name Description Type Reset Value 0 1 Reserved N A R 0 2 3 MCES_CTRL MCES Pin Control 00 Disabled The MCES pin does not affec...

Page 383: ...t register interface version of the IDT specific registers that is supported by this device Register name RIO 0 7 _MC_REG_VER Reset value 0x0000_0001 Register offset 1B000 1B100 1B200 1B300 1B400 1B50...

Page 384: ...m multicast operations if the multicast maximum latency timer expires for this port 1 Remove this port from future multicast operations if the multicast maximum latency timer expires for this port R W...

Page 385: ...the number of free buffer is greater than this value This value must be smaller than PRIO1WM Note It is a programming error for this value to be either greater than or equal to PRIO1WM or PRIO0WM or g...

Page 386: ...1B510 1B610 1B710 Bits 0 1 2 3 4 5 6 7 00 07 Reserved WRR_EN CHOOSE_ UC 08 15 Reserved 16 23 Reserved 24 31 Reserved WEIGHT Bits Name Description Type Reset Value 0 5 Reserved N A R 0 6 WRR_EN Weighte...

Page 387: ...714 Bits 0 1 2 3 4 5 6 7 00 07 Reserved WRR_EN CHOOSE_ UC 08 15 Reserved 16 23 Reserved 24 31 Reserved WEIGHT Bits Name Description Type Reset Value 0 5 Reserved N A R 0 6 WRR_EN Weighted Round Robin...

Page 388: ...718 Bits 0 1 2 3 4 5 6 7 00 07 Reserved WRR_EN CHOOSE_ UC 08 15 Reserved 16 23 Reserved 24 31 Reserved WEIGHT Bits Name Description Type Reset Value 0 5 Reserved N A R 0 6 WRR_EN Weighted Round Robin...

Page 389: ...71C Bits 0 1 2 3 4 5 6 7 00 07 Reserved WRR_EN CHOOSE_ UC 08 15 Reserved 16 23 Reserved 24 31 Reserved WEIGHT Bits Name Description Type Reset Value 0 5 Reserved N A R 0 6 WRR_EN Weighted Round Robin...

Page 390: ...s The SerDes is fully initialized when MPLL_PWR_ON is equal to 1 see SRIO MAC x SerDes Configuration Global on page 364 The SerDes register offsets in this section are based on lane 0 In order to defi...

Page 391: ...rved PAT0 24 31 PAT0 TRIGGER_ ERR MODE Bits Name Description Type Reset Value 0 17 Reserved NA R 0x0 18 27 PAT0 Pattern for MODE setting 3 5 Program the desired pattern in these 10bits when using mode...

Page 392: ...rved PAT0 24 31 PAT0 TRIGGER_ ERR MODE Bits Name Description Type Reset Value 0 17 Reserved NA R 0x0 18 27 PAT0 Pattern for MODE setting 3 5 Program the desired pattern in these 10bits when using mode...

Page 393: ...rved PAT0 24 31 PAT0 TRIGGER_ ERR MODE Bits Name Description Type Reset Value 0 17 Reserved NA R 0x0 18 27 PAT0 Pattern for MODE setting 3 5 Program the desired pattern in these 10bits when using mode...

Page 394: ...rved PAT0 24 31 PAT0 TRIGGER_ ERR MODE Bits Name Description Type Reset Value 0 17 Reserved NA R 0x0 18 27 PAT0 Pattern for MODE setting 3 5 Program the desired pattern in these 10bits when using mode...

Page 395: ...ote Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 1 15 COUNT Current error count If OV14 fiel...

Page 396: ...ignal overflows Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 1 15 COUNT Current error c...

Page 397: ...ignal overflows Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 1 15 COUNT Current error c...

Page 398: ...ignal overflows Note Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 1 15 COUNT Current error c...

Page 399: ...ead operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 15 DTHR_0 Bits below the useful resolution Note...

Page 400: ...Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 15 DTHR_0 Bits below the useful resolution Note...

Page 401: ...Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 15 DTHR_0 Bits below the useful resolution Note...

Page 402: ...Read operations on this register is pipelined Two reads needed to get current value The values are volatile and the value may change at any time R W 0x0 15 DTHR_0 Bits below the useful resolution Note...

Page 403: ...ange within a consecutive 256 byte address space For peripheral addresses the lowest address maps to the least significant byte of the internal register LSB while the highest address maps to the most...

Page 404: ...I2C Internal Read Data Register 0x1D218 0x1D21C 0x18 0x1F Reserved 0x1D220 0x20 0x23 EXI2C_ACC_STAT Externally Visible I2 C Slave Access Status Register 0x1D224 0x24 0x27 EXI2C_ACC_CNTRL Externally V...

Page 405: ...SD Setup and Hold Timing Register 0x1D34C n a I2C_SCL_PERIOD I2C_SCLK High and Low Timing Register 0x1D350 n a I2C_SCL_MIN_PERIOD I2C_SCLK Minimum High and Low Timing Register 0x1D354 n a I2C_SCL_ARB_...

Page 406: ...a chip reset 13 2 1 I2 C Device ID Register This register identifies the version of the IDT I2C block in this device Register name I2C_DEVID Reset value 0x0000_0001 Register offset 0x1D100 Bits 0 1 2...

Page 407: ...to be unaffected by this reset Register name I2C_RESET Reset value 0x0000_0000 Register offset 0x1D104 Bits 0 1 2 3 4 5 6 7 00 07 SRESET Reserved 08 15 Reserved 16 23 Reserved 24 31 Reserved Bits Nam...

Page 408: ...rocessed from MSB to LSB within an I2 C transaction 1 Data from to data registers is ordered processed from LSB to MSB within an I2 C transaction Data registers are I2 C Master Transmit Data Register...

Page 409: ...rs Register Descriptions 409 Tsi574 User Manual June 6 2016 Integrated Device Technology www idt com Do not change this register while a master operation is active The effect on the transaction cannot...

Page 410: ...NTRL Reset value 0x0000_0000 Register offset 0x1D10C Bits 0 1 2 3 4 5 6 7 00 07 START WRITE Reserved SIZE 08 15 Reserved 16 23 PADDR 24 31 PADDR Bits Name Description Type Reset Value 00 START Start O...

Page 411: ...e of 000 should not be normally used for a Read operation as any device put into read mode assumes at least one byte will be read An exception would be the SMBus Quick Command protocol to a device tha...

Page 412: ...it for ACK If PA_SIZE is 00 or 11 this phase is skipped Any loss of arbitration will abort with MCOL Any NACK will abort with MNACK 4 Send Data WRITE 1 If SIZE 0 send SIZE bytes from I2C_MST_TDATA bas...

Page 413: ...RDER is 1 bytes are loaded from LSB to MSB in order RBYTE0 RBYTE1 RBYTE2 RBYTE3 If the transaction size is less than four 4 bytes that is SIZE in the I2C Master Control Register 4 then any remaining b...

Page 414: ...DER is 1 bytes are taken from LSB to MSB in order TBYTE0 TBYTE1 TBYTE2 TBYTE3 If the transaction size is less than 4 bytes that is SIZE in the I2 C Master Control Register 4 then any remaining bytes i...

Page 415: ...TES Bits Name Description Type Reset Value 00 SLV_ACTIVE Slave Active 0 Slave is not addressed 1 Slave is addressed by external master and a read or write is active on the bus This bit is set followin...

Page 416: ...ster 11 Data outgoing read by external master At the end of a slave operation this field will hold its value until the next START RESTART If a slave operation aborts this field will qualify where in t...

Page 417: ...rts this field will qualify where in the transaction the error occurred R 000 23 MST_AN Master Ack Nack 0 Master transaction is not in the ACK NACK bit of a byte 1 Master transaction is in the ACK NAC...

Page 418: ...t Register is de asserted Register name I2C_INT_STAT Reset value 0x0000_0000 Register offset 0x1D11C Bits 0 1 2 3 4 5 6 7 00 07 Reserved OMB_ EMPTY IMB_FULL 08 15 Reserved BL_FAIL BL_OK 16 23 Reserved...

Page 419: ...by an external master invoking a write to an internal register This will not assert if slave writes are disabled WR_EN in the I2 C Slave Configuration Register 0 R W1C 0 22 SA_READ Slave Read 0 Inter...

Page 420: ...W1C 0 29 MA_NACK Master NACK 0 Interrupt status not asserted 1 NACK received during transaction A transaction initiated through the I2 C Master Control Register aborted due to receipt of a NACK in res...

Page 421: ...erved BL_FAIL BL_OK 16 23 Reserved SA_ FAIL SA_ WRITE SA_READ SA_OK 24 31 MA_DIAG Reserved MA_COL MA_TMO MA_NACK MA_ATMO MA_OK Bits Name Description Type Reset Value 0 5 Reserved Reserved R 0x00 6 OMB...

Page 422: ...nable MA_DIAG Interrupt 0 Interrupt is disabled 1 Interrupt is enabled R W 0 25 26 Reserved Reserved R 00 27 MA_COL Enable MA_COL Interrupt 0 Interrupt is disabled 1 Interrupt is enabled R W 0 28 MA_T...

Page 423: ...t value 0x0000_0000 Register offset 0x1D124 Bits 0 1 2 3 4 5 6 7 00 07 Reserved OMB_ EMPTY IMB_ FULL 08 15 Reserved BL_FAIL BL_OK 16 23 Reserved SA_FAIL SA_ WRITE SA_READ SA_OK 24 31 MA_DIAG Reserved...

Page 424: ...s set R W1S 0 24 MA_DIAG Set MA_DIAG Interrupt 0 No effect 1 Interrupt is set R W1S 0 25 26 Reserved Reserved R 00 27 MA_COL Set MA_COL Interrupt 0 No effect 1 Interrupt is set R W1S 0 28 MA_TMO Set M...

Page 425: ...effect 0 Transactions that read the Externally Visible I2 C Internal Read Data Register on page 435 will not invoke reads of the internal registers 1 Transactions that read the Externally Visible I2 C...

Page 426: ...erface is enabled SLV_ADDR is responded to when transaction started by external master When enabled the slave interface will acknowledge transactions to the SLV_ADDR from an external master If not ena...

Page 427: ...latched at power up from the state of input pins This allows board configuration of up to four unique Tsi574 devices on the I2C bus These two bits are then locked for writing until the SLV_UNLK bit is...

Page 428: ...is register can be read and written after boot loading is complete but has no further effect on block operation Register name I2C_BOOT_CNTRL Reset value Undefined Register offset 0x1D140 Bits 0 1 2 3...

Page 429: ...ddress as a 256 byte page select typically 2K EEPROMs When enabled and the 1 byte peripheral address wraps back to zero the least significant 3 bits of the device address is incremented followed by a...

Page 430: ...eld R W Undefined 16 18 PAGE_MODE Page Mode 000 8 bytes 001 32 bytes 010 64 bytes 011 128 bytes 100 256 bytes 101 512 bytes 110 1024 bytes 111 Infinite This field modifies the boot load process to adj...

Page 431: ...al address this field is shifted left by 3 and then copied internally upon boot start or a chain operation The internal address is then incremented as the boot load progresses For 2 byte addressing th...

Page 432: ...end of the boot load process this register will contain the last register address read from the EEPROM or the first four bytes of the register count Register name EXI2C_REG_WADDR Reset value 0x0000_0...

Page 433: ...31 WDATA Bits Name Description Type Reset Value 0 31 WDATA Internal Register Write Data Data written by the external I2C master to be used for an internal register write When WSIZE is configured for 4...

Page 434: ...Register name EXI2C_REG_RADDR Reset value 0x0000_0000 Register offset 0x1D210 Bits 0 1 2 3 4 5 6 7 00 07 ADDR 08 15 ADDR 16 23 ADDR 24 31 ADDR Reserved Bits Name Description Type Reset Value 0 29 ADDR...

Page 435: ...ding this register When RSIZE is configured for 4 byte access in the Externally Visible I2 C Internal Access Control Register on page 438 this register is updated by the read of an internal register w...

Page 436: ...3 4 5 6 7 00 07 Reserved 08 15 Reserved 16 23 Reserved 24 31 ACC_OK Reserved OMB_ FLAG IMB_ FLAG Reserved ALERT_ FLAG Bits Name Description Type Reset Value 00 23 Reserved Reserved R 0x00_0000 24 ACC_...

Page 437: ...x This bit is set when data is written to the incoming mailbox register Externally Visible I2C Incoming Mailbox Register by an external I2C master This bit remains set flag up until software reads the...

Page 438: ...lave interface This register corresponds to the I2 C peripheral addresses 0x24 through 0x27 Register name EXI2C_ACC_CNTRL Reset value 0x0000_00A0 Register offset 0x1D224 Bits 0 1 2 3 4 5 6 7 00 07 Res...

Page 439: ...ng is on consecutive internal registers can be read in one I2C transaction without the need to reset the peripheral address because the peripheral address wraps from 0x17 back to 0x14 If auto incremen...

Page 440: ...ill asserting at the time the W1C occurs the bit remains set The software status bits 1 3 are R W from the register bus They can be set or cleared by software and thereby used for any system purpose A...

Page 441: ...RT_FLAG R W 1 7 TEA Enable TEA Alert Response 0 Status asserted will not enable setting ALERT_FLAG 1 Status asserted will enable setting ALERT_FLAG R W 1 8 RCS Enable RCS Alert Response 0 Status asser...

Page 442: ...W 1 27 PORT4 Enable PORT4 Alert Response 0 Status asserted will not enable setting ALERT_FLAG 1 Status asserted will enable setting ALERT_FLAG R W 1 28 PORT3 Enable PORT3 Alert Response 0 Status asse...

Page 443: ...addresses 0x84 through 0x87 Register name EXI2C_STAT_ENABLE Reset value 0xFFFF_FFFF Register offset 0x1D284 Bits 0 1 2 3 4 5 6 7 00 07 RESET SW_ STAT2 SW_ STAT1 SW_ STAT0 OMBW IMBR I2C TEA 08 15 RCS M...

Page 444: ...us asserted will enable setting ALERT_FLAG R W 1 10 12 Reserved Reserved These bits are unused in the Tsi574 The enables can be changed but have no effect R W 111 13 LOGICAL Enable LOGICAL Alert Respo...

Page 445: ...ble PORT3 Alert Response 0 Status asserted will not enable setting ALERT_FLAG 1 Status asserted will enable setting ALERT_FLAG R W 1 29 PORT2 Enable PORT2 Alert Response 0 Status asserted will not ena...

Page 446: ...1 2 3 4 5 6 7 00 07 DATA 08 15 DATA 16 23 DATA 24 31 DATA Bits Name Description Type Reset Value 0 31 DATA Mailbox data to be transferred to an external I2 C master Every write to this register by sof...

Page 447: ...s register corresponds to the I2 C peripheral addresses 0x94 through 0x97 Register name EXI2C_MBOX_IN Reset value 0x0000_0000 Register offset 0x1D294 Bits 0 1 2 3 4 5 6 7 00 07 DATA 08 15 DATA 16 23 D...

Page 448: ...corresponding bits in the I2C Enable Event Register and then determine whether a related bit in the I2C_INT_STAT register is set Note These registers are affected by a reset controlled by the I2 C Res...

Page 449: ...ing mailbox R W1C 0 09 OMBR Outgoing Mailbox Read Event 0 Event not asserted 1 Slave interface completed a read transaction to the outgoing mailbox when the OMB_FLAG was set The event is asserted only...

Page 450: ...d Error Event 0 Event not asserted 1 The boot load sequence failed due to an error during register reading a protocol error NACK when ACK expected an I2C_SCLK low timer collision after the device addr...

Page 451: ...me slave device This event can also assert during boot load and provides more information on the source of a BLERR event R W1C 0 28 MTRTO Master Transaction Timeout Event 0 Event not asserted 1 Transa...

Page 452: ...SRESET is asserted in the I2C Reset Register Register name I2C_NEW_EVENT Reset value 0x0000_0000 Register offset 0x1D308 Bits 0 1 2 3 4 5 6 7 00 07 Reserved SDW SDR SD Reserved DTIMER DHIST DCMDD 08 1...

Page 453: ...not asserted 1 Event asserted R W1S 0 12 STRTO Slave Transaction Timeout Event 0 Event not asserted 1 Event asserted R W1S 0 13 SBTTO Slave Byte Timeout Event 0 Event not asserted 1 Event asserted R W...

Page 454: ...ed R 00 26 MNACK Master NACK Received Event 0 Event not asserted 1 Event asserted R W1S 0 27 MCOL Master Collision Detect Event 0 Event not asserted 1 Event asserted R W1S 0 28 MTRTO Master Transactio...

Page 455: ...MARBTO Bits Name Description Type Reset Value 00 Reserved Reserved R 0 01 SDW Slave Internal Register Write Done Enable 0 Event does not assert to interrupt status 1 Event will assert in interrupt st...

Page 456: ...O Slave Byte Timeout Enable 0 Event does not assert to interrupt status 1 Event will assert in the interrupt status R W 1 14 SSCLTO Slave I2C_SCLK Low Timeout Enable 0 Event does not assert to interru...

Page 457: ...27 MCOL Master Collision Detect Enable 0 Event does not assert to interrupt status 1 Event will assert in the interrupt status R W 1 28 MTRTO Master Transaction Timeout Enable 0 Event does not assert...

Page 458: ...ype Reset Value 00 03 Reserved Reserved R 0x0 04 15 USDIV Period Divider for Micro Second Based Timers This field divides the reference clock down for use by the Idle Detect Timer the Byte Timeout Tim...

Page 459: ...07 START_SETUP 08 15 START_SETUP 16 23 START_HOLD 24 31 START_HOLD Bits Name Description Type Reset Value 00 15 START_SETUP Count for the START Condition Setup Period Defines the minimum setup time fo...

Page 460: ...STOP Condition Setup Period Defines the minimum setup time for the STOP condition that is both I2C_SCLK seen high and I2C_SD seen low prior to I2C_SD released high This is a master only timing paramet...

Page 461: ...I2C_SD Setup Period Defines the minimum setup time for the I2C_SD signal that is I2C_SD set to desired value prior to rising edge of I2C_SCLK This applies to both slave and master interface Note This...

Page 462: ...SCL_LOW 24 31 SCL_LOW Bits Name Description Type Reset Value 00 15 SCL_HIGH Count for I2C_SCLK High Period Defines the nominal high period of the clock from rising edge to falling edge of I2C_SCLK Th...

Page 463: ...INL 24 31 SCL_MINL Bits Name Description Type Reset Value 00 15 SCL_MINH Count for I2C_SCLK High Minimum Period Defines the minimum high period of the clock from rising edge seen high to falling edge...

Page 464: ...from I2C_SCLK falling edge to the next I2C_SCLK rising edge Value 0x0 disables the timeout Period SCL_TO SCL_TO Period USDIV where USDIV is the microsecond time defined in the I2C Time Period Divider...

Page 465: ...mount of time for a byte to be transferred on the I2C bus This covers the period from Start condition to next ACK NACK between two successive ACK NACK bits or from ACK NACK to Stop Restart condition A...

Page 466: ...r Initial reset value is used for overall boot load timeout During normal operation this timer can be used for any general purpose timing A value of 0 disables the timeout Period DTIMER COUNT Period M...

Page 467: ...ence This register is initialized to the count read from the first two bytes of the EEPROM after reset or to the first two byte read after a boot chaining operation The field counts down as each regis...

Page 468: ...Disabled 0 Boot enabled 1 Boot disabled R Undefined 02 PASIZE Peripheral Address Size 0 1 byte peripheral address 1 2 byte peripheral address Note This is the state of the I2C_BOOT_CNTRL PSIZE field...

Page 469: ...n the Logical Common Transport and Physical Layer specifications TheTsi574 fully manages the end to end link on each port A 1 Protocol The RapidIO Physical Layer 1x 4x LP Serial specification defines...

Page 470: ...for the 1x and 4x interfaces and defines the link initialization sequence for clock synchronization The PCS function is also responsible for idle sequence generation encoding for transmission and lane...

Page 471: ...Code Group Use Number of Groups Encoding 8 bit Value PD packet delimiter 1 K28 3 0x7C SC start of Control Symbol 1 K28 0 0x1C I 1x Idle K or R or A see below 0xBC or 0xFD or 0xFB K 1x Sync 1 K28 5 0xB...

Page 472: ...5 bits stype0 0 2 definition P 0 P 1 stype1 0 2 cmd CRC 000 pkt accepte d pkt ackID buf_status 001 pkt rtry pkt ackID buf_status 010 pkt not acce pted pkt ackID cause see below 011 reserved 100 statu...

Page 473: ...0110 011 11 reserved 10000 OK 10001 111 11 reserved stype1 stype1 0 2 definition cmd 0 2 cmd function pkt delimiter 000 start of pkt 000 reserved yes 001 stomp 000 reserved yes 010 end of pkt 000 rese...

Page 474: ...A Serial RapidIO Protocol Overview Physical Layer 474 Tsi574 User Manual June 6 2016 Integrated Device Technology www idt com...

Page 475: ...t are outside of the RapidIO specification The ability to support multiple line rates gives the Tsi574 flexibility in both application support and power consumption Table 53 shows the supported line r...

Page 476: ...the recommended method B 1 1 1 Modification by EEPROM Boot Load Modifying the EEPROM is the recommended method for using the S_CLK at 125 MHz to create a 3 125 Gbps link baud rate because the EEPROM b...

Page 477: ...ed in Example Maintenance Transaction Sequence on page 477 Example Maintenance Transaction Sequence The following procedure configures port two After these steps are complete port two can train with i...

Page 478: ...MACx_CFG_GBL register Write offset 0x132C0 with 0x4A060005 Write offset 0x132c0 with 0xCA060005 11 Set the MPLL_PWRON bit in the SMACx_CFG_GLOBAL register Write offset 0x132C0 with 0xCA060085 Ensure t...

Page 479: ...onnect Specification Revision 1 3 B 2 1 1 Port Link Time out CSR RapidIO Part 6 1x 4x LP Serial Physical Layer Specification Revision 1 3 Section 6 6 2 2 Port Link Time out CSR Block Offset 0x20 The R...

Page 480: ...IMER_EN to be de asserted When the state machine is not in the SILENT state SILENCE_TIMER_DONE is de asserted IDT Implementation The Tsi574 s silence timer does not have user programmable registers Th...

Page 481: ...e and if the link partner supports 4x mode for all four lanes to be aligned The DISCOVERY_TIMER has a default value of 9 decimal but can be programmed to various values The results of changing the DIS...

Page 482: ...llowing formula 2 13 DLT_THRESH P_CLK period P_CLK is 100 MHz which gives a P_CLK period of 10nS Default value of DLT_THRESH is 0x7FFF which corresponds to 32767 Using these parameters the populated f...

Page 483: ...r use by the Idle Detect Timer the Byte Timeout Timer the I2C_SCLK Low Timeout Timer and the Milli Second Period Divider Period USDIV Period P_CLK USDIV 1 P_CLK is 10 ns Tsi574 reset value is 0x0063 M...

Page 484: ...ng for the Stop condition when generated by the master control logic and the Idle Detect timer The Stop Idle register is broken down as follows The timer period for the STOP_SETUP is relative to the r...

Page 485: ...ace It is shadowed during boot loading and can be reprogrammed prior to a chain operation without affecting the bus timing for the current EEPROM SDA_SETUP Count for the I2C_SD Setup Period The SDA_SE...

Page 486: ...OW field defines the nominal low period of the clock from falling edge to rising edge of I2C_SCLK This is a master only parameter The actual observed period may be longer if other devices pull the clo...

Page 487: ...e maximum amount of time for a slave device holding the I2C_SCLK signal low This timeout covers the period from I2C_SCLK falling edge to the next I2C_SCLK rising edge A value of 0 disables the timeout...

Page 488: ...is 0x0000 TRAN_TO Count for Transaction Timeout Period The TRAN_TO field defines the maximum amount of time for a transaction on the I2C bus This covers the period from Start to Stop A value of 0 dis...

Page 489: ...ers reside is a synchronous bus clocked by the P_CLK source A decrease in the P_CLK frequency causes a proportional increase in register access time during RapidIO maintenance transactions JTAG regist...

Page 490: ...B Clocking P_CLK Programming 490 Tsi574 User Manual June 6 2016 Integrated Device Technology www idt com...

Page 491: ...ad_prbs_all txt Script C 1 Tsi574_start_prbs_all txt Script This JTAG script is used to turn on the PRBS pattern generator for each lane to be tested The SerDes in a port are offset by 0x40 from the l...

Page 492: ...0000002 w 1e6e0 00000002 Port 8 w 1e820 00000002 Start 2 7 Pattern Generator w 1e860 00000002 w 1e8a0 00000002 w 1e8e0 00000002 Port a w 1ea20 00000002 Start 2 7 Pattern Generator w 1ea60 00000002 w 1...

Page 493: ...1 25 Gbps PRBS testing at 2 5 or 3 125 Gbps requires the HALF_RATE bit to be cleared The data to be written therefore becomes 0x203CE511 i 0 Port 0 w 130b0 A03CE511 Clear RX_ALIGN_EN w 130b4 A03CE511...

Page 494: ...11 w 13eb8 A03CE511 w 13ebc A03CE511 C 3 Tsi574_sync_prbs_all txt Script This JTAG script is used to turn on the PRBS pattern matcher for each lane to be tested The SerDes in a port are offset by 0x40...

Page 495: ...b0 0000000a w 1e2f0 0000000a w 1e230 00000002 w 1e270 00000002 w 1e2b0 00000002 w 1e2f0 00000002 Port 4 w 1e430 0000000a Sync pattern matcher w 1e470 0000000a w 1e4b0 0000000a w 1e4f0 0000000a w 1e430...

Page 496: ...00002 w 1e870 00000002 w 1e8b0 00000002 w 1e8f0 00000002 Port a w 1ea30 0000000a Sync pattern matcher w 1ea70 0000000a w 1eab0 0000000a w 1eaf0 0000000a w 1ea30 00000002 w 1ea70 00000002 w 1eab0 00000...

Page 497: ...Tsi574_read_prbs_all txt Script This script is used to read the PRBS values Note that the PRBS error counter and overflow bit fields must be read twice to determine the correct value The result of the...

Page 498: ...e 6 2016 Integrated Device Technology www idt com Port4 r 1e430 r 1e430 r 1e470 r 1e470 r 1e4b0 r 1e4b0 r 1e4f0 r 1e4f0 Port6 r 1e630 r 1e630 r 1e670 r 1e670 r 1e6b0 r 1e6b0 r 1e6f0 r 1e6f0 Port8 r 1e...

Page 499: ...ser Manual June 6 2016 Integrated Device Technology www idt com r 1ea30 r 1ea70 r 1ea70 r 1eab0 r 1eab0 r 1eaf0 r 1eaf0 Portc r 1ec30 r 1ec30 r 1ec70 r 1ec70 r 1ecb0 r 1ecb0 r 1ecf0 r 1ecf0 Porte r 1e...

Page 500: ...C PRBS Scripts Tsi574_read_prbs_all txt Script 500 Tsi574 User Manual June 6 2016 Integrated Device Technology www idt com...

Page 501: ...tion shows the EEPROM script used in Modification by EEPROM Boot Load D 1 Script ew 0 0047FFFF ew 4 FFFFFFFF 1 ew 8 138c8 ew c 7FFF0012 2 ew 10 138c0 ew 14 CA060084 3 ew 18 138B0 ew 1c 203CA513 4 ew 2...

Page 502: ...com 8 ew 40 138B4 ew 44 203C2513 9 ew 48 138B8 ew 4c 203C2513 A ew 50 138BC ew 54 203C2513 B ew 58 138B0 ew 5c 200C2513 C ew 60 138B4 ew 64 200C2513 D ew 68 138B8 ew 6c 200C2513 E ew 70 138BC ew 74 20...

Page 503: ...12 ew 90 138c0 ew 94 CA060045 13 ew 98 138c0 ew 9c CA060005 14 ew a0 138c0 ew a4 4A060005 15 ew a8 138c0 ew ac CA060005 16 ew b0 138c0 ew b4 CA060085 17 ew b8 138B0 ew bc 203C2513 18 ew c0 138B4 ew c4...

Page 504: ...203CA513 1D ew e8 138B8 ew ec 203CA513 1E ew f0 138BC ew f4 203CA513 1F ew f8 138B0 ew fc 203CE513 20 ew 100 138B4 ew 104 203CE513 21 ew 108 138B8 ew 10c 203CE513 22 ew 110 138BC ew 114 203CE513 23 ew...

Page 505: ...136B0 ew 134 203CA513 27 ew 138 136B4 ew 13c 203CA513 28 ew 140 136B8 ew 144 203CA513 29 ew 148 136BC ew 14c 203CA513 2a ew 150 136B0 ew 154 203C2513 2b ew 158 136B4 ew 15c 203C2513 2c ew 160 136B8 ew...

Page 506: ...136B8 ew 184 200C2513 31 ew 188 136BC ew 18c 200C2513 32 ew 190 136c0 ew 194 CA060004 33 ew 198 136c0 ew 19c CA060044 34 ew 1a0 136C4 ew 1a4 002C0545 35 ew 1a8 136c0 ew 1ac CA060045 36 ew 1b0 136c0 ew...

Page 507: ...136B0 ew 1d4 203C2513 3b ew 1d8 136B4 ew 1dc 203C2513 3c ew 1e0 136B8 ew 1e4 203C2513 3d ew 1e8 136BC ew 1ec 203C2513 3e ew 1f0 136B0 ew 1f4 203CA513 3f ew 1f8 136B4 ew 1fc 203CA513 40 ew 200 136B8 ew...

Page 508: ...ipts Script 508 Tsi574 User Manual June 6 2016 Integrated Device Technology www idt com 44 ew 220 136B8 ew 224 203CE513 45 ew 228 136BC ew 22c 203CE513 46 ew 230 136c8 ew 234 7FFF0002 47 ew 238 8 ew 2...

Page 509: ...mable Driver Current and Equalization 76 Error Management 57 Error Management of Multicast Packets 116 Multicast Maximum Latency Timer 117 Silent Discard of Packets 118 Event Notification 119 Interrup...

Page 510: ...MA Layer 470 Port Aggregation 4x and 1x link modes 67 1x 1x Configuration 68 4x 0x Configuration 69 Port Power up and Power down 212 Port Reset 118 Port Width Override 212 Port Write Notifications 131...

Page 511: ...ntroller 222 Multicast 220 Power Supplies 223 Serial Port Configuration 216 Serial Port Lane Ordering Select 219 Serial Port Receive 215 Serial Port Speed Select 218 Serial Port Transmit 215 Signal Ty...

Page 512: ...Index 512 Tsi574 User Manual June 6 2016 Integrated Device Technology www idt com...

Page 513: ...June 6 2016 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose CA 95138 for SALES 800 345 7015 or 408 284 8200 www idt com for Tech Support srio idt com...

Page 514: ...e intended for developers skilled in the art designing with Renesas products You are solely responsible for 1 selecting the appropriate products for your application 2 designing validating and testing...

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