Renesas IDT Tsi574, User Manual

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12. Serial RapidIO Registers > IDT-Specific Performance Registers 338
Tsi574 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
12.9.6 RapidIO Port x Performance Statistics Counter 2 Register
This register is used to collect performance statistics. These counters provide the means of
accumulating statistics for the purposes of performance monitoring measurements: throughput and
latency.
The PS2_CTR counter collects performance statistics information based on the configuration fields
specified in the
“RapidIO Port x Performance Statistics Counter 2 and 3 Control Register” on page 328
register.
The PS2_CTR counter value is writable for testing purposes. This counter saturates when it reaches its
maximum value 0xFFFFFFFF and is cleared on a read. The PS2_CTR is enabled, when
PS2_PRIO[0..3] value in the
“RapidIO Port x Performance Statistics Counter 2 and 3 Control Register”
on page 328 is configured to a value other than 0.
Register name: SP{0..7}_PSC2
Reset value: 0x0000_0000
Register offset: 13048, 13148, 13248, 13348, 13448,
13548, 13648, 13748
Bits 0 1 2 3 4 5 6 7
00:7 PS2_CTR
8:15 PS2_CTR
16:23 PS2_CTR
24:31 PS2_CTR
Bits Name Description Type
Reset
Value
0:31 PS2_CTR This counter is used to collect performance statistics based on the
configurations specified through the
“RapidIO Port x Performance
Statistics Counter 2 and 3 Control Register” register.
A read clears this register.
R/W 0