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Tsi574 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
9. JTAG
Interface
This chapter describes the main features of the JTAG interface. It includes the following information:
•
•
“JTAG Device Identification Number” on page 200
•
“JTAG Register Access Details” on page 200
9.1
Overview
The JTAG interface in Tsi574 is fully compliant with IEEE 1149.6 B
oundary Scan Testing of Advanced
Digital Networks
as well as IEEE 1149.1
Standard Test Access Port and Boundary Scan Architecture
standards. There are five standard pins associated with the interface (TMS, TCK, TDI, TDO and
TRST_b) which allow full control of the internal TAP (Test Access Port) controller.
The JTAG Interface has the following features:
•
Contains a 5-pin Test Access Port (TAP) controller, with support for the following registers:
— Instruction register (IR)
— Boundary scan register
— Bypass register
— Device ID register
— User test data register (DR)
•
IDT-specific pin (BCE) which allows full 1149.6 compliant boundary-scan tests. This pin should
be held high on the board.
•
Supports debug access of Tsi574’s configuration registers
•
Supports the following instruction opcodes:
— Sample/Preload
— Extest
— EXTEST_PULSE
(1149.6)
— EXTEST_TRAIN
(1149.6)
— Bypass
— Hi-Z
— IDCODE
— Clamp
— User data select
