7. I
2
C Interface > Tsi574 as I
2
C Slave
149
Tsi574 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
7.4.6
Master Data Transactions
After the peripheral address phase, if any, 0 to 4 bytes of data are read or written, followed by the Stop
condition. The number of bytes to be transferred is set in the SIZE field of the
when the operation is started, the type of transaction (read or write) is set in the WRITE field
of the same register, and the order of byte transfer is set in the DORDER field of the
For a write transaction, bytes are taken from the
C Master Transmit Data Register”
based on
DORDER and sent to the target device. Each byte must be ACKed by the device. If a NACK is
received, the transaction is aborted with a Stop, an MA_NACK interrupt status in the
. An optional interrupt can also be sent to the Interrupt Controller if enabled in
MA_NACK of the
For a read transaction, bytes are received from the target device and placed in the
based on DORDER. Each byte is ACKed by the Tsi574, except for the final byte that is
NACKed to tell the target device to stop sending data, followed by a Stop condition to idle the bus.
Upon successful completion of a transaction, the MA_OK interrupt status is updated in the
. An optional interrupt can also be sent to the Interrupt Controller if enabled
in MA_OK of the
.
7.5
Tsi574 as I
2
C Slave
The Tsi574 can operate as a slave device on the I
2
C bus. An external master device places a transaction
on the bus with a device address that matches that programmed in the SLV_ADDR field of the
, or matches the fixed SMBus Alert Response address. The external
master can then read or write to the Tsi574 through a small block of 256 addresses called the
Tsi574
peripheral address space
, and do the following:
•
Directly access limited status, read and write mailboxes
•
Configure some options related to the slave access
•
Indirectly read or write any other register in the Tsi574 that is accessible through the register bus
shows the bus protocols for accessing the Tsi574 as a slave device. The general procedure
requires the external master to address the Tsi574, set the peripheral address to a position within the
Tsi574 peripheral address space, then write or read some number of bytes. A write is terminated with a
Stop or Restart, and a read is ended when the master responds to a byte with a NACK. There is no limit
to the number of bytes that can be read or written in one transaction. The Tsi574 increments the
peripheral address pointer after each byte, and wraps within the 256 space (see
). Read and write transactions can be mixed by the external master issuing a Restart
instead of a Stop, then sending a new transaction that addresses the Tsi574 (all writes must include the
peripheral address byte).
If the Tsi574 experiences a chip reset while it is writing to an EEPROM, the write does not
complete and the data at the target EEPROM address may be corrupted.
