Renesas IDT Tsi574, User Manual

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3. Serial RapidIO Electrical Interface > Clocking 70
Tsi574 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
The Tsi574 uses only one external differential clock source (S_CLK_P/N) as the reference to generate
all internal clocks for processing the data. When the frequency of the reference clock is set at
156.25 MHz, Tsi574 can support three different RapidIO standard signaling rates (3.125 Gbps,
2.5 Gbps, and 1.25 Gbps).
Table 5 shows the port speeds and bandwidths supported by the Tsi574. For
more information on clocking refer to “Clocks, Resets and Power-up Options” on page 203 and
“Clocking” on page 475 .
The data rate of all the ports in Tsi574 at power-up is determined by the setting of the
SP_IO_SPEED[1:0] pins (see
“Signal Descriptions” ). There is only one pair of SP_IO_SPEED pins for
the entire device, which means all RapidIO ports default to the same speed at power-up. After reset, the
individual port speeds can be configured through registers (IO_SPEED in
“SRIO MAC x Digital
Loopback and Clock Selection Register” on page 369 ) or through the I
2
C configuration EEPROM.
The RapidIO Interconnect Specification (Revision 1.3) requires the receive and transmit signals must
operate at the same baud rate. This means a port must transmit at the same clock rate that it receives
/-100 ppm.
3.4.1 Changing the Clock Speed
The following procedure changes the signaling rate of a port:
1. Set PWDN_X4 in the “SRIO MAC x Digital Loopback and Clock Selection Register” on page 369
to 1
2. Select the new clock speed using IO_SPEED in the SMACx_DLOOP_CLK_SEL register
3. Set PWDN_X4 in the SMACx_DLOOP_CLK_SEL to 0
Table 5: Reference Clock Frequency and Supported Serial RapidIO Data Rates
Reference
Clock
Frequency
(S_CLK_p/n)
Supported
Data Rate
SP_IO_SPEED[1:0]
Setting
Default Speed for
all Ports
User Bandwidth
(1x mode)
User Bandwidth
(4x mode)
156.25MHz
a
a. For information about 125 MHz S_CLK refer to
“Clocking” on page 475 .
1.25 Gbit/s 00 1.25 Gbit/s 1.0 Gbit/s 4.0 Gbit/s
2.50 Gbit/s 01 2.50 Gbit/s 2.0 Gbit/s 8.0 Gbit/s
3.125 Gbit/s 10 3.125 Gbit/s 2.5 Gbit/s 10 Gbit/s
N/A 11
(Illegal)
Undefined Undefined Undefined
When ports in the same MAC are both operating in 1x mode, both ports operate at the same
rate.
The settings of SP_IO_SPEED[1:0] pins and the reference clock used have a strict
relationship. Entering an illegal setting causes unpredictable behavior of the device.