Renesas IDT Tsi574, User Manual

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12. Serial RapidIO Registers > SerDes Per Lane Register 400
Tsi574 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
12.14.10 SerDes Lane 1 Frequency and Phase Value Register
This register contains the frequency and phase of the incoming eyes on the SerDes.
Register name: SMAC{0,2,4,6}_FP_VAL_1
Reset value: 0x0000_0000
Register offset: 1E074, 1E274, 1E474, 1E674
Bits 0 1 2 3 4 5 6 7
00:07 Reserved FVAL
08:15 FVAL DTHR_0
16:23 Reserved PVAL
24:31 PVAL DTHR_1
Bits Name Description Type
Reset
Value
0:1 Reserved NA R 0x0
2:14 FVAL Frequency is 1.526*FVAL ppm from the reference.
Note: Read operations on this register is pipelined. Two reads needed
to get current value. The values are volatile and the value may change
at any time
R/W 0x0
15 DTHR_0 Bits below the useful resolution
Note: Read operations on this register is pipelined. Two reads needed
to get current value. The values are volatile and the value may change
at any time
R/W 0
16:20 Reserved NA R 0x0
21:30 PVAL Phase is 0.78125*pval ps from zero reference
Note: Read operations on this register is pipelined. Two reads needed
to get current value. The values are volatile and the value may change
at any time
R/W 0x0
31 DTHR_1 Bits below the useful resolution
Note: Read operations on this register is pipelined. Two reads needed
to get current value. The values are volatile and the value may change
at any time
R/W 0x0