7. I
2
C Interface > Tsi574 as I
2
C Slave
151
Tsi574 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
Figure 32: Transaction Protocols for Tsi574 as Slave
7.5.1
Slave Clock Stretching
When the Tsi574 is a slave, the external master generates the I
2
C clock (I2C_SCLK). If the Tsi574
must access the internal register bus, I2C_SCLK is held low until data is available on a register read, or
until a register write completes.
P/R
Shaded = Response From Slave Interface
A = Ack
N = Nack
S = Start
P = Stop
R = Restart
S/R
SLV_PA
WriteData
7 Bit Wr(0)
Slave Address
Peripheral
Starting at New SLV_PA
WriteData
A
A
A
A
WriteData A
0 or more bytes (no defined limit)
Write Transaction
Matched to SLV_ADDR
Sets SLV_PA
Data Written to Peripheral Space
P/R
ReadData
ReadData
A
A
ReadData N
Read Transaction (Setting Peripheral Address)
Readdress for Read
SLV_PA incremented(*) after each byte
Address
Starting at New SLV_PA
Data Read from Peripheral Space
S/R
SLV_PA
7 Bit Wr(0) A
A
Slave Address
Peripheral
Matched to SLV_ADDR
Address
R 7 Bit RD(1) A
Slave Address
Matched to SLV_ADDR
Sets SLV_PA
1 or more bytes (no defined limit)
SLV_PA incremented(*) after each byte
S/R 7 Bit RD(1) A
Slave Address
Matched to SLV_ADDR
Read Transaction (Using Last Peripheral Address)
P/R
ReadData
ReadData
A
A
ReadData N
Starting at Current SLV_PA
Data Read from Peripheral Space
1 or more bytes (no defined limit)
SLV_PA incremented(*) after each byte
(*) Certain exceptions occur - see text
