Renesas IDT Tsi574, User Manual

Page: 425 / 514

13. I2C Registers > Register Descriptions 425
Tsi574 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
13.2.11 I
2
C Slave Configuration Register
This register configures the slave interface portion of the I
2
C block. The slave interface is the logic that
responds to transactions from an external master on the I
2
C bus.
Register name: I2C_SLV_CFG
Reset value: 0xD0000030
Register offset: 0x1D12C
Bits 0 1 2 3 4 5 6 7
00:07 RD_EN WR_EN ALRT_EN SLV_EN Reserved SLV_UNLK
08:15 Reserved
16:23 Reserved
24:31 Reserved SLV_ADDR
Bits Name Description Type
Reset
Value
0 RD_EN Register Bus Read Enable
This bit controls whether external masters can read registers
internal to the Tsi574. The SLV_EN bit must also be set for
this option to have any effect.
0 = Transactions that read the “Externally Visible I
2
C Internal
Read Data Register” on page 435 will not invoke reads of
the internal registers.
1 = Transactions that read the “Externally Visible I
2
C Internal
Read Data Register” on page 435 will trigger reads of the
internal register whose address is in the “Externally Visible
I
2
C Internal Read Address Register” on page 434 .
R/W 1
1 WR_EN Register Bus Write Enable
This bit controls whether external masters can write to
Tsi574’s internal registers. The SLV_EN bit must also be set
for this option to have any effect.0 = Transactions that write
the
“Externally Visible I
2
C Internal Write Data Register” on
page 433 will not invoke writes of the internal registers.
1 = Transactions that write the “Externally Visible I
2
C
Internal Write Data Register” on page 433 will trigger writes
of the internal register whose address is in the “Externally
Visible I
2
C Internal Write Address Register” on page 432 .
R/W 1