Renesas IDT Tsi574, User Manual

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7. I
2
C Interface > Tsi574 as I
2
C Slave 150
Tsi574 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
At the completion of any slave transaction, either the SA_OK or SA_FAIL interrupt status is updated in
the
“I
2
C Interrupt Status Register” . An optional interrupt can be sent to the Interrupt Controller, if
enabled in SA_OK or SA_FAIL of the “I
2
C Interrupt Enable Register” , to alert the processor/host that
an external device has accessed the peripheral address space.
In addition, either the SA_WRITE or SA_READ interrupt status is updated in the “I
2
C Interrupt Status
Register” if a read or write to the internal register space was triggered by the access. An optional
interrupt can also be sent to the Interrupt Controller if enabled in SA_WRITE or SA_READ of the “I
2
C
Interrupt Enable Register” The SA_FAIL interrupt indicates the slave transaction encountered an error.
An SA_FAIL includes the slave logic detecting a collision when it was responding with data or an
ACK/NACK, or one of the time-outs triggering and aborting the transaction (see
“Timeouts” ). If no
error condition occurred, then the SA_OK interrupt is triggered.