12. Serial RapidIO Registers > IDT-Specific RapidIO Registers
305
Tsi574 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
12.8.4
RapidIO Port x RapidIO Watermarks
This register controls ingress buffer allocation for reception of packets for each port (see
).
Register name: SP{BC,0..7}_RIO_WM
Reset value: 0x0001_0203
Register offset: 1000C, 1100C, 1110C, 1120C, 1130C,
1140C, 1150C, 1160C, 1170C
Bits
0
1
2
3
4
5
6
7
00:7
Reserved
8:15
Reserved
PRIO2WM
16:23
Reserved
PRIO1WM
24:31
Reserved
PRIO0WM
Bits
Name
Description
Type
Reset
Value
0:12
Reserved
N/A
R
0
13:15
PRIO2WM
Priority 2 packets are accepted if the number of free buffer is greater
than this value. This value must be smaller than PRIO1WM.
Note: It is a programming error for this value to be either greater than
or equal to PRIO1WM or PRIO0WM, or greater than 7.
R/W
1
16:20
Reserved
N/A
R
0
21:23
PRIO1WM
Priority 1 packets are accepted if the number of free buffer is greater
than this value. This value must be smaller than PRIO0WM.
Note: It is a programming error for this value to be either greater than
or equal to PRIO0WM, or greater than 7.
R/W
2
24:28
Reserved
N/A
R
0
29:31
PRIO0WM
Priority 0 packets are accepted if the number of free buffer is greater
than this value.
Note: It is a programming error for this value to be greater than 7.
R/W
3
This register must be programmed after reset and not when transactions are in progress.
