3
rd
Generation Rack-
Mount RDMS™
29
Quasonix, Inc.
Screen Name
Actual Name
QPSK
QPSK
AQPSK
AQPSK
AUQPSK
AUQPSK
OQPSK
OQPSK
UQPSK
UQPSK
DPM
Digital Phase Modulation
STC
Space Time Coding
SOQPSKLDPC
SOQPSK with Low Density Parity Check (LDPC) Decoder
STCLDPC
Space Time Coding with Low Density Parity Check
Note:
Changing modes causes the receiver to reload the FPGA, which takes approximately twelve (12) seconds to
complete. A ‘Please Wait’ message displays on the front panel display screen to indicate that the unit is being re
-
configured. The unit is temporarily unavailable during this time.
4.4.2.3.1 AQPSK Mode
Note that AQPSK mode results in two independent bit streams out of the RDMS. The I data is available on the
normal clock and data outputs, but the Q data is only available on an MDM connector unless the user has a 3U
receiver. Refer to Table 5 for connector/pin information for I data outputs (Clock A and Data A) and Q data outputs
(Clock B and Data B).
Figure 27: Main Menu, Bit Rate A and B Settings
4.4.2.4
Bit Rate
There are two methods available to the user to set the receiver’s bit rate. The first one is to press the Rate key on the
front panel keypad. The second method is to highlight the Bit Rate option on the Main Menu, then press the Enter
key on the PC keyboard.
