EPAQ-9410
Hardware Programming Reference 0.16
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Copyright © 2019 QEI
Page 16
FP_DIP_SW2: DIP switch SW1-2
0 = ON (down)
1 = OFF (up)
FP_DIP_SW3: DIP switch SW1-3
0 = ON (down)
1 = OFF (up)
FP_DIP_SW4: DIP switch SW1-4
0 = ON (down)
1 = OFF (up)
3.7.9
AD CPLD Revision Register
Register Name: AD_REVISION
Address: 0xB403_0018
Access type: read-only
7
6
5
4
3
2
1
0
AD_REVISION
AD_REVISION: AD CPLD Revision
3.8 QUAD UARTS
Two SC16C754B QUAD UARTS.
The SC16C754B is a quad Universal Asynchronous Receiver/Transmitter (UART) with
64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s
(3.3 V and 5 V).
QUAD UART 1 (U1), controls RS-232-485_PORT1, RS-232-485_PORT2, RS-232-
485_PORT3 and RS-232-485_PORT4 ports.
QUAD UART 2 (U7), controls CH7, CH8, CH9 and COM_EXP ports.
Start
End
Size
Description
0xB400_0000
0xB400_0007
8 Bytes
QUAD UART 1, Channel A
0xB400_0008
0xB400_000F
8 Bytes
QUAD UART 1, Channel B
0xB400_0010
0xB400_0017
8 Bytes
QUAD UART 1, Channel C
0xB400_0018
0xB400_001F
8 Bytes
QUAD UART 1, Channel D
0xB400_0020
0xB400_0027
8 Bytes
QUAD UART 2, Channel A
0xB400_0028
0xB400_002F
8 Bytes
QUAD UART 2, Channel B
0xB400_0030
0xB400_0037
8 Bytes
QUAD UART 2, Channel C
0xB400_0038
0xB400_003F
8 Bytes
QUAD UART 2, Channel D
Under Linux, the individual channels of QUAD UART are mapped to devices as follows:
Channel
Linux name
QUAD UART 1, Channel A /dev/sttyS0
GPIO_1_9
