EPAQ-9410
Hardware Programming Reference 0.16
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Copyright © 2019 QEI
Page 28
Access type: read-only
Reading the CH_TXD2 register returns the momentary state of the CPLD pins as
described in the table below
7
6
5
4
3
2
1
0
COM_EXP_TXD
CH15_TXD
CH14_TXD
IRIG_FIBER_TX
IRIG_B_RS485_TXD
CH11_TXD
CH10_TXD
CH9_TXD
3.11.5 CH_RTS Status Register
Register Name: CH_RTS_STS
Addresses: 0xB408_0024
Access type: read-only
Reading the CH_RTS register returns the momentary state of the CPLD pins as described
in the table below
7
6
5
4
3
2
1
0
0
0
MODEM_2_DET
MODEM_1_DET
CH4_RTS#
CH3_RTS#
CH2_RTS#
CH1_RTS#
3.12 System Reset & Watchdog Timer
The ePAQ-9410 utilizes a watchdog timer / power-on reset circuit. The functions of this
circuit are to provide:
a)
Initial power-on reset of all circuitry
b)
Protection against runaway processor
c)
Full power-on restart in case of watchdog timeout
This functionality is supported by hardware circuitry on both the Proc Full and Mother
Boards as well as software interaction.
The watchdog timer can operate in two switch selectable modes:
a)
Normal mode – watchdog enabled
b)
Bypass mode – watchdog disabled
The selection of watchdog mode is performed by pole 2 of configuration switch U1 on
the Proc Full board.
3.12.1 Watchdog Normal Mode
This mode is selected by pole #2 of configuration switch U1 in the open (off) position. In
this mode the CPU shall provide a strobe to the watchdog timer U31 every 1.6 seconds
maximum via GPIO pin 3-9 (signal WDOG_COLD#). The watchdog function is
controlled by U31 on the Proc Full board, a MicroChip MCP1320T-29.
During application of power from the Mother Board U31 will detect the rising edge of
the +3.3V supply voltage. At 1V the RST# pin will go active low. After the +3.3V supply
rail reaches 2.90V, the RST# pin will remain active for 200mS min (140mS min, 280mS
max).
On removal of power, the RST# pin will go active low when the +3.3V rail reaches
2.657V.
