EPAQ-9410
Hardware Programming Reference 0.16
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Copyright © 2019 QEI
Page 11
Pad Pad name
Function
GPIO
T3
ATA_DMARQ
BB0_TXD
GPIO2_31
T5
ATA_BUFF_EN
BB1_RXD
GPIO2_30
3.3 SDRAM
LowPowerDDR1 SDRAM, 64Meg by 16 bits, 1.8 Volts, Micron MT46H64M16LFBF-
6 IT:B MT46H64M16LFBF-6 IT:B -40C TO 85C 10-057931-001 60-VFBGA
MT46H64M16LF – 16 Meg x 16 x 4 banks (=64 Meg x 16 = 128 MBytes)
From the processor perspective, the SDRAM is arranged as two banks of 32-bit SDRAM,
256 MBytes each. 0x80000000 and 0x90000000 are the starting addresses of the memory
banks. There is no gap between the banks and the SDRAM can be viewed as a
continuous region of 512 MBytes
During normal, NOR flash boot, the SDRAM and the SDRAM memory controller is
initialized by u-boot bootloader during early stages of the boot process.
board/pcm043/lowlevel_init.S
u-boot passes SDRAM memory layout to Linux kernel via memory based arguments
(ATAG_MEM method). Observe messages during u-boot to confirm layout:
## Transferring control to Linux (at address 0x80008000) ...
Memory: 80000000[10000000]
Memory: 90000000[10000000]
Starting kernel ...
Potentially, there is an advantage for Linux to work with one continuous memory region
instead of two memory regions. Not sure if Linux is smart enough to figure out if the
memory regions are adjacent.
3.4 NOR Flash
We have 2 x
S29GL512P (512 Megabit) at CS0# and CS1#
starting at 0xA0000000 and 0xA8000000, respectively
512 Megabit = 64 MBytes
3.5 NAND flash
2 x MT29F4G08ABADAWP-IT_D
2 x 4Gb for 512MBytes total
The hardware design supports a stuffing option when a more dense flash part could be
placed into U6, for example MT29F16G08AJADAWP, at the expense of second NOR
flash chip in U13. This configuration was not thoroughly reviewed or tested.
