EPAQ-9410
Hardware Programming Reference 0.16
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Copyright © 2019 QEI
Page 19
The table below summarizes supported values for IRIG_FIBER_TX_SEL register.
Value
Description
0x0
0, IRIG_FIBER_TX_NI signal is driven low
0x1
IRIG_FIBER_TX_NI = IRIG_FIBER_RX_NI
0x2
IRIG_FIBER_TX_NI = IRIG_SIGNAL_BUS
0x3
IRIG_FIBER_TX_NI = CH8_TXD
0x4
IRIG_FIBER_TX_NI = (CH8_RTS_L) ? (IRIG_FIBER_RX_NI) :
(CH8_TXD)
0x5-0x7
reserved for future use, IRIG_FIBER_TX_NI is driven low
The IRIG_FIBER_TX_INV bit allow for optional inversion of the
IRIG_FIBER_TX/IRIG_FIBER_RX signals as specified below:
IRIG_FIBER_TX_INV
0:
IRIG_FIBER_TX/IRIG_FIBER_RX are not inverted
1:
IRIG_FIBER_TX/IRIG_FIBER_RX are inverted
3.10.3 IRIG-B_RS485_TXD Register
Register Name: IRIG_B_RS485_TXD
Address: 0xB402_0002
Access type: write-only
3
2
1
0
IRIG_FIBER_TXD_SEL
The IRIG_B_RS485_TXD register controls the configuration of the IRIG-
B_RS485_TXD and IRIG-B_RS485_DRV_EN# signals. The RIG-B_RS485_DRV_EN#
signal is the “driver enable” signal for IRIG-B RS-485 isolated port J7-B.
The table below summarizes supported values for IRIG_B_RS485_TXD register.
Value
Description
0x0
Disabled/Irig-In:
{IRIG_B_RS485_TXD, IRIG_B_RS485_DRV_EN_L} = {1'b1, 1'b1};
0x1
reserved/unused
0x2
TEST0:
{IRIG_B_RS485_TXD, IRIG_B_RS485_DRV_EN_L} = {1'b0, 1'b0};
0x3
TEST1:
{IRIG_B_RS485_TXD, IRIG_B_RS485_DRV_EN_L} = {1'b1, 1'b0};
0x4
IrigOut:
{IRIG_B_RS485_TXD, IRIG_B_RS485_DRV_EN_L} =
{IRIG_SIGNAL_BUS, 1'b0};
0x5
~IrigOut:
{IRIG_B_RS485_TXD, IRIG_B_RS485_DRV_EN_L} =
{~IRIG_SIGNAL_BUS, 1'b0};
0x6
CH8:
{IRIG_B_RS485_TXD, IRIG_B_RS485_DRV_EN_L} =