EPAQ-9410
Hardware Programming Reference 0.16
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Copyright © 2019 QEI
Page 29
While in the Normal Mode, the watchdog IC, U31, must be strobed by GPIO 3-9 no less
frequently than every 1.6S to avoid a time-out and subsequent reset. However, this time-
out function will commence with the first strobe after power-on. Therefore, there is no
time-out until the first strobe is applied. Multiplexer U15 selects the GPIO 3-9 signal
(WDOG_COLD#), as directed by configuration switch pole #2, to be the strobe to the
watchdog timer IC, U31.
3.12.2 Bypass Mode
This mode is selected by pole #2 of configuration switch U1 is in the closed (on)
position. This selects the output of free-running oscillator, U15, to strobe the watchdog
U31 so that no processor interaction is required. U29, a LM555 timer IC, provides a
400mS cycle time strobe signal. Multiplexer U15 selects the output of U29, as directed
by configuration switch pole #2, to be the strobe to the watchdog timer IC, U31.
LED D1 on the Proc Full board will be illuminated to indicate that the Watchdog Bypass
mode is in effect.
3.12.3 Power-On Restart
In either mode above, circuitry on the Mother Board can be configured to remove the
+3.3V power supply rail from the Proc Full board, thereby resulting in a full power-on
restart to the CPU.
This function is controlled by a second MCP1320T U124, inverter U125 and FET Q10,
all located on the Mother Board.
If this function is desired R230 (currently DNI on the BOM) must be populated. For test
JP1 may be connected pin1 to pin 2 with a jumper wire.
When R230 is inserted, the circuit functions as follows:
The signal WDI_B from the Proc Full board (either the free-running oscillator or the
strobe from the CPU) triggers the watchdog timer U124 on the Mother Board. In bypass
mode the free-running oscillator U15 on the ProcFull board will hold off the watchdog
timer on the Mother Board. In normal mode, the first strobe enables the watchdog timer
on the Mother Board. In the event of the loss of such strobes, the watchdog timer on the
Mother Board times out and generates its own reset pulse. Inverter U125 changes the
asserted level to high which turns on Q10. This pulls low R230 which disables the output
of the +3.3V DC/DC regulator U81. Within 20mS the +3.3V supply rail goes to 0V. The
reset pulse is 200mS min (140mS min, 280mS max). Thus the +3.3V rail to CPU
ProcFull board will be at 0V for 120mS min. This is sufficient to provide a hard power-
on restart to the CPU.
Note that U124 & U125 are powered from +5V, not affected by this power-on restart.
Should the CPU be unable to hold off the watchdog on the ProcFull board, the above
process will be repeated approx every 1.6S (1.12S min, 2.4S max). This will result in
