QEI ePAQ-9410, User Manual

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EPAQ-9410 Hardware Programming Reference 0.16
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Copyright © 2019 QEI
Page 7
1 Introduction
This document describes hardware functionality of ePAQ-9410 ProcFull board Rev B
and ePAQ-9410 Mother Board Rev B.
2 References
1. ePAQ-9410/9420 Multifunction Gateway Functional Specification, 05-055104-
001 ePAQ-94XX MultiFunction Gateway Spec Rev H13.pdf, REV.H13,
6/27/2011
2. eXP-9430 Comm Port Expander Functional Specification, 05-055111-001 eXP-
9430 Comm Port Expander Rev. E.pdf, Rev.E
3 Blocks
3.1 Processor
3.1.1 Memory Map
Start End Size Description
0xA000_0000 0xA3FF_FFFF 64Mbytes NOR Flash 1 on
CS0
0xA400_0000 0xA7FF_FFFF 64Mbytes CS0, (aliased to
NOR Flash 1?)
0xA800_0000 0xABFF_FFFF 64Mbytes NOR Flash 2
0xAC00_0000 0xAFFF_FFFF 64Mbytes CS1, (aliased to
NOR Flash 2?)
0xB400_0000 0xB5FF_FFFF 32 MBytes WEIM CS4,
Address Decode
CPLD
3.1.2 CPU GPIO Signal Usage
Pin # Signal Name Used On I/O Comment
L20 GPIO_1_0 ProcFull Drives Diag LED 0, high active
L16 GPIO_1_1 MotherBoard Not used
M19 GPIO_1_2 MotherBoard Drives Diag LED 2, high active
M17 GPIO_1_3 MotherBoard Drives Diag LED 3, high active
V12 CAPTURE_GPIO1-4 MotherBoard Goes to Serial Routing CPLD
J4 GPIO_1_7 ProcFull Drives Diag LED 4, high active
J1 GPIO_1_8 ProcFull Drives Diag LED 5, high active
J5 GPIO_1_9 MotherBoard QUART U1 INTA
H1 GPIO_1_14 ProcFull Drives Diag LED 6, high active
G4 GPIO_1_15 ProcFull Drives Diag LED 7, high active