EPAQ-9410
Hardware Programming Reference 0.16
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Copyright © 2019 QEI
Page 18
0x1F
reserved
3.10.1 IRIG-B Bus Register
Register Name: IRIG_SIGNAL_BUS_SEL
Address: 0xB402_0000
Access type: write-only
3
2
1
0
IRIG_SIGNAL_BUS_SEL
The IRIG_SIGNAL_BUS_SEL register controls the configuration of the
IRIG_SIGNAL_BUS signal internal to the SR CPLD. The external IRIG_B-RS-485
signal is always driven by the internal IRIG_SIGNAL_BUS signal and can be configured
to be transmitted on RS-232-485_PORT[1..4] ports connected to QUAD UART 1. See
CH[1..4]_CFG registers of LED Monitor CPLD.
The table below summarizes supported values for IRIG_SIGNAL_BUS_SEL register.
Value
Description
0x0
0, IRIG_SIGNAL_BUS signal is driven low
0x1
IRIG_SIGNAL_BUS = IRIG_FIBER_RX_NI
0x2
IRIG_SIGNAL_BUS = ~IRIG_FIBER_RX_NI
0x3
IRIG_SIGNAL_BUS = IRIG_COAX_IN
0x4
IRIG_SIGNAL_BUS = IRIG_B_RS485_RXD
0x5
IRIG_SIGNAL_BUS = ~IRIG_B_RS485_RXD
0x6
IRIG_SIGNAL_BUS = GPIO_MICRO_IRIG_IN, IRIG_SIGNAL_BUS is
controlled by processor’s GPIO 2-19
0x7
IRIG_SIGNAL_BUS = CH8_TXD, QUAD UART 2, CH B TDX signal
0x8
IRIG_SIGNAL_BUS = 1, IRIG_SIGNAL_BUS is driven high
0x9-0xF
reserved for future use, IRIG_SIGNAL_BUS is driven low
3.10.2 IRIG_FIBER_TX Register
Register Name: IRIG_FIBER_TX_SEL
Address: 0xB402_0001
Access type: write-only
3
2
1
0
IRIG_FIBER_TX_INV
IRIG_FIBER_TX_SEL
The IRIG_FIBER_TX_SEL bits controls the configuration of the IRIG_FIBER_TX_NI
signal internal to the SR CPLD. The IRIG_FIBER_TX_NI is the Non-Inverted
counterpart of the IRIG_FIBER_TX signal. Similarly, the IRIG_FIBER_RX_NI is the
non-inverted counterpart of the IRIG_FIBER_RX signals.