EPAQ-9410
Hardware Programming Reference 0.16
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Copyright © 2019 QEI
Page 26
0x31
CH_RXD2 Monitor
CH_RXD2_MON
read-only
--
0x32
CH_TXD Monitor
CH_TXD_MON
read-only
--
0x33
CH_TXD2 Monitor
CH_TXD2_MON
read-only
--
0x34
CH_RTS Monitor
CH_RTS_MON
read-only
--
All XXX_STS registers return the current state of the corresponding pin of CPLD. All
XXX_MON registers function as follows:
Each bit is set when the corresponding line goes active. When the register is read, the bits
returned indicate lines that have been active since the previous read. "Active" indicates
that the line was in its active state, not its idle state.
For example, if a signal goes active (once) and then goes back inactive, the next read will
return a 1, the subsequent immediate read will return a 0. If a signal goes active and stays
active, all reads will return a 1 for as long as signal is still active.
RTS signals are considered to be active low.
RS232 related TX and RX signals are considered inactive when no characters are
transmitted: inactive = “idle” == “mark” == ‘bit value 1”, active = “space” == “bit value
0” = “start bit” = “break”.
RS232/RS485 CHn Configuration Register
Register Name: CH[1..4]_CFG
Addresses: [1]: 0xB408_0001, [2]: 0xB408_0002, [3]: 0xB408_0003, [4]: 0xB408_0004
Access type: write-only
7
6
5
4
3
2
1
0
RS485_DRV_CFG TX_SEL
MOD_SEL
MOD_SEL: Mode Select
0 = RS485 mode
1 = RS232 mode
TX_SEL: RS485 TX Select
0 = QUAD UART1 CHn_TXD
1 = IRIG_B_RS485
RS485_DRV_CFG: RS485 Driver Enable Configuration
00b – RS485 Driver Disabled
01b – RS485 Driver Enabled
10b – RS485 Driver Enable is controlled by CHn_RTS# QUAD UART output; RS485
driver is enabled when CHn_RTS# is active/asserted (logic 0), RS485 driver is disabled
when CHn_RTS# is inactive/deasserted (logic 1)
11b – Reserved, RS485 Driver Disabled
