EPAQ-9410
Hardware Programming Reference 0.16
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Copyright © 2019 QEI
Page 10
These boot modes are among many possible boot modes and configurations supported by
IMX357 CPU. The ePAQ-9410 design only supports the boot modes listed above. The
supported boot modes are selected by the configuration switch U1.
NOR FLASH Boot Mode
Signal
Logic Level
Switch Position
BOOT_MODE0
0
U1 pole 7 = closed (on)
BOOT_MODE1
1
U1 pole 3 = closed (on)
MEM_CTL0
0
U1 pole 4 = open (off)
MEM_CTL1
0
U1 pole 5 = open (off)
Serial Download Boot Mode
Signal
Logic Level
Switch Position
BOOT_MODE0
1
U1 pole 7 = open (off)
BOOT_MODE1
1
U1 pole 3 = closed (on)
MEM_CTL0
0
U1 pole 4 = open (off)
MEM_CTL1
0
U1 pole 5 = open (off)
Startup/JTAG Boot Mode
Signal
Logic Level
Switch Position
BOOT_MODE0
1
U1 pole 7 = open (off)
BOOT_MODE1
0
U1 pole 3 = open (off)
MEM_CTL0
0
U1 pole 4 = open (off)
MEM_CTL1
0
U1 pole 5 = open (off)
This boot mode will not execute the IMX357’s internal boot ROM. A compatible JTAG
emulator may be used to load and execute application code.
3.2.1
CAPTURE and COMPARE
These signals are intended to be used for the two receive lines of the bit-bang
interface. Although one is labeled "CAPTURE" and the other "COMPARE", in fact,
both of these would potentially be used as capture inputs.
The idea is that for the Bit-Bang receiver, we have the option of using the
input capture hardware to give us an accurate time-of-transition on the
received signal (which then can be translated into bit times).
The processor pads CAPTURE and COMPARE can also be used as GPIO’s:
Pad Pad name
Function
GPIO
V12 CAPTURE
BB0_RXD
GPIO1_4
T12 COMPARE
BB1_RXD
GPIO1_5
3.2.2
GPIO_BIT_BANG_OUT_CH[0,1]
These signals are intended to be used for the two transmit lines of the bit-bang
interface as follows:
