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EPAQ-9410

Hardware Programming Reference 0.16

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Copyright © 2019 QEI

Page 6

Revision History

Revision

Date

Author

Description

0.01

1/7/2012

Initial revision

0.02

1/19/2012 KE

Updated CPLD sections

0.03

1/24/2012 KS

Added CPU GPIO Signal Usage section

0.04

1/24/12

Updated CPLD sections, added REVISION registers

0.05

2/9/12

Added descriptions for boot modes, watch-dog and
initial programming via serial port

0.07

2/27/12

Updated CPLD registers and versions
added I2C section

0.08

3/1/12

updated SR CPLD section

0.09

3/1/12

updated AD and LM CPLD sections

0.10

3/7/12

updated SR CPLD section

0.11

3/20/12

added “boot modes”, “CAPTURE and COMPARE”,
GPIO_BIT_BANG_OUT_CH[0,1]

0.12

10/18/12

updated NAND flash section

0.13

10/19/12

bring-up procedure WIP

0.16

10/3/19

CPLD/USB/Ethernet enables

Summary of Contents for ePAQ-9410

Page 1: ...EPAQ 9410 Hardware Programming Reference 0 16 ________________________________________________________________________ ePAQ 9410 Hardware Programming Reference 0 16 User s Manual October 2019 ...

Page 2: ...plied for inaccuracies Further more QEI reserves the right to make changes to any products herein described to improve reliability function or design QEI does not assume liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others This manual and all data contained constitute proprieta...

Page 3: ...6 ________________________________________________________________________ ________________________________________________________________________ Copyright 2019 QEI Page 2 Revisions Revision Description Date A Release to Production October 2019 ...

Page 4: ...ister 14 3 7 4 L3 LED Register 14 3 7 5 L4 LED Register 14 3 7 6 SW10 High IP Address Register 15 3 7 7 SW11 Low IP Address Register 15 3 7 8 Option DIP Switch Register 15 3 7 9 AD CPLD Revision Register 16 3 8 QUAD UARTS 16 3 9 DUART 17 3 10 Serial Routing CPLD 17 3 10 1 IRIG B Bus Register 18 3 10 2 IRIG_FIBER_TX Register 18 3 10 3 IRIG B_RS485_TXD Register 19 3 10 4 IRIG B_OUTPUT_TO_MICRO Regis...

Page 5: ...Server 31 4 2 Install additional files 32 5 Bring up procedure 32 5 1 Equipment list 32 5 2 Visual inspection 33 5 3 ePAQ 9410 Motherboard Initial Power Up 34 5 4 ePAQ 9410 ProcFull Initial Power Up 35 5 5 Initial programming 35 5 6 CPLD programming 35 5 7 Modem ports 36 5 7 1 CH 1 TX CH 2 RX configuration 36 5 7 2 CH 2 TX CH 1 RX configuration 36 5 7 3 LED s test 37 5 8 RS232 RS485 Ports 37 5 8 1...

Page 6: ...gramming Reference 0 16 ________________________________________________________________________ ________________________________________________________________________ Copyright 2019 QEI Page 5 5 21 RTC 47 5 22 Supercap 47 ...

Page 7: ...gnal Usage section 0 04 1 24 12 KE Updated CPLD sections added REVISION registers 0 05 2 9 12 KE Added descriptions for boot modes watch dog and initial programming via serial port 0 07 2 27 12 KE Updated CPLD registers and versions added I2C section 0 08 3 1 12 KE updated SR CPLD section 0 09 3 1 12 KE updated AD and LM CPLD sections 0 10 3 7 12 KE updated SR CPLD section 0 11 3 20 12 KE added bo...

Page 8: ... End Size Description 0xA000_0000 0xA3FF_FFFF 64Mbytes NOR Flash 1 on CS0 0xA400_0000 0xA7FF_FFFF 64Mbytes CS0 aliased to NOR Flash 1 0xA800_0000 0xABFF_FFFF 64Mbytes NOR Flash 2 0xAC00_0000 0xAFFF_FFFF 64Mbytes CS1 aliased to NOR Flash 2 0xB400_0000 0xB5FF_FFFF 32 MBytes WEIM CS4 Address Decode CPLD 3 1 2 CPU GPIO Signal Usage Pin Signal Name Used On I O Comment L20 GPIO_1_0 ProcFull Drives Diag ...

Page 9: ...G_IN IRIG B source for SR CPLD Y3 GPIO_2_20 MotherBoard I IRIG B_OUTPUT_TO_MICRO IRIG B input to uP W1 GPIO_2_27 MotherBoard Not used T4 GPIO_2_28 MotherBoard SD_CARD_DET V2 GPIO_2_29 CommExpander COMM_EXP_RESET T5 GPIO_2_30 MotherBoard GPIO_BIT_BANG_OUT_CH1 T3 GPIO_2_31 MotherBoard GPIO_BIT_BANG_OUT_CH0 R4 GPIO_3_0 ProcFull Not used V1 GPIO_3_1 MotherBoard Not used R5 GPIO_3_2 MotherBoard Not use...

Page 10: ...0K only used when BT_MEM_CTRL 1 0 b01 NAND boot not used in our design V15 CSI_D13 BT_PAGE_SIZE 1 100 10K U14 CSI_D14 BT_ECC_SEL 100 10K If the bootable device is MMC then 0 Don t use eMMC fast boot mode 1 Use eMMC fast boot mode not relevant T14 CSI_VSYNC BT_BUS_WIDTH 100 10K BT_MEM_CTL 1 0 00 0 16 bit 1 Reserved however this refers to functionality during internal boot mode only which we are not...

Page 11: ...ot Mode Signal Logic Level Switch Position BOOT_MODE0 1 U1 pole 7 open off BOOT_MODE1 0 U1 pole 3 open off MEM_CTL0 0 U1 pole 4 open off MEM_CTL1 0 U1 pole 5 open off This boot mode will not execute the IMX357 s internal boot ROM A compatible JTAG emulator may be used to load and execute application code 3 2 1 CAPTURE and COMPARE These signals are intended to be used for the two receive lines of t...

Page 12: ...SDRAM memory controller is initialized by u boot bootloader during early stages of the boot process board pcm043 lowlevel_init S u boot passes SDRAM memory layout to Linux kernel via memory based arguments ATAG_MEM method Observe messages during u boot to confirm layout Transferring control to Linux at address 0x80008000 Memory 80000000 10000000 Memory 90000000 10000000 Starting kernel Potentially...

Page 13: ... for future use 0xB40B_0000 0xB40B_0000 reserved for future use 0xB40C_0000 0xB40C_0000 reserved for future use 0xB40D_0000 0xB40D_0000 reserved for future use 0xB40E_0000 0xB40E_0000 reserved for future use 0xB40F_0000 0xB40F_0000 reserved for future use 0xB410_0000 0xB410_0000 reserved for future use 0xB41F_0000 0xB41F_0000 reserved for future use Register summary at 0xB401_0000 Offset Register ...

Page 14: ...x12 Option DIP Switch OPTION_DIP_SWITCH read only 0x18 AD CPLD Revision AD_REVISION read only 0x01 TP107 Ethernet Port Chip Forced LOW always to enable serial programming None 0x0 3 7 1 Heartbeat Register Register Name HEARTBEAT_L Address 0xB401_000F Access type write only 7 6 5 4 3 2 1 0 LED_OFF Heartbeat LED is the top row left column LED in the 2 rows by 3 columns LED array located on the ePAQ ...

Page 15: ...lumns LED array located on the ePAQ 9410 front panel 7 6 5 4 3 2 1 0 LED_OFF LED_OFF LED control 0 LED on 1 LED off 3 7 4 L3 LED Register Register Name LED_3 Address 0xB401_0012 Access type write only L3 LED is the bottom row middle column LED in the 2 rows by 3 columns LED array located on the ePAQ 9410 front panel 7 6 5 4 3 2 1 0 LED_OFF LED_OFF LED control 0 LED on 1 LED off 3 7 5 L4 LED Regist...

Page 16: ..._4 SW10_3 SW10_2 SW10_1 SW10_ 1 8 DIP switch SW10 1 8 0 ON left 1 OFF right 3 7 7 SW11 Low IP Address Register Register Name IP_CSR_2 Address 0xB403_0001 Access type read only Refers to SW11 eight DIP switches SW10 is in front SW11 7 6 5 4 3 2 1 0 SW11_8 SW11_7 SW11_6 SW11_5 SW11_4 SW11_3 SW11_2 SW11_1 SW11_ 1 8 DIP switch SW11_ 1 8 0 ON left 1 OFF right 3 7 8 Option DIP Switch Register Register N...

Page 17: ...FOs automatic hardware software flow control and data rates up to 5 Mbit s 3 3 V and 5 V QUAD UART 1 U1 controls RS 232 485_PORT1 RS 232 485_PORT2 RS 232 485_PORT3 and RS 232 485_PORT4 ports QUAD UART 2 U7 controls CH7 CH8 CH9 and COM_EXP ports Start End Size Description 0xB400_0000 0xB400_0007 8 Bytes QUAD UART 1 Channel A 0xB400_0008 0xB400_000F 8 Bytes QUAD UART 1 Channel B 0xB400_0010 0xB400_0...

Page 18: ...rite only 0x0 0x02 IRIG B_RS485_TXD IRIG_B_RS485_TXD_SEL write only 0x0 0x03 IRIG B_OUTPUT_TO_MICRO IRIG_B_OUTPUT_TO_MICRO_SEL write only 0x0 0x04 unused 0x05 IRIG B_MOD_OUT_EN_H IRIG_B_MOD_OUT_EN_H write only 0x0 0x06 CH8_RXD CH8_RXD_SEL write only 0x0 0x07 COM_EXP_IRIG B COM_EXP_IRIG_B_SEL write only 0x0 0x08 Telco 1 Mode CH14_SEL write only 0x0 0x09 Telco 1 Control CH14_CTRL read write 0x0A Tel...

Page 19: ..._SIGNAL_BUS_SEL register Value Description 0x0 0 IRIG_SIGNAL_BUS signal is driven low 0x1 IRIG_SIGNAL_BUS IRIG_FIBER_RX_NI 0x2 IRIG_SIGNAL_BUS IRIG_FIBER_RX_NI 0x3 IRIG_SIGNAL_BUS IRIG_COAX_IN 0x4 IRIG_SIGNAL_BUS IRIG_B_RS485_RXD 0x5 IRIG_SIGNAL_BUS IRIG_B_RS485_RXD 0x6 IRIG_SIGNAL_BUS GPIO_MICRO_IRIG_IN IRIG_SIGNAL_BUS is controlled by processor s GPIO 2 19 0x7 IRIG_SIGNAL_BUS CH8_TXD QUAD UART 2...

Page 20: ...RIG_FIBER_TX IRIG_FIBER_RX are not inverted 1 IRIG_FIBER_TX IRIG_FIBER_RX are inverted 3 10 3 IRIG B_RS485_TXD Register Register Name IRIG_B_RS485_TXD Address 0xB402_0002 Access type write only 3 2 1 0 IRIG_FIBER_TXD_SEL The IRIG_B_RS485_TXD register controls the configuration of the IRIG B_RS485_TXD and IRIG B_RS485_DRV_EN signals The RIG B_RS485_DRV_EN signal is the driver enable signal for IRIG...

Page 21: ...CRO_SEL register controls the configuration of the IRIG B_OUTPUT_TO_MICRO signal The table below summarizes supported values for the IRIG_B_OUTPUT_TO_MICRO_SEL register Value Description 0x0 0xF reserved for future use IRIG B_OUTPUT_TO_MICRO IRIG_SIGNAL_BUS 3 10 5 IRIG B_MOD_OUT_EN_H Register Register Name IRIG B_MOD_OUT_EN_H Address 0xB402_0005 Access type write only 3 2 1 0 IRIG_B_MOD_OUT_EN_H T...

Page 22: ...nnected to IRIG_B_RS485_RXD CH8_RXD CH8_CTS_L IRIG_B_RS485_RXD 1 b0 0x3 loopback CH8_RXD CH8_CTS_L CH8_TXD CH8_RTS_L 0x4 0xF same as 0 but de assert CTS CH8_RXD CH8_CTS_L 1 b1 1 b1 3 10 7 COM_EXP_IRIG B Register Register Name COMM_EXP_IRIG_B_SEL Address 0xB402_0007 Access type write only 3 2 1 0 COMM_EXP_IRIG_B_SEL The COMM_EXP_IRIG_B_SEL register controls the configuration of the COMM_EXP_IRIG B ...

Page 23: ...sserted M0 0 M1 1 and PTT is de asserted 0x2 MODEM is controlled by a Bit Bang channel MODEM 1 is always controlled by the Bit Bang CH 0 MODEM 2 is always controlled by the Bit Bang CH 1 PTT M0 M1 are controlled by BB 0 1 _RTS signal When RTS is de asserted M0 0 M1 1 and PTT is de asserted 0x4 debug test mode MODEM is controlled by TELCO_ 1 2 _CTRL register 0x3 0x5 0xF reserved for future use same...

Page 24: ... controlled by a Bit Bang channel RS232 port 1 is always controlled by the Bit Bang CH 0 RS232 port 2 is always controlled by the Bit Bang CH 1 CH 10 11 _TXD CH 10 11 _RTS_L CH 10 11 _TXCLK BB 0 1 _TXD BB 0 1 _RTS_L 1 b0 0x3 0xF disabled CH 10 11 _TXD CH 10 11 _RTS_L CH 10 11 _TXCLK 1 b1 1 b1 1 b0 3 10 11 Bit Bang CH 0 1 Register Register Name BB 0 1 _SEL Address 0 0xB402_000E 1 0xB402_000F Access...

Page 25: ...s type write only 3 2 1 0 DUART_CH A B _SEL The DUART_CH A B _SEL register controls the configuration of the DUART CH A and DUART CH B related signals The table below summarizes supported values for DUART_CH A B _SEL field Value Description 0x0 not routed DUART_CH A B _RXD DUART_CH A B _CTS_L CH 10 11 _RXCLK_IN 1 b1 1 b0 1 b0 0x1 RS232 routing DUART_CH A B _RXD DUART_CH A B _CTS_L CH 10 11 _RXCLK_...

Page 26: ...dress map base is at 0xB408_0000 Offset Register Name Access Reset 0x00 reserved 0x01 RS232 RS485 CH1 Configuration Register CH1_CFG write only 0x00 0x02 RS232 RS485 CH2 Configuration Register CH2_CFG write only 0x00 0x03 RS232 RS485 CH3 Configuration Register CH3_CFG write only 0x00 0x04 RS232 RS485 CH4 Configuration Register CH4_CFG write only 0x00 0x05 CH5_HLF_DPLX_EN_H CH5_HLF_DPLX_EN_H write ...

Page 27: ...ext read will return a 1 the subsequent immediate read will return a 0 If a signal goes active and stays active all reads will return a 1 for as long as signal is still active RTS signals are considered to be active low RS232 related TX and RX signals are considered inactive when no characters are transmitted inactive idle mark bit value 1 active space bit value 0 start bit break RS232 RS485 CHn C...

Page 28: ...ess type read only Reading the CH_RXD register returns the momentary state of the CPLD pins as described in the table below 7 6 5 4 3 2 1 0 0 CH7_RXD UART3_RXD UART2_RXD CH4_RXD CH3_RXD CH2_RXD CH1_RXD 3 11 2 CH_RXD2 Status Register Register Name CH_RXD2_STS Addresses 0xB408_0021 Access type read only Reading the CH_RXD2 register returns the momentary state of the CPLD pins as described in the tab...

Page 29: ...b Protection against runaway processor c Full power on restart in case of watchdog timeout This functionality is supported by hardware circuitry on both the Proc Full and Mother Boards as well as software interaction The watchdog timer can operate in two switch selectable modes a Normal mode watchdog enabled b Bypass mode watchdog disabled The selection of watchdog mode is performed by pole 2 of c...

Page 30: ...V power supply rail from the Proc Full board thereby resulting in a full power on restart to the CPU This function is controlled by a second MCP1320T U124 inverter U125 and FET Q10 all located on the Mother Board If this function is desired R230 currently DNI on the BOM must be populated For test JP1 may be connected pin1 to pin 2 with a jumper wire When R230 is inserted the circuit functions as f...

Page 31: ...nufacturing Software 4 1 Initial Programming via Serial Port Freescale provides a programming utility called Advanced Toolkit Advanced Toolkit V1 17 from Freescale was customized to work with ePAQ 9410 ProcFull board The customized Advanced Toolkit Utility is used to program U Boot and U Boot environment into the NOR Flash via Serial Boot mode Once the U Boot is programmed the board is booted norm...

Page 32: ...The board should boot and display U Boot sign on message and U Boot command prompt 4 1 1 NOR Flash programming via TFTP Server The TFTP server can be setup in several ways Linux TFTP server with Linux physical machine or VMWare virtual machine Windows TFTP server For Windows TFTPD32 from http tftpd32 jounin net has been tested To setup TFTPD32 server follow regular installation instructions for TF...

Page 33: ...th0 netmask 255 255 255 0 eth0 gateway 192 168 24 1 eth0 serverip 192 168 24 113 To update program Linux kernel type update_kernel nor imagename at U Boot command prompt For example update_kernel nor uImage 2 6 39 RevC oe svn95 To update program Linux Root Filesystem type update_rootfs nor imagename at U Boot command prompt for example update_rootfs nor root 2 6 39 RevC oe svn95 jffs2 reboot the s...

Page 34: ... A6 B5 C6 D5 IRIG RS485 to Quad RS232 Loopback J7 B RJ45 J2 A RJ45 J2 B RJ45 J2 C RJ45 J2 D RJ45 B7 A7 B7 C7 D7 B8 A8 B8 C8 D8 A1 to A2 B1 to B2 C1 to C2 D1 to D2 A3 to A4 B3 to B4 C3 to C4 D3 to D4 RS232 CROSSOVER J8 A RJ45 J8 B RJ45 A1 B2 A2 B1 A3 B4 A4 B3 A6 B7 A7 B6 5 2 Visual inspection Check the general quality of the solder connections Check for solder bridges Check for unsoldered pins and ...

Page 35: ...or 2 0V measure across C155 PASS FAIL For USB1_VCC5V measure across C270 PASS FAIL For USB1_3V3 measure across C157 PASS FAIL For USB 1_8V measure across C168 PASS FAIL For USB_IO_ 3V3 measure across C321 PASS FAIL For VCC_ISO_5V_IRIG_485 measure across C235 PASS FAIL For VCC_ISO_5V_CH1 measure across C276 PASS FAIL For VCC_ISO_5V_CH2 measure across C277 PASS FAIL For VCC_ISO_5V_CH3 measure across...

Page 36: ...1 PASS FAIL For PLL_1V5 measure across C79 PASS FAIL For CPU_CORE_1V35 measure across C4 PASS FAIL Measure the voltage of each power supply with a DVM across the following components and record the results For 3_3V measure across C59 For 3_3V_LATE measure across C88 For 1_8V measure across C41 For PLL_1V5 measure across C79 For CPU_CORE_1V35 measure across C4 5 5 Initial programming See 4 Manufact...

Page 37: ...ump a 0xB4020000 o 0x08 b 0x05 modem CH1 M1 M0 0 1 transmit mmdump a 0xB4020000 o 0x09 b 0x01 modem CH2 CH15 TX is controlled by DUART CHB TX mmdump a 0xB4020000 o 0x0A b 0x05 modem CH2 M1 M0 1 0 receive mmdump a 0xB4020000 o 0x0B b 0x02 DUART CH A RX is controlled by MODEM 1 mmdump a 0xB4020000 o 0x12 b 0x02 DUART CH B RX is controlled by MODEM 2 mmdump a 0xB4020000 o 0x13 b 0x02 3 set baudrate f...

Page 38: ...a 0xB4020000 o 0x13 b 0x02 3 set baudrate for both DUART ports stty F dev ttySC0 echo icrnl 1200 stty F dev ttySC1 echo icrnl 1200 4 terminal 1 cat dev ttySC0 terminal 2 cat fox txt dev ttySC1 observe text from file fox txt appear on terminal 1 5 7 3 LED s test TBD 5 8 RS232 RS485 Ports PORT 3 J2B PORT 4 J2A PORT 5 J2D PORT 6 J2C Bug 480 Verify that RS232 RS485 Ports 1 4 function correctly 5 8 1 R...

Page 39: ... 0xB4080003 0x00 root QEIprocFull oe mmdump a 0xb4080000 o 0x04 b 0x00 W 0xB4080004 0x00 make sure that loopback test fails and that only yellow LED is active green is not lit 5 8 2 RS 485 test install IRIG RS485 to Quad RS232 Loopback cable setup_all_ports sh root QEIprocFull oe mmdump a 0xb4080000 o 0x01 b 0x00 W 0xB4080001 0x00 root QEIprocFull oe mmdump a 0xb4080000 o 0x02 b 0x00 W 0xB4080002 ...

Page 40: ...rocFull oe mmdump a 0xb4080000 o 0x03 b 0x00 W 0xB4080003 0x00 root QEIprocFull oe mmdump a 0xb4080000 o 0x04 b 0x08 W 0xB4080004 0x08 root QEIprocFull oe cat dev ttyS2 root QEIprocFull oe cat fox txt dev ttyS3 5 9 OPTIONS S1 DIP switches S1 DIP switches 1 4 Bug 356 verify front panel DIP switch SW1 See 3 7 8 Option DIP Switch Register mmdump a 0xb4030000 o 0x12 b perform walking 0 s and walking 1...

Page 41: ...b4010000 o 0x0F b 0x1 perform walking ones and walking zeroes test on HBT L1 L2 L3 and L4 5 11 IRIG SERIAL PORT 7 J3 TX left RX right LED s TX top RX bottom Bug 327 bring up IRIG B fiber interface J3T and J3R test procedure without fiber loopback cable both TX and RX LED s are off setup_all_ports sh set IRIG_BUS signal high mmdump a 0xb4020000 o 0x00 b 0x08 fiber TX IRIG_BUS mmdump a 0xb4020000 o ...

Page 42: ...board Bug 579 bring up micro SD card interface Bug 580 bring up SD card interface 5 13USB MAINT J5 5 14USB HOST J6 Bug 344 bring up USB HUB mount dev sda1 usb0 5 15IRIG RS 485 PORT 8 J7B See Bug 328 bring up IRIG B_RS 485 Iso 5 15 1 IRIG TX test Install IRIG RS485 to Quad RS232 Loopback cable setup_all_ports sh CH8 TX is mapped to IRIG RS 485 mmdump a 0xb4020000 o 0x02 b 6 W 0xB4020002 0x06 cat de...

Page 43: ...EIprocFull oe mmdump a 0xb4080000 o 0x03 b 0x00 W 0xB4080003 0x00 root QEIprocFull oe mmdump a 0xb4080000 o 0x04 b 0x00 W 0xB4080004 0x00 root QEIprocFull oe mmdump a 0xb4080000 o 0x01 b 0x08 cat dev ttyS5 cat fox txt dev ttyS0 LED s at IRIG PORT 8 J7B yellow left LED is not blinking green is blinking at RS 232 RS 485 ports 2 4 green LED s are blinking yellow LED s are not ar RS 232 RS 484 port 1 ...

Page 44: ... cat command is executed test MSTR_RS422_TXEN install loopback cable mmdump a 0xB4010000 o 0x16 b 0x0 mmdump a 0xB4080000 o 0x05 b 0x0 observe the contents of fox txt NOT appear on the terminal LED s only yellow left is blinking green right LED is NOT blinking 5 16 2 PORT 10 J7D external loopback test Install RS422 LOOPBACK cable into PORT 10 J7D setup_all_ports sh mmdump a 0xB4010000 o 0x16 b 0x1...

Page 45: ... cat fox txt dev ttyS4 observe the contents of fox txt appear on the terminal LED s both yellow left and green right LED s are blinking unplug the loopback cable observe the contents of fox txt NOT appear on the terminal LED s only yellow left is blinking green right LED is NOT blinking testing CH7_HLF_DPLX_EN_H install loopback cable mmdump a 0xB4010000 o 0x16 b 0x1 mmdump a 0xB4080000 o 0x07 b 0...

Page 46: ...e LED s yellow left blinks on J8 A and green right blinks on J8 B test J8 B TX J8 A RX cat dev ttySC0 cat fox txt dev ttySC1 observe the contents of fox txt appear on the console LED s yellow left blinks on J8 B and green right blinks on J8 A verify that RTS maps to CTS over the crossover cable J8 A RTS output J8 B CTS input rts dev ttySC0 0 cts dev ttySC1 verify output dev dev ttySC1 dev ttySC1 C...

Page 47: ...thernet connection confirm that no LED s are on at the fiber Ethernet ports connect PORT 14 J10 to local network via Startech Fiber Ethernet Media Converter MCM110ST2 confirm top LED is mostly on bottom LED is mostly off use ping utility to ping another machine ping 192 168 24 1 both LED s are blinking repeat for PORT 15 J11 5 2010 100BaseTX Ethernet Ports PORT 16 J12B PORT 17 J12A PORT 18 J12D PO...

Page 48: ...5 J11 remove Copper Ethernet connection confirm that no LED s are on at the copper Ethernet ports connect PORT 16 J12B to local network confirm yellow left is mostly on green is mostly off use ping utility to ping another machine ping 192 168 24 1 both LED s are blinking repeat for PORT 17 J12A PORT 18 J12D PORT 19 J12C 5 21RTC Bug 446 RTC clock is reset after power cycle Bug 51 The SuperCap C167 ...

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