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MPC555

/

MPC556

EXTERNAL BUS INTERFACE

MOTOROLA

USER’S MANUAL

Rev. 15 October 2000

9-38

:

9.5.7.7 Burst Data in Progress

This signal is sent from the master to the slave to indicate that there is a data beat fol-
lowing the current data beat. The master uses this signal to give the slave advance
warning of the remaining data in the burst. BDIP can also be used to terminate the
burst cycle early. Refer to

9.5.3 Burst Transfer

and

9.5.4 Burst Mechanism

for more

information.

9.5.8 Termination Signals

The EBI uses three termination signals:

• Transfer acknowledge (TA)
• Burst inhibit (BI)
• Transfer error acknowledge (TEA)

9.5.8.1 Transfer Acknowledge

Transfer acknowledge indicates normal completion of the bus transfer. During a burst
cycle, the slave asserts this signal with every data beat returned or accepted.

Table 9-8 Address Types Definition

STS

TS

AT0

AT1

AT2

AT3

PTR

RSV

Address Space Definitions

1

x

x

x

x

x

1

1

No transfer

0

0

1

NOTES:

1. Cases in which both TS and STS are asserted indicate normal cycles with the show cycle attribute.

0

0

0

0

0

1

RCPU, normal instruction, program trace, supervisor mode

1

1

1

RCPU, normal instruction, supervisor mode

1

0

1

0

RCPU, reservation data, supervisor mode

1

1

1

RCPU, normal data, supervisor mode

1

0

0

0

1

RCPU, normal instruction, program trace, user mode

1

1

1

RCPU, normal instruction, user mode

1

0

1

0

RCPU, reservation data, user mode

1

1

1

RCPU, normal data, user mode

1

?

?

?

1

1

Reserved

1

0

0

0

0

0

1

RCPU, show cycle address instruction, program trace, su-
pervisor mode

1

1

1

RCPU, show cycle address instruction, supervisor mode

1

0

1

0

RCPU, reservation show cycle data, supervisor mode

1

1

1

RCPU, show cycle data, supervisor mode

1

0

0

0

1

RCPU, show cycle address instruction, program trace, user
mode

1

1

1

RCPU, show cycle address instruction, user mode

1

0

1

0

RCPU, reservation show cycle data, user mode

1

1

1

RCPU, show cycle data, user mode

1

?

?

?

1

1

Reserved

F

re

e

sc

a

le

S

e

m

ic

o

n

d

u

c

to

r,

I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

n

c

.

..

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Summary of Contents for MPC555

Page 1: ... MPC556 USER S MANUAL Revised 15 October 2000 Copyright 2000 MOTOROLA All Rights Reserved Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 2: ... MPC556 USER S MANUAL Revised 15 October 2000 Copyright 2000 MOTOROLA All Rights Reserved Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 3: ...r Modules QADC 1 4 1 2 11 Two CAN 2 0B Controller Modules TouCANs 1 5 1 2 12 Queued Serial Multi Channel Module QSMCM 1 5 1 3 MPC555 MPC556 Address Map 1 5 Section 2 SIGNAL DESCRIPTIONS 2 1 Packaging and Pinout Descriptions 2 1 2 2 Pin Functionality 2 6 2 3 Signal Descriptions 2 12 2 3 1 USIU Pads 2 12 2 3 1 1 ADDR 8 31 SGPIOA 8 31 2 12 2 3 1 2 DATA 0 31 SGPIOD 0 31 2 13 2 3 1 3 IRQ 0 SGPIOC 0 2 1...

Page 4: ...3 1 33 TCK DSCK 2 19 2 3 1 34 TDO DSDO 2 19 2 3 1 35 TRST 2 20 2 3 1 36 XTAL 2 20 2 3 1 37 EXTAL 2 20 2 3 1 38 XFC 2 20 2 3 1 39 CLKOUT 2 20 2 3 1 40 EXTCLK 2 20 2 3 1 41 VDDSYN 2 20 2 3 1 42 VSSSYN 2 20 2 3 1 43 ENGCLK BUCLK 2 21 2 3 2 QSMCM PADS 2 21 2 3 2 1 PCS0 SS QGPIO 0 2 21 2 3 2 2 PCS 1 3 QGPIO 1 3 2 21 2 3 2 3 MISO QGPIO 4 2 21 2 3 2 4 MOSI QGPIO 5 2 21 2 3 2 5 SCK QGPIO 6 2 22 2 3 2 6 TX...

Page 5: ...OUCAN_B PADS 2 26 2 3 6 1 CNTX0_ A B 2 26 2 3 6 2 CNRX0_ A B 2 26 2 3 7 CMF PADS 2 27 2 3 7 1 EPEE 2 27 2 3 7 2 VPP 2 27 2 3 7 3 VDDF 2 27 2 3 7 4 VSSF 2 27 2 3 8 GLOBAL POWER SUPPLIES 2 27 2 3 8 1 VDDL 2 27 2 3 8 2 VDDH 2 27 2 3 8 3 VDDI 2 27 2 3 8 4 VSSI 2 27 2 3 8 5 KAPWR 2 28 2 3 8 6 VDDSRAM 2 28 2 3 8 7 VSS 2 28 2 4 Reset State 2 28 2 4 1 Pin Functionality Out of Reset 2 28 2 4 2 Pad Module C...

Page 6: ...44 2 5 5 Five Volt Input Output Pad 2 45 2 5 5 1 Type H Interface 2 45 2 5 5 2 Type I Interface 2 46 2 5 5 3 Type IH Interface 2 48 2 5 5 4 Type J Interface 2 49 2 5 5 5 Type JD Interface 2 49 2 5 6 Type K Interface EPEE Pad 2 50 2 5 7 Analog Pads 2 51 2 5 7 1 Type L Interface QADC Port A 2 51 2 5 7 2 Type M Interface QADC Port B 2 52 2 5 7 3 Type N Interface ETRIG 2 53 2 5 8 Pads with Fast Mode 2...

Page 7: ...Set Time Base 3 19 3 9 PowerPC OEA Register Set 3 20 3 9 1 Machine State Register MSR 3 20 3 9 2 DAE Source Instruction Service Register DSISR 3 22 3 9 3 Data Address Register DAR 3 22 3 9 4 Time Base Facility TB OEA 3 23 3 9 5 Decrementer Register DEC 3 23 3 9 6 Machine Status Save Restore Register 0 SRR0 3 24 3 9 7 Machine Status Save Restore Register 1 SRR1 3 24 3 9 8 General SPRs SPRG0 SPRG3 3...

Page 8: ...3 41 3 13 10 4 Storage Synchronization Instructions 3 41 3 13 10 5 Floating Point Load and Store With Update Instructions 3 41 3 13 10 6 Floating Point Load Single Instructions 3 41 3 13 10 7 Floating Point Store Single Instructions 3 41 3 13 10 8 Optional Instructions 3 42 3 13 10 9 Little Endian Byte Ordering 3 42 3 14 PowerPC Virtual Environment Architecture VEA 3 42 3 14 1 Atomic Update Primit...

Page 9: ...Instructions 3 52 3 15 5 Timer Facilities 3 53 3 15 6 Optional Facilities and Instructions 3 53 Section 4 BURST BUFFER 4 1 Burst Buffer Block Diagram 4 1 4 2 Burst Buffer Features 4 2 4 3 Instruction VocabularyBased Compression Model Main Principles 4 3 4 3 1 Compression Model Features 4 3 4 3 2 Model Limitations 4 4 4 3 3 Vocabulary Based Instruction Compression Algorithm 4 4 4 3 4 Memory Organiz...

Page 10: ...es 6 6 6 3 USIU General Purpose I O 6 6 6 4 Interrupt Controller 6 8 6 4 1 SIU Interrupt Sources Priority 6 11 6 5 Hardware Bus Monitor 6 12 6 6 MPC555 MPC556 Decrementer 6 12 6 7 MPC555 MPC556 Time Base TB 6 13 6 8 Real Time Clock RTC 6 14 6 9 Periodic Interrupt Timer PIT 6 15 6 10 Software Watchdog Timer SWT 6 16 6 11 Freeze Operation 6 17 6 12 Low Power Stop Operation 6 17 6 13 System Configura...

Page 11: ...nterrupt Timer Register PITR 6 33 6 13 5 General Purpose I O Registers 6 34 6 13 5 1 SGPIO Data Register 1 SGPIODT1 6 34 6 13 5 2 SGPIO Data Register 2 SGPIODT2 6 34 6 13 5 3 SGPIO Control Register SGPIOCR 6 35 Section 7 RESET 7 1 Reset Operation 7 1 7 1 1 Power On Reset 7 1 7 1 2 Hard Reset 7 2 7 1 3 Soft Reset 7 2 7 1 4 Loss of Lock 7 3 7 1 5 On Chip Clock Switch 7 3 7 1 6 Software Watchdog Rese...

Page 12: ...e 8 17 8 8 3 3 Exiting from Deep Sleep Mode 8 17 8 8 3 4 Exiting from Power Down Mode 8 18 8 8 3 5 Low Power Modes Flow 8 18 8 9 Basic Power Structure 8 20 8 9 1 Clock Unit Power Supply 8 20 8 9 2 Chip Power Structure 8 20 8 9 2 1 VDDL 8 20 8 9 2 2 VDDI 8 20 8 9 2 3 VDDSYN VSSSYN 8 21 8 9 2 4 KAPWR 8 21 8 9 2 5 VDDA VSSA 8 21 8 9 2 6 VPP 8 21 8 9 2 7 VDDF VSSF 8 21 8 9 2 8 VDDH 8 21 8 9 2 9 VDDSRA...

Page 13: ...st 9 31 9 5 6 2 Bus Grant 9 32 9 5 6 3 Bus Busy 9 32 9 5 6 4 Internal Bus Arbiter 9 33 9 5 7 Address Transfer Phase Signals 9 35 9 5 7 1 Transfer Start 9 36 9 5 7 2 Address Bus 9 36 9 5 7 3 Read Write 9 36 9 5 7 4 Burst Indicator 9 36 9 5 7 5 Transfer Size 9 37 9 5 7 6 Address Types 9 37 9 5 7 7 Burst Data in Progress 9 38 9 5 8 Termination Signals 9 38 9 5 8 1 Transfer Acknowledge 9 38 9 5 8 2 Bu...

Page 14: ... 10 7 Memory Controller External Master Support 10 24 10 8 Programming Model 10 27 10 8 1 General Memory Controller Programming Notes 10 27 10 8 2 Memory Controller Status Registers MSTAT 10 28 10 8 3 Memory Controller Base Registers BR0 BR3 10 28 10 8 4 Memory Controller Option Registers OR0 OR3 10 30 10 8 5 Dual Mapping Base Register DMBR 10 31 10 8 6 Dual Mapping Option Register 10 32 Section 1...

Page 15: ...O IMB3 BUS INTERFACE UIMB 12 1 Features 12 1 12 2 UIMB Block Diagram 12 2 12 3 Clock Module 12 2 12 4 Interrupt Operation 12 3 12 4 1 Interrupt Sources and Levels on IMB 12 4 12 4 2 IMB Interrupt Multiplexing 12 4 12 4 3 ILBS Sequencing 12 4 12 4 4 Interrupt Synchronizer 12 6 12 5 Programming Model 12 7 12 5 1 UIMB Module Configuration Register UMCR 12 7 12 5 2 Test control register UTSTCREG 12 8 ...

Page 16: ...iming 13 13 13 9 2 Front End Analog Multiplexer 13 14 13 9 3 Digital to Analog Converter Array 13 14 13 9 4 Comparator 13 14 13 9 5 Successive Approximation Register 13 14 13 10 Digital Control Subsystem 13 14 13 10 1 Queue Priority 13 15 13 10 2 Queue Boundary Conditions 13 17 13 10 3 Scan Modes 13 18 13 10 3 1 Disabled Mode 13 18 13 10 3 2 Reserved Mode 13 18 13 10 3 3 Single Scan Modes 13 18 13...

Page 17: ... 14 5 6 QSMCM Test Register QTEST 14 8 14 5 7 QSMCM Interrupt Level Registers QDSCI_IL QSPI_IL 14 8 14 6 QSMCM Pin Control Registers 14 9 14 6 1 Port QS Data Register PORTQS 14 10 14 6 2 PORTQS Pin Assignment Register PQSPAR 14 11 14 6 3 PORTQS Data Direction Register DDRQS 14 12 14 7 Queued Serial Peripheral Interface 14 13 14 7 1 QSPI Registers 14 15 14 7 1 1 QSPI Control Register 0 14 16 14 7 1...

Page 18: ...arity Checking 14 52 14 8 7 5 Transmitter Operation 14 52 14 8 7 6 Receiver Operation 14 54 14 8 7 7 Receiver Functional Operation 14 56 14 8 7 8 Idle Line Detection 14 57 14 8 7 9 Receiver Wake Up 14 58 14 8 7 10 Internal Loop Mode 14 58 14 9 SCI Queue Operation 14 58 14 9 1 Queue Operation of SCI1 for Transmit and Receive 14 58 14 9 2 Queued SCI1 Status and Control Registers 14 59 14 9 2 1 QSCI1...

Page 19: ...Interrupt Control Section ICS 15 11 15 9 MIOS Counter Prescaler Submodule MCPSM 15 12 15 9 1 MIOS Counter Prescaler Submodule MCPSM Registers 15 12 15 9 1 1 MCPSM Status Control Register MCPSMCSCR 15 13 15 10 MIOS Modulus Counter Submodule MMCSM 15 13 15 10 1 MIOS Modulus Counter Submodule MMCSM Registers 15 15 15 10 1 1 MMCSM Up Counter Register MMCSMCNT 15 16 15 10 1 2 MMCSM Modulus Latch Regist...

Page 20: ... Register MIOS1RPR1 15 37 15 15 MIOS1 Function Examples 15 38 15 15 1 MIOS1 Input Double Edge Pulse Width Measurement 15 38 15 15 2 MIOS1 Input Double Edge Period Measurement 15 40 15 15 3 MIOS1 Double Edge Single Output Pulse Generation 15 41 15 15 4 MIOS1 Output Pulse Width Modulation With MDASM 15 42 15 15 5 MIOS1 Input Pulse Accumulation 15 43 15 16 MIOS1 Configuration 15 43 Section 16 CAN 2 0...

Page 21: ...ration Register 16 24 16 7 3 TouCAN Interrupt Configuration Register 16 24 16 7 4 Control Register 0 16 25 16 7 5 Control Register 1 16 26 16 7 6 Prescaler Divide Register 16 27 16 7 7 Control Register 2 16 28 16 7 8 Free Running Timer 16 29 16 7 9 Receive Global Mask Registers 16 29 16 7 10 Receive Buffer 14 Mask Registers 16 30 16 7 11 Receive Buffer 15 Mask Registers 16 30 16 7 12 Error and Sta...

Page 22: ...t Service Request Registers 17 17 17 4 10 Channel Priority Registers 17 18 17 4 11 Channel Interrupt Status Register 17 19 17 4 12 Link Register 17 19 17 4 13 Service Grant Latch Register 17 19 17 4 14 Decoded Channel Number Register 17 19 17 4 15 TPU3 Module Configuration Register 2 17 20 17 4 16 TPU Module Configuration Register 3 17 21 17 4 17 TPU3 Test Registers 17 22 17 4 18 TPU3 Parameter RA...

Page 23: ...le B 19 15 19 3 Shadow Information 19 15 19 3 1 Address Range of Shadow Information 19 16 19 3 2 Reset Configuration Word CMFCFIG 19 16 19 4 Array Read Operation 19 17 19 5 Programming the CMF Array 19 18 19 5 1 Program Sequence 19 18 19 5 2 Program Margin Reads 19 22 19 5 3 Over Programming 19 23 19 6 Erasing CMF Array Blocks 19 23 19 6 1 Erase Sequence 19 23 19 6 2 Erase Margin Reads 19 26 19 6 ...

Page 24: ... Tracking 21 1 21 2 1 Program Trace Cycle 21 2 21 2 1 1 Instruction Queue Status Pins VF 0 2 21 3 21 2 1 2 History Buffer Flushes Status Pins VFLS 0 1 21 4 21 2 1 3 Queue Flush Information Special Case 21 4 21 2 2 Program Trace when in Debug Mode 21 4 21 2 3 Sequential Instructions Marked as Indirect Branch 21 5 21 2 4 The External Hardware 21 5 21 2 4 1 Synchronizing the Trace Window to the CPU I...

Page 25: ...FLS 0 1 _MPIO32B 3 4 Pins 21 32 21 5 6 Development Port Registers 21 32 21 5 6 1 Development Port Shift Register 21 33 21 5 6 2 Trap Enable Control Register 21 33 21 5 6 3 Development Port Registers Decode 21 33 21 5 6 4 Development Port Serial Communications Clock Mode Selection 21 34 21 5 6 5 Development Port Serial Communications Trap Enable Mode 21 38 21 5 6 6 Serial Data into Development Port...

Page 26: ... 3 22 5 Instruction Register 22 4 22 5 1 EXTEST 22 5 22 5 2 SAMPLE PRELOAD 22 5 22 5 3 BYPASS 22 5 22 5 4 CLAMP 22 6 22 5 5 HI Z 22 6 22 6 Restrictions 22 6 22 7 Low Power Stop Mode 22 6 22 8 Non IEEE 1149 1 1990 Operation 22 7 22 9 Boundary Scan Register 22 7 Appendix A MPC555 MPC556 INTERNAL MEMORY MAP Appendix B REGISTER GENERAL INDEX Appendix C REGISTER DIAGRAM INDEX Appendix D TPU ROM FUNCTIO...

Page 27: ...ater Than 16 D 52 D 19 3 2 Data Positioning D 52 D 19 3 3 Data Timing D 52 Appendix E CLOCK AND BOARD GUIDELINES E 1 INTRODUCTION E 1 E 2 MPC555 MPC556 Family Power Distribution E 2 E 3 PLL and Crystal Oscillator External Components E 4 E 3 1 Crystal Oscillator External Components E 4 E 3 2 KAPWR Filtering E 5 E 3 3 PLL External Components E 6 E 3 4 PLL Off Chip Capacitor CXFC E 7 E 4 Clock Oscill...

Page 28: ...s G 52 G 17 QSMCM Electrical Characteristics G 53 G 18 GPIO Electrical Characteristics G 57 G 19 TPU3 Electrical Characteristics G 57 G 20 TouCAN Electrical Characteristics G 58 G 21 MIOS Timing Characteristics G 59 G 21 1 MPWMSM Timing Characteristics G 60 G 21 2 MMCSM Timing Characteristics G 62 G 21 3 MDASM Timing Characteristics G 65 G 21 4 MPIOSM Timing Characteristics G 68 Appendix H FLASH E...

Page 29: ...pe IH Interface 2 48 2 16 Type J Interface 2 49 2 17 Type JD Interface 2 50 2 18 EPEE Pad Type K 2 51 2 19 Type L Interface 2 52 2 20 Type M Interface 2 52 2 21 Type N Interface 2 53 2 22 Type O Interface 2 54 2 23 Type P Interface 2 55 2 24 Type Q Interface 2 56 2 25 Type R Interface 2 56 2 26 Type S Interface 2 57 3 1 RCPU Block Diagram 3 2 3 2 Sequencer Data Path 3 4 3 3 RCPU Programming Model ...

Page 30: ...tion Basic Scheme 7 7 7 2 Reset Configuration Sampling Scheme For Short PORESET Assertion Limp Mode Disabled 7 8 7 3 Reset Configuration Timing for Short PORESET Assertion Limp Mode Enabled 7 9 7 4 Reset Configuration Timing for Long PORESET Assertion Limp Mode Disabled 7 9 7 5 Reset Configuration Sampling Timing Requirements 7 10 8 1 Clock Unit Block Diagram 8 2 8 2 Main System Oscillator OSCM 8 ...

Page 31: ...d Burst 9 25 9 19 Non Wrap Burst with Three Beats 9 26 9 20 Non Wrap Burst with One Data Beat 9 27 9 21 Internal Operand Representation 9 28 9 22 Interface To Different Port Size Devices 9 29 9 23 Bus Arbitration Flowchart 9 31 9 24 Masters Signals Basic Connection 9 32 9 25 Bus Arbitration Timing Diagram 9 33 9 26 Internal Bus Arbitration State Machine 9 35 9 27 Termination Signals Protocol Basic...

Page 32: ...0 16 10 15 Consecutive Accesses Read After Read From Different Banks EHTR 1 10 17 10 16 Consecutive Accesses Read After Read From Same Bank EHTR 1 10 18 10 17 Aliasing Phenomena Illustration 10 23 10 18 Synchronous External Master Configuration For GPCM Handled Memory Devices 10 25 10 19 Synchronous External Master Basic Access GPCM Controlled 10 26 11 1 L2U Bus Interface Block Diagram 11 2 11 2 D...

Page 33: ...Diagram 14 43 14 14 Start Search Example 14 56 14 15 Queue Transmitter Block Enhancements 14 62 14 16 Queue Transmit Flow 14 64 14 17 Queue Transmit Software Flow 14 65 14 18 Queue Transmit Example for 17 Data Bytes 14 66 14 19 Queue Transmit Example for 25 Data Frames 14 67 14 20 Queue Receiver Block Enhancements 14 68 14 21 Queue Receive Flow 14 71 14 22 Queue Receive Software Flow 14 72 14 23 Q...

Page 34: ...ing 19 38 19 10 VPP Conditioning Circuit 19 39 20 1 SRAM Block Diagram 20 1 20 2 SRAM Memory Map 20 2 21 1 Watchpoints and Breakpoint Support in the CPU 21 10 21 2 Partially Supported Watchpoint Breakpoint Example 21 15 21 3 Instruction Support General Structure 21 17 21 4 Load Store Support General Structure 21 20 21 5 Functional Diagram of MPC555 MPC556 Debug Mode Support 21 23 21 6 Debug Mode L...

Page 35: ...e Ch B Non Inverted Center Aligned Mode D 26 D 17 MCPWM Parameters Slave Ch A Inverted Center Aligned Mode D 27 D 18 MCPWM Parameters Slave Ch B Non Inverted Center Aligned Mode D 28 D 19 FQD Parameters Primary Channel D 30 D 20 FQD Parameters Secondary Channel D 31 D 21 PPWA Parameters D 33 D 22 OC Parameters D 35 D 23 PWM Parameters D 37 D 24 DIO Parameters D 39 D 25 SPWM Parameters Part 1 of 2 ...

Page 36: ...l Master Write to Internal Registers Timing G 38 G 18 Interrupt Detection Timing for External Level Sensitive Lines G 39 G 19 Interrupt Detection Timing for External Edge Sensitive Lines G 40 G 20 Debug Port Clock Input Timing G 41 G 21 Debug Port Timings G 42 G 22 Reset Timing Configuration from Data Bus G 44 G 23 Reset Timing Data Bus Weak Drive During Configuration G 45 G 24 Reset Timing Debug ...

Page 37: ... Minimum Input Pin Timing Diagram G 65 G 45 MDASM Input Pin to Counter Bus Capture Timing Diagram G 66 G 46 MDASM Input Pin to MDASM Interrupt Flag Timing Diagram G 66 G 47 MDASM Minimum Output Pulse Width Timing Diagram G 66 G 48 Counter Bus to MDASM Output Pin Change Timing Diagram G 67 G 49 Counter Bus to MDASM Interrupt Flag Setting Timing Diagram G 67 G 50 MPIOSM Input Pin to MPIOSM_DR Data R...

Page 38: ... MPC555 MPC555 LIST OF FIGURES MOTOROLA USER S MANUAL Rev 15 October 2000 xxxviii Figure Number Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 39: ...Register Bit Descriptions 3 21 3 13 Floating Point Exception Mode Bits 3 22 3 14 Time Base Field Definitions Write Only 3 23 3 15 Uses of SPRG0 SPRG3 3 25 3 16 Processor Version Register Bit Descriptions 3 26 3 17 EIE EID AND NRI Registers 3 26 3 18 FPECR Bit Descriptions 3 27 3 19 Instruction Set Summary 3 29 3 20 MPC555 MPC556 Exception Classes 3 34 3 21 Exception Vector Offset Table 3 36 3 22 I...

Page 40: ... 6 33 6 21 SGPIODT1 Bit Descriptions 6 34 6 22 SGPIODT2 Bit Descriptions 6 35 6 23 SGPIOCR Bit Descriptions 6 35 6 24 Data Direction Control 6 36 7 1 Reset Action Taken For Each Reset Cause 7 4 7 2 Reset Configuration Word and Data Corruption Coherency 7 4 7 3 Reset Status Register Bit Descriptions 7 5 7 4 Reset Configuration Options 7 7 7 5 Hard Reset Configuration Word Bit Descriptions 7 11 8 1 ...

Page 41: ...2 Reservation Snoop Support 11 9 11 3 L2U_MCR LSHOW Modes 11 9 11 4 L2U Show Cycle Support Chart 11 12 11 5 L2U PPC Register Decode 11 12 11 6 Hex Address For SPR Cycles 11 13 11 7 L2U_MCR Bit Descriptions 11 14 11 8 L2U_RBAx Bit Descriptions 11 14 11 9 L2U_RAx Bit Descriptions 11 15 11 10 L2U_GRA Bit Descriptions 11 16 12 1 STOP and HSPEED Bit Functionality 12 2 12 2 Bus Cycles and System Clock C...

Page 42: ...n Control Registers 14 9 14 8 Effect of DDRQS on QSPI Pin Function 14 10 14 9 QSMCM Pin Functions 14 11 14 10 PQSPAR Bit Descriptions 14 12 14 11 DDRQS Bit Descriptions 14 13 14 12 QSPI Register Map 14 16 14 13 SPCR0 Bit Descriptions 14 17 14 14 Bits Per Transfer 14 17 14 15 SPCR1 Bit Descriptions 14 18 14 16 SPCR2 Bit Descriptions 14 19 14 17 SPCR3 Bit Descriptions 14 20 14 18 SPSR Bit Descriptio...

Page 43: ...criptions 15 28 15 23 MPWMSMSCR Bit Descriptions 15 29 15 24 PWMSM Output Pin Polarity Selection 15 29 15 25 MPIOSM Address Map 15 30 15 26 MPIOSMDR Bit Descriptions 15 31 15 27 MPIOSMDDR Bit Descriptions 15 31 15 28 MIRSM0 Address Map 15 34 15 29 MIOS1SR0 Bit Descriptions 15 34 15 30 MIOS1ER0 Bit Descriptions 15 35 15 31 MIOS1RPR0 Bit Descriptions 15 36 15 32 MIRSM1 Address Map 15 36 15 33 MIOS1S...

Page 44: ... Prescaler Values 17 6 17 3 TCR2 Counter Clock Source 17 7 17 4 TCR2 Prescaler Control 17 8 17 5 TPU3 Register Map 17 9 17 6 TPUMCR Bit Descriptions 17 11 17 7 DSCR Bit Descriptions 17 13 17 8 DSSR Bit Descriptions 17 14 17 9 TICR Bit Descriptions 17 15 17 10 CIER Bit Descriptions 17 15 17 11 CFSRx Bit Descriptions 17 16 17 12 HSQRx Bit Descriptions 17 17 17 13 HSSRx Bit Descriptions 17 18 17 14 C...

Page 45: ... Data Events 21 18 21 8 Load Store Watchpoints Programming Options 21 19 21 9 The Check Stop State and Debug Mode 21 29 21 10 Trap Enable Data Shifted into Development Port Shift Register 21 38 21 11 Debug Port Command Shifted Into Development Port Shift Register 21 38 21 12 Status Data Shifted Out of Development Port Shift Register 21 39 21 13 Debug Instructions Data Shifted Into Development Port...

Page 46: ...Memory Array A 25 D 1 Bank 0 Functions D 2 D 2 Bank 1 Functions D 3 D 3 QOM Bit Encoding D 6 D 4 SIOP Function Valid CHAN_Control Options D 50 D 5 SIOP State Timing D 52 E 1 External Components Value For Different Crystals Q1 E 4 F 1 Memory Access Times Using Different Buses F 1 F 2 Timing Examples F 2 G 1 Absolute Maximum Ratings G 1 G 2 Thermal Characteristics G 3 G 3 ESD Protection G 6 G 4 DC E...

Page 47: ...ming Characteristics G 60 G 23 MMCSM Timing Characteristics G 62 G 24 MDASM Timing Characteristics G 65 G 25 MPIOSM Timing Characteristics G 68 H 1 Program and Erase Characteristics H 1 H 2 CMF AC and DC Power Supply Characteristics H 2 H 3 Flash Module Life H 3 H 4 CMF Programming Algorithm v5 H 3 H 5 CMF Erase Algorithm v5 H 3 Freescale Semiconductor I Freescale Semiconductor Inc For More Inform...

Page 48: ...er Page Number MPC555 MPC556 LIST OF TABLES MOTOROLA USER S MANUAL Rev 15 October 2000 xlviii Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 49: ...round to or supplements the information in this manual see John L Hennessy and David A Patterson Computer Architecture A Quantitative Approach Morgan Kaufmann Publishers Inc San Mateo CA PowerPC Microprocessor Family the Programming Environments MPCF PE AD Motorola order number MPC500 Family RCPU Reference Manual RCPURM AD Motorola order num ber Conventions This document uses the following notatio...

Page 50: ... bits To clear a bit or bits means to establish logic level zero on the bit or bits A signal that is asserted is in its active logic state An active low signal changes from logic level one to logic level zero when asserted and an active high signal changes from logic level zero to logic level one A signal that is negated is in its inactive logic state An active low signal changes from logic level ...

Page 51: ...controller modules TouCANTM 50 channel timer system dual time processor units TPU3 modular I O system MIOS1 32 analog inputs dual queued analog to digital converters QADC64 Submicron HCMOS CDR1 technology 272 pin plastic ball grid array PBGA packaging 40 MHz operation 40 C to 125 C with dual supply 3 3 V 5 V MPC556 supports code compression to increase code density NOTE Throughout this manual refe...

Page 52: ...PU core is running in normal mode and show cycles is turned off ISCT_SER of the ICTRL register is set to 111 See Table 21 21 Fully static low power operation Integrated floating point unit Precise exception model Extensive system development support On chip watchpoints and breakpoints Program flow tracking USIU RCPU Burst Interface 256 Kbytes Flash 192 Kbytes Flash 16 Kbytes SRAM 10 Kbytes SRAM L2...

Page 53: ...ernal and eight internal interrupts IEEE 1149 1 JTAG test access port External bus interface 24 address pins 32 data pins Supports multiple master designs Four beat transfer bursts two clock minimum bus transactions Tolerates 5 V inputs provides 3 3 V outputs 1 2 4 Flexible Memory Protection Unit Four instruction regions and four data regions 4 Kbyte to 16 Mbyte region size support Default attribu...

Page 54: ...Each channel can be synchronized to one or both counters Selectable channel priority levels 5 V outputs 6 Kbyte dual port TPU RAM DPTRAM is shared by the two TPU3 modules for TPU microcode 1 2 9 18 Channel Modular I O System MIOS1 Ten double action submodules DASMs Eight dedicated PWM sub modules PWMSMs Two 16 bit modulus counter submodules MCSMs Two parallel port I O submodules PIOSM 5 V outputs ...

Page 55: ...ransfer length from eight to 16 bits inclusive Synchronous interface with baud rate of up to system clock 4 Four programmable peripheral select pins support up to 16 devices Wrap around mode allows continuous sampling of a serial peripheral for effi cient interfacing to serial A D converters Two serial communications interfaces SCI Each SCI offers these features UART mode provides NRZ format and h...

Page 56: ...c RAM memory 26 Kbytes Control registers and IMB2 modules 64 Kbytes USIU and flash control registers UIMB interface and IMB2 modules SRAM control registers 0x0000 0000 0x003F FFFF 0x0040 0000 0x007F FFFF 0x0080 0000 0x00BF FFFF 0x00C0 0000 0x00FF FFFF 0x0100 0000 0x013F FFFF 0x0140 0000 0x017F FFFF 0x0180 0000 0x01BF FFFF 0x01C0 0000 0x01FF FFFF 0xFFFF FFFF Internal 4 Mbyte Memory Block Resides in...

Page 57: ...PTRAM 6 Kbytes QSMCM 4 Kbytes MIOS1 4 Kbytes TouCAN_A 1 Kbyte TouCAN_B 1 Kbyte UIMB_Registers 128 bytes TPU3_A 1 Kbyte TPU3_B 1 Kbyte QADC_A 1 Kbyte QADC_B 1 Kbyte DPTRAM Control Reserved 8180 bytes Reserved 2 Kbytes 0x30 2000 0x30 4000 0x30 5000 0x30 6000 Reserved 1920 bytes 12 bytes IMB3 Address Space 0x2F C800 0x2F C840 UIMB Interface 32 Kbytes IMB3 Modules CMF Flash A Reserved for Flash Contro...

Page 58: ...MPC555 MPC556 OVERVIEW MOTOROLA USER S MANUAL Rev 15 October 2000 1 8 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 59: ...inout Descriptions Figure 2 1 gives the case configuration and packaging information for the MPC555 MPC556 Figure 2 2 gives the MPC555 MPC556 pinout data Table 2 1 gives an overview of the pins on the MPC555 MPC556 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 60: ...GPERASME Y14 5M 1994 2 DIMENSIONSINMILLIMETERS 3 DIMENSIONISMEASUREDATTHEMAXIMUM SOLDERBALLDIAMETERPARALLELTO PRIMARYDATUMA 4 PRIMARYDATUMAANDTHESEATINGPLANE AREDEFINEDBYTHESPHERICALCROWNSOF THESOLDERBALLS PIN 1 E2 D2 D E B M 0 2 INDEX C 0 2 4X TOP VIEW D1 A E1 4X e 19X e 2 19X e 1 2 3 5 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A B C D E F G H J K L M N P R T U 20 V W Y 272X b 3 C B M 0 3 A M 0 15 ...

Page 61: ...GP IRQ4B _SGP VSS VSS VSS VSS PCS1 _QGP PCS0 _QGP MISO _QGP4 MOSI _QGP5 M IRQ0B _SGP IRQ1B _SGP IRQ2B _SGP SGP_ IRQOUTB VSS VSS VSS VSS PCS3 _QGP PCS2 _QGP ECK SCK_ QGP6 N WEB_ AT 0 BRB_IWP2 BGB_LWP1 BBB _IWP3 Note The pinout is a top down view of the package RXD1_ QGPI TXD1_ QGPO RXD2_ QGPI TXD2_ QGPO P WEB_ AT 1 WEB_ AT 2 WEB_ AT 3 CS0B VPP EPEE VSSF VDDH R RD_WRB CS3B CS2B CS1B VDDL VDDF XFC VD...

Page 62: ...RQ 5 SGPIOC 5 MODCK 1 3 IRQ 6 7 MODCK 2 3 3 Bus control TSIZ 0 1 11 3 V RD WR BURST BDIP TS TA TEA RSTCONF TEXP3 OE BI STS General purpose chip select ma chine multiplexed with development and debug support CS 0 3 8 3 V WE 0 3 BE 0 3 AT 0 3 Power on reset and reset configuration PORESET3 3 3 V HRESET3 SRESET3 Development and debug support SGPIOC 6 FRZ PTR 5 3 V 5 V GPIO SGPIOC 7 IRQOUT LWP 0 BG VF...

Page 63: ...2 34 5 V A_AN0 ANW PQB0 B_AN0 ANW PQB0 A_AN1 ANX PQB1 B_AN1 ANX PQB1 A_AN2 ANY PQB2 B_AN2 ANY PQB2 A_AN3 ANZ PQB3 B_AN3 ANZ PQB3 A_AN 48 51 PQB 4 7 B_AN 48 51 PQB 4 7 A_AN 52 54 MA 0 2 PQA 0 2 B_AN 52 54 MA 0 2 PQA 0 2 A_AN 55 56 PQA 3 4 B_AN 55 56 PQA 3 4 A_AN 57 59 PQA 5 7 B_AN 57 59 PQA 5 7 TouCAN A_CNTX0 B_CNTX0 A_CNRX0 B_CNRX0 4 5 V Flash EEPROM EPEE 1 3 V Supplies Ground VSS VSSF VSSSYN 18 A...

Page 64: ... released A pull up resistor may be needed on this type of out put Receiver Type Type of receiver used for the pin Some inputs need to have a synchronizer to prevent latching a metastable signal at the pins Such require ments are indicated in this column with the abbreviation synch Another possible entry is glitch filter It is added to reset signals Direction Direction of the pin for each function...

Page 65: ...esis Synch I O 5 V 200 fast IRQ 2 CR SGPIOC 2 MTS IRQ 2 Hysteresis Synch I 3 V IH CR I 3 V SGPIOC 2 TP Hysteresis Synch I O 5 V 200 fast MTS TP O 3 V 25 50 IRQ 3 KR RETRY SGPIOC 3 IRQ 3 Hysteresis Synch I 3 V IH KR RETRY TP I O 3 V 25 50 SGPIOC 3 TP Hysteresis Synch I O 5 V 200 fast IRQ 4 AT 2 SGPIOC 4 IRQ 4 Hysteresis Synch I 3 V IH AT 2 TP O 3 V 25 50 SGPIOC 4 TP Hysteresis Synch I O 5 V 200 fas...

Page 66: ...R SGPIOC 6 TP Hysteresis Synch I O 5 V 200 fast I FRZ TP O 3 V 25 50 PTR TP O 3 V 25 50 SGPIOC 7 IRQOUT LWP 0 SGPIOC 7 TP Hysteresis Synch I O 5 V 200 fast I IRQOUT TP O 3 V 25 50 LWP 0 TP O 3 V 25 50 BG VF 0 LWP 1 BG TP I O 3 V 25 50 G VF 0 TP O 3 V 25 50 LWP 1 TP O 3 V 25 50 BR VF 1 IWP 2 BR TP I O 3 V 25 50 G VF 1 TP O 3 V 25 50 IWP 2 TP O 3 V 25 50 BB VF 2 IWP 3 BB3 ANG I O 3 V 25 50 G VF 2 TP...

Page 67: ...TP OD Synch No Synch I O 5 V 50 fast O QGPIO 4 TP OD Synch No Synch I O 5 V 50 fast MOSI QGPIO 5 MOSI TP OD Synch No Synch I O 5 V 50 fast O QGPIO 5 TP OD Synch No Synch I O 5 V 50 fast SCK QGPIO 6 SCK TP OD Synch No Synch I O 5 V 50 fast O QGPIO 6 TP OD Synch No Synch I O 5 V 50 fast TXD 1 2 QGPO 1 2 TXD 1 2 TP OD O 5 V 200 fast Q QGPO 1 2 TP OD O 5 V 200 fast RXD 1 2 QGPI 1 2 RXD 1 2 I 5 V R QGP...

Page 68: ...esis Synch I O 5 V 200 fast P QADC_A QADC_B ETRIG 1 2 ETRIG 1 2 Synch I 5 V N AN0 ANW PQB0 AN0 Analog I 5 V M ANW Analog I 5 V PQB0 Hysteresis Synch I 5 V AN1 ANX PQB1 AN1 Analog I 5 V M ANX Analog I 5 V PQB1 Hysteresis Synch I 5 V AN2 ANY PQB2 AN2 Analog I 5 V M ANY Analog I 5 V PQB2 Hysteresis Synch I 5 V AN3 ANZ PQB3 AN3 Analog I 5 V M ANZ Analog I 5 V PQB3 Hysteresis Synch I 5 V AN 48 51 PQB 4...

Page 69: ...1 PQB 4 7 AN 48 51 Analog I 5 V M PQB 4 7 Hysteresis Synch I 5 V AN 52 54 MA 0 2 PQA 0 2 AN 52 54 Analog I 5 V L MA 0 2 OD O 5 V PQA 0 2 OD Hysteresis Synch I O 5 V AN 55 56 PQA 3 4 AN 55 56 Analog I 5 V L PQA 3 4 OD Hysteresis Synch I O 5 V AN 57 59 PQA 5 7 AN 57 59 Analog I 5 V L PQA 5 7 OD Hysteresis Synch I O 5 V TOUCAN_A TOUCAN_B A_CNTX0 CNTX0_A TP OD O 5 V 50 fast Q B_CNTX0 CNTX0_B TP OD O 5...

Page 70: ...ve ADDR8 is the most significant signal for this bus CMF EPEE EPEE Sequencer I 3 V K VPP VPP I 5 V Global Power Supplies VDDA VDDA I 5 V VDDF VDDF I 3 V VDDL VDDL I 3 V VDDH VDDH I 5 V VDDI VDDI I 3 V VDDSYN VDDSYN I 3 V VRH VRH I 5 V VRL VRL I VSSA VSSA I VSSF VSSF I VSSSYN VSSSYN I KAPWR2 KAPWR I 3 V VDDSRAM VDDSRAM I 3 V VSS VSS I NOTES 1 All inputs are 5 V friendly All 5 V outputs are slow sle...

Page 71: ...nal lines that can request by means of the internal interrupt controller a service routine from the RCPU Reservation This line used together with the address bus to indicate that the internal core initiated a transfer as a result of a STWCX or a LWARX instruction SGPIO This function allows the pins to be used as general purpose inputs outputs 2 3 1 5 IRQ 2 CR SGPIOC 2 MTS Pin Name irq2_b_cr_b_sgpi...

Page 72: ...s to which the address applies The address type signals are valid at the rising edge of the clock in which the special transfer start STS is asserted AT 2 iden tifies an access as either data or instrucion SGPIO This function allows the pins to be used as general purpose inputs outputs 2 3 1 8 IRQ 5 SGPIOC 5 MODCK 1 Pin Name irq5_b_sgpioc5_modck1 Interrupt Request One of the eight external lines t...

Page 73: ...e ownership of the bus Every master should negate this signal before the bus relinquish Every master should negate this signal before the bus is relinquished This pin is an active negate signal and may need an external pull up resistor to ensure proper operation and signal timing specifications 2 3 1 15 TA Pin Name ta_b Transfer Acknowledge This line indicates that the slave device addressed in th...

Page 74: ...put Enable This output line is asserted when a read access to an external slave controlled by the GPCM in the memory controller is initiated by the chip 2 3 1 19 BI STS Pin Name bi_b_sts_b Burst Inhibit This bi directional active low three state line indicates that the slave device addressed in the current burst transaction is not able to support burst transfers When the chip drives out the signal...

Page 75: ...he keep alive power pins The pin has a glitch detector to ensure that low spikes of less than 20 ns are rejected The internal PORESET signal is asserted only if PORESET is asserted for more than 100 ns See SECTION 7 RESET for more details on timing 2 3 1 23 HRESET Pin Name hreset_b Hard Reset The chip can detect an external assertion of HRESET only if it occurs while the chip is not asserting rese...

Page 76: ...lush Status This output line together with VF1 and VF2 is output by the chip when a program instructions flow tracking is required by the user VF report the number of instructions flushed from the instruction queue in the internal core See SECTION 21 DEVELOPMENT SUPPORT for more details Load Store Watchpoint This output line reports the detection of a data watchpoint in the program flow executed b...

Page 77: ...low executed by the RCPU Visible History Buffer Flush Status These signals are output by the chip to enable program instruction flow tracking They report the number of instructions flushed from the history buffer in the RCPU See SECTION 21 DEVELOPMENT SUPPORT for de tails 2 3 1 31 TMS Pin Name tms Test Mode Select This input controls test mode operations for on board test logic JTAG 2 3 1 32 TDI D...

Page 78: ... 3 1 37 EXTAL Pin Name extal EXTAL This line is one of the connections to an external crystal for the internal os cillator circuitry If this pin is unused it must be grounded 2 3 1 38 XFC Pin Name xfc External Filter Capacitance This input line is the connection pin for an external ca pacitor filter for the PLL circuitry 2 3 1 39 CLKOUT Pin Name clkout Clock Out This output line is the clock syste...

Page 79: ...PADS 2 3 2 1 PCS 0 SS QGPIO 0 Pin Name pcs0_ss_b_qgpio0 PCS 0 This signal provides QSPI peripheral chip select 0 SS Assertion of this bi directional signal places the QSPI in slave mode QSPI GPIO 0 When this pin is not needed for a QSPI application it can be config ured as a general purpose input output 2 3 2 2 PCS 1 3 QGPIO 1 3 Pin Name pcs1_qgpio1 pcs3_qgpio3 3 pins PCS 1 3 These signals provide...

Page 80: ...Pin Name txd1_qgpo1 txd2_qgpo2 2 pins Transmit Data These output signals are the serial data outputs from the SCI1 and SCI2 QSCI GPO 1 2 When these pins are not needed for a SCI applications they can be configured as general purpose outputs When the transmit enable bit in the SCI control register is set to a logic 1 these pins can not function as general purpose outputs 2 3 2 7 RxD 1 2 QGPI 1 2 Pi...

Page 81: ... MDA14 can be used as the load input to the MMCSM22 modulus counter 2 3 3 3 MDA 15 27 31 Pin Name mda15 mda27 mda31 6 pins Double Action Each of these pins provide a path for two 16 bit input captures and two 16 bit output compares 2 3 3 4 MPWM 0 3 16 19 Pin Name mpwm0 mpwm3 mpwm16 mpwm19 8 pins Pulse Width Modulation These pins provide variable pulse width output signals at a wide range of freque...

Page 82: ...rammable timed events 2 3 4 2 T2CLK Pin Name a_t2clk 1 pin for first TPU b_t2clk 1 pin for second TPU T2CLK This signal is used to clock or gate the timer count register 2 TCR2 within the TPU This pin is an output only in special test mode 2 3 5 QADC_A QADC_B PADS 2 3 5 1 ETRIG 1 2 Pin Name etrig1 etrig2 ETRIG These are the external trigger inputs to the QADC_A and QADC_B modules ETRIG 1 can be co...

Page 83: ...NY Externally multiplexed analog input Port PQB2 Input only port This is a 5 V input This path is synchronized in the pad The input is level shifted before it is sent internally to the QADC 2 3 5 5 AN 3 ANZ PQB 3 _ A B Pin Name a_an3_anz_pqb3 1 pin for first QADC b_an3_anz_pqb3 1 pin for sec ond QADC Analog Input AN3 Internally multiplexed input only analog channel The input is passed on as a sepa...

Page 84: ...n55_pqa3 b_an59_pqa7 5 pins for second QADC Analog Input AN 55 59 Input only The input is passed on as a separate signal to the QADC Port PQA 3 7 Bi directional 2 3 5 9 VRH Pin Name vrh VRH Input pin for high reference voltage for the QADC_A and QADC_B modules 2 3 5 10 VRL Pin Name vrl VRL Input pin for low reference voltage for the QADC_A and QADC_B modules 2 3 5 11 VDDA Pin Name vdda VDDA Power ...

Page 85: ...Input Flash supply voltage 5 V supply used during program and erase oper ations of the CMF 2 3 7 3 VDDF Pin Name vddf VDDF Flash core voltage input 3 V supply This separate supply voltage is needed in order to reduce noise in the read path of CMF 2 3 7 4 VSSF Pin Name vssf VSSF Flash core zero supply input This separate supply is needed in order to re duce noise in the read path of CMF 2 3 8 GLOBA...

Page 86: ...d to a value during reset by a 130 microampere resistor based on certain con ditions In reset state all I O pins become inputs and all outputs except clkout hreset_b sreset_b will be pulled only by the pull up pull down 2 4 1 Pin Functionality Out of Reset The functionality out of reset of some pins that support multiple functionality is defined in the SIUMCR through the reset configuration word F...

Page 87: ...28 29 30 31 RESERVED HARD RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 2 3 PDMCR Bit Descriptions Bit s Name Description 0 SLRC0 SLRC0 controls the slew rate of the following modules TPU QADC USIU SGPIO 0 Slow slew rate for pins Controls slew rate pins of 200 ns 1 Normal slew rate for pins 1 SLRC1 SLRC1 controls the slew rate of the QSPI and TouCAN modules 0 Slow slew rate for pins Controls slew ra...

Page 88: ...vices are either disabled immediately at the negation of reset or remain enabled Hard reset can occur at any time and there may be a bus cycle pending For this rea son the bits in PDMCR that control the enabling and disabling of the pull up or pull down resistors in the pads are set or reset synchronously PORESET affects these bits asynchronously This causes the pull up or pull down resistors to b...

Page 89: ... it remains in this mode until any external bus access completes After this the 3 V 5 V select signal switches to 5 V mode to enable the pull ups This ensures that there is no con tention on the bus due to the pull up being enabled This signal is not affected by soft reset Each pad group has a 3 V 5 V select signal Internal to the pad logic combines these signals to control the pull up 2 4 6 3 Exa...

Page 90: ... released SPRDS is asserted This disables the pull up resistor immediately The output driver drives the pin to the required state after reset 2 4 8 Pin Reset States Table 2 4 summarizes the reset states of all the pins on the MPC555 MPC556 Table 2 4 Pin Reset State Pin Function Port Voltage Reset State USIU ADDR 8 31 SGPIOA 8 31 ADDR 8 31 I O 3 V PU5 until reset negates1 SGPIOA 8 31 IO 5 V PU5 unt...

Page 91: ...r to ne gate the pin in appropriate time RSTCONF TEXP3 RSTCONF I 3 V PU3 when driver not enabled or until SPRDS is set TEXP O 3 V OE OE O 3 V PU3 until reset negates BI STS BI4 I O 3 V PU3 when driver not enabled or until SPRDS is set STS O 3 V CS 0 3 CS 0 3 O 3 V PU3 until reset negates WE 0 3 BE 0 3 AT 0 3 WE 0 3 BE 0 3 O 3 V PU3 when driver not enabled or until SPRDS is set AT 0 3 O 3 V PORESET...

Page 92: ...or until SPRDS is set VF 2 O 3 V IWP 3 O 3 V IWP 0 1 VFLS 0 1 IWP 0 1 O 3 V PU3 until reset negates VFLS 0 1 O 3 V TMS TMS I 3 V PU3 until SPRDS is set TDI DSDI TDI I 3 V PU3 until SPRDS is set DSDI I 3 V TCK DSCK TCK I 3 V PD until SPRDS is set DSCK I 3 V TDO DSDO TDO O 3 V PU3 until reset negates DSDO O 3 V TRST TRST I 3 V PU3 until SPRDS is set XTAL3 XTAL I 3 V EXTAL3 EXTAL I 3 V XFC XFC I 3 V ...

Page 93: ...PRDS is set MPIO32B 0 2 I O 5 V VFLS 0 1 MPIO32B 3 4 VFLS 0 1 O 3 V PU5 until PRDS is set MPIO32B 3 4 I O 5 V MPIO32B 5 15 MPIO32B 5 15 I O 5 V PU5 until PRDS is set TPU_A TPU_B A TPUCH 0 15 TPUCH 0 15 I O 5 V PU5 until PRDS is set A T2CLK T2CLK I O 5 V PU5 when driver not enabled2 B TPUCH 0 15 TPUCH 0 15 I O 5 V PU5 until PRDS is set B T2CLK T2CLK I O 5 V PU5 when driver not enabled2 QADC_A QADC_...

Page 94: ...5 V PU5 until PRDS is set ANY I 5 V PU5 until PRDS is set PQB2 I 5 V PU5 until PRDS is set B AN3 ANZ PQB3 AN3 I 5 V PU5 until PRDS is set ANZ I 5 V PU5 until PRDS is set PQB3 I 5 V PU5 until PRDS is set B AN 48 51 PQB 4 7 AN 48 51 I 5 V PU5 until PRDS is set PQB 4 7 I 5 V PU5 until PRDS is set B AN 52 54 MA 0 2 PQA 0 2 AN 52 54 I 5 V PU5 until PRDS is set MA 0 2 I 5 V PU5 until PRDS is set PQA 0 2...

Page 95: ...put driver For 3 V 5 V pads the appropri ate driver is enabled based on the pin functionality selected Input enable Enables the receiver For 3 V 5 V pads the appropriate receiver is enabled based on the pin functionality selected CMF EPEE EPEE I 3 V PD VPP VPP I 5 V VDDF VDDF I 3 V VSSF VSSF I 3 V Global Power Supplies VDDL VDDL I 3 V VDDH VDDH I 5 V VDDI VDDSI I 3 V VSSI VSSI I 3 V KAPWR3 KAPWR I...

Page 96: ...ull down resistor for the SGPIO pins and the pins for the modules on the UIMB Special pull resistor disable select SPRDS Reflects the state of the SPRDS bit in the PDMCR For pins that support bus arbitration functionality multiplexed with opcode tracking and debug functionality this signal controls the pull up re sistors Analog Analog input signals to the QADC The corresponding digital interface s...

Page 97: ...or three states the output Figure 2 4 Type B Interface 2 5 3 Three Volt Input Pad Four subtypes are defined for the 3 V input only pad one with a pull up resistor one with a pull up resistor and with or without hysteresis in the receiver one with hysteresis 3 V Driver Logic Data Out Pin OE 3 V Drive Sel Sprds 3 V Driver Logic Data Out Pin OE Drive Sel Freescale Semiconductor I Freescale Semiconduc...

Page 98: ...input with a pull up resistor Figure 2 5 Type C Interface 2 5 3 2 Type CH Interface Pad type CH has a 3 V input with hysteresis and a pull up resistor The hyst_sel signal selects the receiver with or without hysteresis Figure 2 6 Type CH Interface 3 V Receiver Pin 3 V Data In Sprds Pin 3 V Data In 3 V Receiver 3 V hyst_sel Sprds Freescale Semiconductor I Freescale Semiconductor Inc For More Inform...

Page 99: ... and an internal pull down resistor Figure 2 8 Type D Interface 2 5 4 Three Volt Input Output Pad This is a 3 V bi directional pad with a pull up device The drive strength for the output driver can be configured for either a 25 pF or a 50 pF load The SPRDS and OE sig nals control the pull up devices 3 V Receiver Pin 3 V Data In 3 V Receiver Pin 3 V Data In Sprds Freescale Semiconductor I Freescale...

Page 100: ...is connected to VSS to disable the open drain drive Figure 2 9 Type E Interface 2 5 4 2 Type EOH Interface In this pad type the data interface to the internal logic has separate paths for input and output The receiver has hysteresis The pull up is active when the driver is not en abled 3 V Driver 3 V Receiver Logic Data Out Pin OE IE 3 V Data In Drive Sel OD Enable Sprds Freescale Semiconductor I ...

Page 101: ...this pad type the data interface to the internal logic has the same path for both input and output The pull up is inactive when the driver is enabled 3 V OD Driver 3 V Receiver Logic Data Out Pin OE IE 3 V Data In Drive Sel Sprds Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 102: ...ace to the internal logic has the same path for both input and output This pad type also has the SPRDS signal as an input to disable the resistor when the pad is a non bus function Data IO Pin OE IE 3 V Drive Sel Sprds OD Driver Receiver Logic 3 V 3 V Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 103: ...as a 5 V input output function A 3 V 5 V sel interface signal determines which driver gets selected This pad type has two separate data output paths These paths are multiplexed onto the output pin based on the 3 V 5 V select signal This pad also has a dedicated syn chronous input path If only one of the output paths is used on a device the other can be connected to ground In this case the 3 V 5 V ...

Page 104: ...tput function A 3 V 5 V sel interface signal indicates which driver gets selected The data inter face to the internal logic has separate paths for input and output 3 V Driver Receiver Logic 5 V Data Out Pin OE Synch Clk 3 V 5 V Sel PRDS 5 V Synch Drive Sel 3 V Data Out Data In SLRC 5 V Synch 5 V Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www fr...

Page 105: ...rmines which driver gets selected In this pad type the data interface to the internal logic has separate paths for input and output The 3 V receiver has 2 possible paths with or without hysteresis The hyst_sel signal selects the appropriate path 3 V Driver 3 V Receiver Logic Data Out Pin OE IE 3 V 5 V Sel PRDS 5 V Data In Drive Sel SLRC 5 V 5 V Freescale Semiconductor I Freescale Semiconductor Inc...

Page 106: ...input output function A 3 V 5 V sel interface signal indicates which driver gets selected The data inter face to the internal logic has the same path for both input and output 5 V 3 V Driver 5 V 3 V Receiver Logic Data Out Pin OE IE 3 V 5 V Sel PRDS 5 V Data In Drive Sel 3 V hyst_sel SLRC Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale...

Page 107: ...3 V 5 V sel interface signal indicates which driver gets selected The data interface to the internal logic has the same path for both input and output The pad has a pull down resistor which is activated by reset and or PRDS 5 V 3 V Driver 5 V 3 V Receiver Logic Pin 5 V PRDS 3 V 5 V Sel Data OE Drive Sel SLRC IE Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Prod...

Page 108: ...to see that a transition to a new state on the pin is maintained for at least two clocks before the information is passed on internally to the sequencer implemented in the flash The synchronizer clock to this pad is GCLK2 5 V 3 V Driver 3 V Receiver Logic Data Pin OE IE 3 V 5 V Sel PRDS Drive Sel SLRC 5 V Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go...

Page 109: ...hat is mul tiplexed on the pin 2 5 7 1 Type L Interface QADC Port A This pad is used for interfacing to the port A of the QADC The digital portion of the pad supports bi directional operation The receiver has a synchronizer The digital in put is level shifted from 5 V to 3 V before it is sent internally to the QADC Data Pin Synch Clk Sequencer 1 1 0 0 0 0 1 1 1 1 0 0 Freescale Semiconductor I Free...

Page 110: ...er The digital input is level shifted from 5 V to 3 V before it is sent internally to the QADC Figure 2 20 Type M Interface Pin Analog OD Driver Synch Rx Digital Level Shifter Analog In Dig Out Data Direction Dig In Input Enable Sync Clk PRDS 5 V Pin Analog Synch Rx Digital Level Shifter Analog In Dig In Input Enable Sync Clk PRDS PRDS 5 V Freescale Semiconductor I Freescale Semiconductor Inc For ...

Page 111: ...to the TPU and MIOS have a fast mode provision 2 5 8 1 Type O Interface QSMCM Pads This pad is used for interfacing to the QSMCM It is a 5 V bi directional pad and has provision for a fast mode in which the slow slew rate driver is bypassed and data is driven by a fast slew rate driver When the pin is an input the data can be driven either synchronously or asynchronously A pull up device is availa...

Page 112: ...ins In addition the receiver has a digital filter some what like the sequencer for the EPEE pad to check for a state on the pin for a particular number of clocks The pad also has a pull up device Depending on the reset state see Table 2 4 the pull up may be controlled by the PRDS signal Driver Receiver Logic Pin 5 V Driver Slow Fast Receiver 5 V 5 V 5 V Synch 5 V SLRC OD Enable PRDS Data Out OE No...

Page 113: ... and fast drive capability The driver is con figureable to be either push pull or open drain using the OD enable signal This pad type has a pull up device that can be controlled using the PRDS signal Driver Logic Pin 5 V Driver Slow Fast Hysteresis 5 V Receiver 5 V 5 V Synch SLRC PRDS Data Out OE Synch Clk Synch Data In Freescale Semiconductor I Freescale Semiconductor Inc For More Information On ...

Page 114: ...nous data are driven in from the internal module that interfaces to this pad A pull up device can be controlled using the PRDS signal Figure 2 25 Type R Interface Logic Pin 5 V Driver Driver Slow Fast 5 V 5 V PRDS OD Enable Data Out OE SLRC Receiver Pin Synch Clk 5V Normal Receiver Synch Data In Data In PRDS 5 V Synch 5 V Freescale Semiconductor I Freescale Semiconductor Inc For More Information O...

Page 115: ...t of reset in the reset section of the document The following is a list of pad groups which were obtained based on the 3 V 5 V se lection from the information in the pin configuration out of reset tables In other words each group receives a different encoded 3 V 5 V select signal All pins that drive 3 V have the provision to choose between drive strengths for a 25 pF load or a 50 pF load Table 2 5...

Page 116: ...p 10 V4 addr_sgpioa 11 addr_sgp 11 V3 addr_sgpioa 12 addr_sgp 12 W1 addr_sgpioa 13 addr_sgp 13 Y2 addr_sgpioa 14 addr_sgp 14 W3 addr_sgpioa 15 addr_sgp 15 Y3 addr_sgpioa 16 addr_sgp 16 W4 addr_sgpioa 17 addr_sgp 17 Y4 addr_sgpioa 18 addr_sgp 18 W5 addr_sgpioa 19 addr_sgp 19 Y5 addr_sgpioa 20 addr_sgp 20 W6 addr_sgpioa 21 addr_sgp 21 Y6 addr_sgpioa 22 addr_sgp 22 V7 addr_sgpioa 23 addr_sgp 23 W7 ad...

Page 117: ... V15 data_sgpiod 22 data_sgp 22 V14 data_sgpiod 23 data_sgp 23 U14 data_sgpiod 24 data_sgp 24 V13 data_sgpiod 25 data_sgp 25 U13 data_sgpiod 26 data_sgp 26 V12 data_sgpiod 27 data_sgp 27 U12 data_sgpiod 28 data_sgp 28 V11 data_sgpiod 29 data_sgp 29 U11 data_sgpiod 30 data_sgp 30 V10 data_sgpiod 31 data_sgp 31 V9 IRQ 0 SGPIOC 0 irq0_b_sgpioc0 irq0b_sgp M1 IRQ 1 RSV SGPIOC 1 irq1_b_rsv_b_sgpioc1 irq...

Page 118: ...c6_frz_ptr_b sgp_frz K3 SGPIOC 7 IRQOUT LWP 0 sgpioc7_irqout_b_lwp0 sgp_irqoutb M4 BG VF 0 LWP 1 bg_b_vf0_lwp1 bgb_lwp1 N3 BR VF 1 IWP 2 br_b_vf1_iwp2 brb_iwp2 N2 BB VF 2 IWP 3 bb_b_vf2_iwp3 bbb_iwp3 N4 IWP 0 1 VFLS 0 1 iwp0_vfls0 iwp0_vfls L2 iwp1_vfls1 iwp1_vfls L1 TMS tms tms K1 TDI DSDI tdi_dsdi tdi_dsdi K2 TCK DSCK tck_dsck tck_dsck J1 TDO DSDO tdo_dsdo tdo_dsdo J2 TRST trst_b trst_b J3 XTAL ...

Page 119: ... mda11 mda11 A17 mda12 mda12 A18 mda13 mda13 A19 mda14 mda14 B17 mda15 mda15 B18 MDA 27 31 mda27 mda27 C17 mda28 mda28 B20 mda29 mda29 C18 mda30 mda30 C19 mda31 mda31 C20 MPWM 0 3 16 19 mpwm0 mpwm0 E17 mpwm1 mpwm1 D18 mpwm2 mpwm2 D19 mpwm3 mpwm3 D20 mpwm16 mpwm16 F17 mpwm17 mpwm17 E18 mpwm18 mpwm18 F18 mpwm19 mpwm19 E19 VF 0 2 MPIO32B 0 2 vf0_mpio32b0 vf0_mpio0 J19 vf1_mpio32b1 vf1_mpio1 J20 vf2_m...

Page 120: ... D3 a_tpuch1 a_tpuch1 A2 a_tpuch2 a_tpuch2 D4 a_tpuch3 a_tpuch3 C3 a_tpuch4 a_tpuch4 A3 a_tpuch5 a_tpuch5 D5 a_tpuch6 a_tpuch6 B3 a_tpuch7 a_tpuch7 C4 a_tpuch8 a_tpuch8 A4 a_tpuch9 a_tpuch9 C5 a_tpuch10 a_tpuch10 B4 a_tpuch11 a_tpuch11 B5 a_tpuch12 a_tpuch12 A5 a_tpuch13 a_tpuch13 C6 a_tpuch14 a_tpuch14 B6 a_tpuch15 a_tpuch15 A6 A T2CLK a_t2clk a_t2clk C2 Table 2 6 Pin Names and Abbreviations Cont...

Page 121: ...aan2_pqb2 C8 A AN3 ANZ PQB3 a_an3_anz_pqb3 aan3_pqb3 B8 A AN 48 51 PQB 4 7 a_an48_pqb4 aan48_pqb4 A9 a_an49_pqb5 aan49_pqb5 B9 a_an50_pqb6 aan50_pqb6 D9 a_an51_pqb7 aan51_pqb7 C9 A AN 52 54 MA 0 2 PQA 0 2 a_an52_ma0_pqa0 aan52_pqa0 A10 a_an53_ma1_pqa1 aan53_pqa1 B10 a_an54_ma2_pqa2 aan54_pqa2 A11 A AN 55 56 PQA 3 4 a_an55_pqa3 aan55_pqa3 D10 a_an56_pqa4 aan56_pqa4 C10 A AN 57 59 PQA 5 7 a_an57_pqa...

Page 122: ... vrl vrl A7 VDDA vdda vdda C7 VSSA vssa vssa D7 TOUCAN_A TOUCAN_B A CNTX0 a_cntx0 a_cntx0 K19 B CNTX0 b_cntx0 b_cntx0 H4 A CNRX0 a_cnrx0 a_cnrx0 K20 B CNRX0 b_cnrx0 b_cnrx0 H3 CMF EPEE epee epee P18 VPP vpp vpp P17 VDDF vddf vddf R18 VSSF vssf vssf P19 Global Power Supplies VDDL vddl vddl D17 E4 K4 K17 R17 T4 U10 U15 VDDH vddh vddh A1 A16 A20 B2 B19 P20 Y1 Y20 W2 W19 VDDI vddi vddi T17 U5 D6 D16 K...

Page 123: ...ngle clock cycle execution for many instructions Five independent execution units and two register files Independent LSU for load and store operations BPU featuring static branch prediction A 32 bit IU Fully IEEE 754 compliant FPU for both single and double precision opera tions Thirty two general purpose registers GPRs for integer operands Thirty two floating point registers FPRs for single or do...

Page 124: ...AD STORE FLOATING DATA LOAD INTEGER STORE DATA LOAD ADDRESS STORE ALU BFU IMUL IDIV GPR HISTORY GPR 32 X 32 CONTROL REGS NEXT ADDRESS GENERATION BRANCH UNIT PROCESSOR INSTRUCTION QUEUE PRE FETCH INSTRUCTION SEQUENCER RCPU L DATA L ADDR SO U RCE BU SES 4 SLO TS C LO CK I DATA I ADDR WRITE BACK BUS 2 SLOTS CLOCK Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Produ...

Page 125: ...tructions from the pre fetch queue and uses static branch prediction on unresolved conditional branches to allow the instruction unit to fetch instructions from a predicted target instruction stream while a conditional branch is evaluated The BPU folds out branch instructions for uncondi tional branches or conditional branches unaffected by instructions in the execution stage Instructions issued b...

Page 126: ...look ahead operations For example since branch instructions do not depend on GPRs branches can often be resolved early eliminating stalls caused by taken branches Table 3 1 summarizes the RCPU execution units INSTRUCTION ADDRESS GENERATOR CC UNIT 32 32 READ WRITE BUSES BRANCH INSTRUCTION BUFFER 32 INSTRUCTION MEMORY SYSTEM EXECUTION UNITS AND REGISTERS FILES CONDITION EVALUATION INSTRUCTION PRE FE...

Page 127: ...cated registers rather than general purpose or floating point registers execution of branch instructions is independent from execution of integer instructions 3 4 2 Integer Unit IU The IU executes all integer processor instructions except the integer storage access instructions which are implemented by the load store unit The IU contains the follow ing subunits The IMUL IDIV unit includes the impl...

Page 128: ...ernal on chip data RAM resulting in two clocks latency Double word accesses require two clocks resulting in three clocks latency Since the L bus is 32 bits wide double word transfers require two bus accesses The load store unit performs zero fill for byte and half word transfers and sign extension for half word transfers Addresses are formed by adding the source one register operand specified by t...

Page 129: ...the two source operands Load and store instructions transfer data between memory and on chip registers PowerPC processors have two levels of privilege supervisor mode of operation typi cally used by the operating environment and user mode of operation used by the ap plication software The programming models incorporate 32 GPRs special purpose registers SPRs and several miscellaneous registers Supe...

Page 130: ...Floating Point Status and Control Register FPSCR CR 0 31 0 31 0 31 GPR0 GPR1 GPR31 User Level SPRs Integer Exception Register XER Link Register LR Count Register CTR 0 31 0 63 0 31 Time Base Lower Read TBL Time Base Upper Read TBU Time Base Facility for Reading USER MODEL UISA FPR0 FPR1 FPR31 See Table 3 2 for list of supervisor level SPRs See Table 3 3 for list of development support SPRs Freesca...

Page 131: ... and NRI Special Purpose Reg isters for bit descriptions 82 Non Recoverable Interrupt NRI 1 See 3 9 10 1 EIE EID and NRI Special Purpose Reg isters for bit descriptions 272 SPR General 0 SPRG0 See 3 9 8 General SPRs SPRG0 SPRG3 for bit de scriptions 273 SPRGeneral 1 SPRG1 See 3 9 8 General SPRs SPRG0 SPRG3 for bit de scriptions 274 SPR General 2 SPRG2 See 3 9 8 General SPRs SPRG0 SPRG3 for bit de ...

Page 132: ...Table 11 8 for bit descriptions 816 IMPU Region Attribute Register 0 MI_RA0 1 See Table 4 6 for bit descriptions 817 IMPU Region Attribute Register 1 MI_RA1 1 See Table 4 6 for bit descriptions 818 IMPU Region Attribute Register 2 MI_RA2 1 See Table 4 6 for bit descriptions 819 IMPU Region Attribute Register 3 MI_RA3 1 See Table 4 6 for bit descriptions 824 L2U Region Attribute Register 0 L2U_RA0 ...

Page 133: ...it descriptions 148 Exception Cause Register ECR See Table 21 27 for bit descriptions 149 Debug Enable Register DER See Table 21 28 for bit descriptions 150 Breakpoint Counter A Value and Control COUNTA See Table 21 25 for bit descriptions 151 Breakpoint Counter B Value and Control COUNTB See Table 21 26 for bit descriptions 152 Comparator E Value Register CMPE See Table 21 18 for bit descriptions...

Page 134: ...nstructions operate on data located in FPRs and with the exception of the compare instructions which update the CR place the result into an FPR Information about the status of floating point operations is placed into the float ing point status and control register FPSCR and in some cases into the CR after the completion of the operation s writeback stage For information on how the CR is affect ed ...

Page 135: ...X are the logical ORs of other FPSCR bits Therefore these two bits are not listed among the FPSCR bits directly affected by the various instructions A listing of FPSCR bit descriptions is shown in Table 3 5 Table 3 4 FPSCR Bit Categories Bits Type 0 3 12 21 23 Status sticky 1 2 13 20 Status not sticky 24 31 Control FPSCR Floating Point Status and Control Register MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 1...

Page 136: ...r SNaN This is a sticky bit 8 VXISI Floating point invalid operation exception for This is a sticky bit 9 VXIDI Floating point invalid operation exception for This is a sticky bit 10 VXZDZ Floating point invalid operation exception for 0 0 This is a sticky bit 11 VXIMZ Floating point invalid operation exception for 0 This is a sticky bit 12 VXVC Floating point invalid operation exception for inval...

Page 137: ...es that software can simulate fsqrt and frsqrte and to provide a consistent interface to han dle exceptions caused by square root operations 23 VXCVI Floating point invalid operation exception for invalid integer convert This is a sticky bit 24 VE Floating point invalid operation exception enable 25 OE Floating point overflow exception enable 26 UE Floating point underflow exception enable This bi...

Page 138: ...an unsigned quantity or a bit string can be deduced from the EQ bit The CR0 bits are interpreted as shown in Table 3 7 If any portion of the result the 32 bit value placed into the destination register is undefined the value placed in the first three bits of CR0 is undefined 3 7 4 2 Condition Register CR1 Field Definition In all floating point instructions when the CR is set to reflect the result ...

Page 139: ...uctions CRn Bit1 NOTES 1 Here the bit indicates the bit number in any one of the four bit subfields CR0 CR7 Description 0 Less than floating point less than LT FL For integer compare instructions rA SIMM UIMM or rB algebraic comparison or rA SIMM UIMM or rB logical comparison For floating point compare instructions frA frB 1 Greater than floating point greater than GT FG For integer compare instru...

Page 140: ...ow SO The summary overflow bit is set whenever an instruction sets the overflow bit OV to indicate overflow and remains set until software clears it It is not altered by compare instructions or other instructions that cannot overflow 1 OV Overflow OV The overflow bit is set to indicate that an overflow has occurred during exe cution of an instruction Integer and subtract instructions having OE 1 s...

Page 141: ...MPC555 MPC556 Internal Clock Signals and 8 12 1 System Clock Control Register SC CR The TB consists of two 32 bit registers time base upper TBU and time base lower TBL In the context of the VEA user level applications are permitted read only ac cess to the TB The OEA defines supervisor level access to the TB for writing values to the TB Different SPR encodings are provided for reading and writing ...

Page 142: ...re loaded into SRR1 and the MSR is updated to reflect the exception processing machine state The MSR can also be modified by the mtmsr sc and rfi instructions It can be read by the mfm sr instruction Table 3 12 shows the bit definitions for the MSR MSR Machine State Register MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESERVED POW 0 ILE RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 2...

Page 143: ...cessed 1 The processor can execute floating point instructions and can take floating point enabled ex ception type program exceptions 19 ME Machine check enable 0 Machine check exceptions are disabled 1 Machine check exceptions are enabled 20 FE0 Floating point exception mode 0 See Table 3 13 21 SE Single step trace enable 0 The processor executes instructions normally 1 The processor generates a ...

Page 144: ...ocessor operates in little endian mode during normal processing NOTES 1 This bit is only available on the MPC556 Table 3 13 Floating Point Exception Mode Bits FE 0 1 Mode 00 Ignore exceptions mode Floating point exceptions do not cause the floating point assist error handler to be invoked 01 10 11 Floating point precise mode The system floating point assist error handler is invoked precisely at th...

Page 145: ...elay The DEC satisfies the following requirements Loading a GPR from the DEC has no effect on the DEC Storing a GPR to the DEC replaces the value in the DEC with the value in the GPR Whenever bit 0 of the DEC changes from zero to one a decrementer exception request unless masked is signaled Multiple DEC exception requests may be re ceived before the first exception occurs however any additional re...

Page 146: ...xception type SRR0 addresses either the instruction causing the exception or the immediately following instruction The instruction addressed can be determined from the exception type and status bits When an exception occurs SRR0 is set to point to an instruction such that all prior in structions have completed execution and no subsequent instruction has begun execu tion The instruction addressed b...

Page 147: ...4 25 26 27 28 29 30 LSB 31 SRR1 RESET UNDEFINED SPRG0 SPRG3 General Special Purpose Registers 0 3 SPR 272 SPR 275 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LSB 31 SPRG0 SPRG1 SPRG2 SPRG3 RESET UNCHANGED Table 3 15 Uses of SPRG0 SPRG3 Register Description SPRG0 Software may load a unique physical address in this register to identify an area of memory res...

Page 148: ...Floating Point Exception Cause Register FPECR The FPECR is a 32 bit supervisor level internal status and control register used by the floating point assist firmware envelope It contains four status bits indicating whether the result of the operation is tiny and whether any of three source operands are denor malized In addition it contains one control bit to enable or disable SIE mode This reg iste...

Page 149: ... 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LSB 31 RESERVED DNC DNB DNA TR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3 18 FPECR Bit Descriptions Bit s Name Description 0 SIE SIE mode control bit 0 Disable SIE mode 1 Enable SIE mode 1 27 Reserved 28 DNC Source operand C denormalized status bit 0 Source operand C is not denormalized 1 Source operand C is denormalized 29 DNB Source ...

Page 150: ...ger and floating point load and store instruc tions Integer load and store instructions Integer load and store multiple instructions Floating point load and store Primitives used to construct atomic memory operations lwarx and stwcx in structions Flow control instructions include branching instructions condition register logical instructions trap instructions and other instructions that affect the...

Page 151: ...rD rA rB Add Extended addi rD rA SIMM Add Immediate addic rD rA SIMM Add Immediate Carrying addic rD rA SIMM Add Immediate Carrying and Record addis rD rA SIMM Add Immediate Shifted addme addme addmeo addmeo rD rA Add to Minus One Extended addze addze addzeo addzeo rD rA Add to Zero Extended and and rA rS rB AND andc andc rA rS rB AND with Complement andi rA rS UIMM AND Immediate andis rA rS UIMM ...

Page 152: ... fmsub frD frA frC frB Floating Multiply Subtract Double Precision fmsubs fmsubs frD frA frC frB Floating Multiply Subtract Single fmul fmul frD frA frC Floating Multiply Double Precision fmuls fmuls frD frA frC Floating Multiply Single fnabs fnabs frD frB Floating Negative Absolute Value fneg fneg frD frB Floating Negate fnmadd fnmadd frD frA frC frB Floating Negative Multiply Add Double Preci si...

Page 153: ...Load Word and Reserve Indexed lwbrx rD rA rB Load Word Byte Reverse Indexed lwz rD d rA Load Word and Zero lwzu rD d rA Load Word and Zero with Update lwzux rD rA rB Load Word and Zero with Update Indexed lwzx rD rA rB Load Word and Zero Indexed mcrf crfD crfS Move Condition Register Field mcrfs crfD crfS Move to Condition Register from FPSCR mcrxr crfD Move to Condition Register from XER mfcr rD ...

Page 154: ...yte with Update Indexed stbx rS rA rB Store Byte Indexed stfd frS d rA Store Floating Point Double stfdu frS d rA Store Floating Point Double with Update stfdux frS rB Store Floating Point Double with Update Indexed stfdx frS rB Store Floating Point Double Indexed stfiwx frS rB Store Floating Point as Integer Word Indexed stfs frS d rA Store Floating Point Single stfsu frS d rA Store Floating Poin...

Page 155: ...index EA rA 0 rB register indirect with index These simple addressing modes allow efficient address generation for memory ac cesses Calculation of the effective address for aligned transfers occurs in a single clock cycle stwbrx rS rA rB Store Word Byte Reverse Indexed stwcx rS rA rB Store Word Conditional Indexed stwu rS d rA Store Word with Update stwux rS rA rB Store Word with Update Indexed st...

Page 156: ...vice register DSISR Addition ally some exception conditions can be explicitly enabled or disabled by software 3 11 1 Exception Classes The MPC555 MPC556 exception classes are shown in Table 3 20 3 11 2 Ordered Exceptions In the MPC555 MPC556 all exceptions except for reset debug port non maskable interrupts and machine check exceptions are ordered Ordered exceptions satisfy the following criteria ...

Page 157: ...ly defined state The following conditions exist at the point a precise ex ception occurs 1 Architecturally no instruction following the faulting instruction in the code stream has begun execution 2 All instructions preceding the faulting instruction appear to have completed with respect to the executing processor 3 SRR0 addresses either the instruction causing the exception or the immediate ly fol...

Page 158: ...tion register is copied to the history buffer If a data dependency exists the machine is stalled until the dependency is re solved Table 3 21 Exception Vector Offset Table Vector Offset Hexadecimal Exception Type 00000 Reserved 00100 System reset NMI interrupt 00200 Machine check 00300 Reserved 00400 Reserved 00500 External interrupt 00600 Alignment 00700 Program 00800 Floating point unavailable 0...

Page 159: ... machine When an exception is taken all instructions following the excepting instruction are canceled i e the values of the affected destination registers are restored using the values saved in the history buffer during the dispatch stage Figure 3 4 shows basic instruction pipeline timing Figure 3 4 Basic Instruction Pipeline Table 3 22 indicates the latency and blockage for each type of instructi...

Page 160: ...cause register XER and the reserved bits of the machine state register MSR which are set by the source value on write and return the value last set for it on read 3 13 3 Classes of Instructions Non optional instructions are implemented by the hardware Optional instructions are executed by implementation dependent code and any attempt to execute one of these commands causes the MPC555 MPC556 to tak...

Page 161: ...instructions refer to Table 3 22 of this manual 3 13 7 1 Invalid Branch Instruction Forms Bits marked with z in the BO encoding definition are discarded by the MPC555 MPC556 decoding Thus these types of invalid form instructions yield result of the de fined instructions with the z bit zero If the decrement and test CTR option is specified for the bcctr or bcctrl instructions the target address of ...

Page 162: ...0x80000000 and if Rc 1 the contents of bits in CR field 0 are LT 1 GT 0 EQ 0 and SO is set to the correct value In cmpi cmp cmpli and cmpl instructions the L bit is applicable for 64 bit implementations In 32 bit implementations if L 1 the instruction form is invalid The core ignores this bit and therefore the behavior when L 1 is identical to the valid form instruction with L 0 3 13 9 Floating Po...

Page 163: ...alignment error handler is invoked 3 13 10 5 Floating Point Load and Store With Update Instructions For Load and Store with update instructions if RT 0 then the EA is written into R0 3 13 10 6 Floating Point Load Single Instructions In case the operand falls in the range of a single denormalized number the floating point assist interrupt handler is invoked Refer to RCPU Reference Manual Floating P...

Page 164: ...provision is made to cancel the reservation inside the MPC555 MPC556 by using the CR_B and KR_B input pins 3 14 2 Effect of Operand Placement on Performance The load store unit hardware supports all of the PowerPC load store instructions An optimal performance is obtained for naturally aligned operands These accesses result in optimal performance one bus cycle for up to 4 bytes size and good perfo...

Page 165: ... be ac cessed by any external system master 3 15 1 Branch Processor Registers 3 15 1 1 Machine State Register MSR The floating point exception mode encoding in the MPC555 MPC556 core is as fol lows The SF bit is reserved set to zero The IP bit initial state after reset is set as programmed by the reset configuration as specified by the USIU specification 3 15 1 2 Branch Processors Instructions The...

Page 166: ...e can be issued and then aborted In each interrupt handler when registers SRR0 and SRR1 are saved MSRRI can be set to 1 The following paragraphs define the types of OEA interrupts The exception table vec tor defines the offset value by interrupt type Refer to Table 3 21 3 15 4 1 System Reset Interrupt A system reset interrupt occurs when the IRQ0 pin is asserted and the following reg isters are se...

Page 167: ...this condi tion Refer to SECTION 7 RESET for more details If the machine check interrupt is enabled MSRME 1 it is taken If SRR1 Bit 30 1 the interrupt is recoverable and the following registers are set For load store bus cases these registers are also set Execution resumes at offset 0x00200 from the base address indicated by MSRIP 3 15 4 3 Data Storage Interrupt A data storage interrupt is never g...

Page 168: ...ception type program interrupt is not generated by floating point arithmetic instructions In stead if MSRFE0 MSRFE1 FPSCRFEX is set the floating point assist interrupt is generated 3 15 4 7 Illegal Instruction Type Program Interrupt An illegal instruction type program interrupt is not generated by the MPC555 MPC556 An implementation dependent software emulation interrupt is generated in stead 3 15...

Page 169: ...nt exception condition is detected the corresponding floating point enable bit in the FPSCR floating point status and control register is set ex ception enabled and MSRFE0 MSRFE1 1 Note that when MSRFE0 MSRFE1 and FPSCRFEX is set as a result of move to FPSCR move to MSR or rfi the floating point assist interrupt handler is not invoked When an intermediate result is detected and the floating point ...

Page 170: ...ult of move to FPSCR instruction move to MSR instruction or the execution of the rfi instruction Floating point enabled exception type program interrupt is not generated by float ing point arithmetic instructions instead if MSRFE0 MSRFE1 FPSCRFEX is set the floating point assist interrupt is generated In addition the following registers are set Register Name Bits Description Save Restore Register ...

Page 171: ...is to guarded storage and MSRIR 1 The following registers are set Register Name Bits Description Save Restore Register 0 SRR0 Set to the effective address of the instruction that caused the interrupt Save Restore Register 1 SRR1 1 4 Set to 0 10 15 Set to 0 Other Loaded from bits 16 31 of MSR In the current implementa tion Bit 30 of the SRR1 is never cleared except by loading a zero value from MSRR...

Page 172: ...effective address of the instruction that caused the interrupt Save Restore Register 1 SRR1 1 Set to 0 2 Set to 0 3 Set to 1 if the fetch access was to a guarded storage when MSRIR 1 otherwise set to 0 4 Set to 1 if the storage access is not permitted by the protec tion mechanism otherwise set to 0 10 Set to 0 11 15 Set to 0 Other Loaded from bits 16 31 of MSR In the current implementa tion Bit 30...

Page 173: ...Description Save Restore Register 0 SRR0 Set to the effective address of the instruction that caused the interrupt Save Restore Register 1 SRR1 1 4 Set to 0 10 15 Set to 0 Other Loaded from bits 16 31 of MSR In the current implementa tion Bit 30 of the SRR1 is never cleared except by loading a zero value from MSRRI Machine State Register MSR IP No change ME No change LE Bit is copied from ILE Othe...

Page 174: ...ore Register 0 SRR0 For I breakpoints set to the effective address of the instruc tion that caused the interrupt For L breakpoint set to the ef fective address of the instruction following the instruction that caused the interrupt For development port maskable request or a peripheral breakpoint set to the effective address of the instruction that the processor would have executed next if no interr...

Page 175: ... RA is not altered 3 15 5 Timer Facilities Descriptions of the timebase and decrementer registers can be found in SECTION 6 SYSTEM CONFIGURATION AND PROTECTION and in SECTION 8 CLOCKS AND POWER CONTROL 3 15 6 Optional Facilities and Instructions Any other OEA optional facilities and instructions except those that are discussed here are not implemented by the MPC555 MPC556 hardware Attempting to ex...

Page 176: ...PC555 MPC556 CENTRAL PROCESSING UNIT MOTOROLA USER S MANUAL Rev 15 October 2000 3 54 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 177: ... the ICDU is bypassed and the BBC is in normal function The IMPU allows the memory to be divided into four regions with different attributes as well as a default global region for memory space that is not included in either of the two regions Each of the two regions can be of size four Kbytes to four Gbytes Over lap between regions is allowed The IMPU includes registers that contain the following ...

Page 178: ...ributes Supports special attribute for debug port fetch accesses Is programmed using the MPC555 MPC556 mtspr mfspr instructions to from implementation specific special purpose registers Designed for minimum power consumption The ICDU offers the following features Instruction code on line decompression based on a fixed vocabulary bounded Huffman algorithm No need for address translation between com...

Page 179: ...uctions to from implementation specific special purpose registers Designed for minimum power consumption Compressed non compressed region with enable disable option Special reset exception vector for Decompression ON mode 4 3 Instruction VocabularyBased Compression Model Main Principles 4 3 1 Compression Model Features Implemented for PowerPC architecture Up to 30 code size reduction No need for a...

Page 180: ... vocabularies of frequently appearing PowerPC RISC instructions or instruction halves and replacing these instructions with pointers to the vocabularies Compressed and bypass field lengths may vary An example of compressed code is shown in Figure 4 2 Compression of the instructions in a vocabulary may be in one of the following modes 1 Compression of the whole instruction into four vocabulary byte...

Page 181: ...symbols corresponding to the X1 X2 X3 and X4 input bytes Therefore in order to compress a given code four vocab ularies are required This partitionong produced a better comression ratio Figure 4 3 Instruction Coding 4 1 Original Code 4 SAVED 0 4 8 8 c 10 14 18 Compressed 0 3 2 1 0 4 8 8 c 10 14 18 0 2 3 0 23 24 vocabulary1 31 15 8 7 Tx1 X1 16 X2 X3 X4 vocabulary2 vocabulary3 vocabulary4 Tx2 Tx3 Tx...

Page 182: ...s Figure 4 4 Two Streams Memory Organization Before Compression In Figure 4 4 each left and right stream line includes two original bytes of the instruc tion Figure 4 5 shows the memory after compressed streams have been put into it Figure 4 5 Two Streams Memory Organization After Compression X1 X2 X3 X4 31 0 15 16 Right Stream Left Stream Instruction Code Left Bit Pointer Right Bit Pointer Base A...

Page 183: ...bit field Each stream line may include a variable number of compressed symbols depending on how well the bytes in the original stream were compressed The decompressor has to maintain two bit pointers left and right in order to have ac cess to the start location of any instruction s half The decompressor maintains tracking of the base address to start fetching from the next address in the memory Fi...

Page 184: ...location being pointed to by the base address A zero 0 for bit 20 will indicate that the left side is resident in the base address location A one 1 for bit 20 will indicate that the right side is resident in the base address location The instruction stream side not pointed to will reside in the following address location The same line bit bit 21 reflects the relative location of the two side strea...

Page 185: ...wo Mbytes The word pointer for the conditional 0 1 Compressed Instruction Base Address x x 4 0 19 Word Pointer Base Address 22 26 27 31 Right Pointer Pointer Left Left Right X don t care Left and Right are at the base address Same_Line 0 Base Address x x 4 1 1 X 0 0 19 Word Pointer Base Address 22 26 27 31 Right Pointer Pointer Left 0 19 Word Pointer Base Address 22 26 27 31 Right Pointer Pointer ...

Page 186: ... 0 6 Base Address of the 25 25 30 31 Word Pointer from 30 31 30 31 30 31 27 31 0 25 6 16 16 0 0 0 Unconditional immediate branch instruction BEFORE compression mapping Unconditional immediate branch instruction AFTER compression mapping I form Conditional immediate branch instruction BEFORE compression mapping Conditional immediate branch instruction AFTER compression mapping B form Direct interna...

Page 187: ...ndirect branches use the regular two pointer format described above The indirect branch destination address is copied without any change from one of the following reg isters LR CTR SRR0 See the PowerPC RCPU User s Manual RCPURM AD for more details 4 3 8 Compression Process The compression process is implemented by the following steps See Figure 4 11 User code compilation linking User application c...

Page 188: ...Phase A The compression tool replaces regular PowerPC instructions by their compressed representation which contain fewer data bits The compressed data bit representation is contained in the vocabulary The vocabulary is structured into a binary bounded Huffman code tree This method has the result of the first instructions being repre sented by fewer bits Further instructions require more bits for ...

Page 189: ...cated decompressor unit in the BBC Decompression flow See Figure 4 11 RCPU provides a bit aligned COF1 address to the BBC ICDU Converts COF address to word aligned physical address to access the memory Fetches the compressed instruction code data from the memory decom presses it and delivers non compressed instruction code together with the bit aligned next instruction address to the RCPU that use...

Page 190: ...code compression when equal to 1 and disables code compression when equal to 0 Bit 22 defines the ex ception table code as either compressed with a value of 1 or non compressed with a value of 0 4 4 Modes Of Operation The burst buffer module can operate in the following modes Normal Slave Reset Debug Standby Burst The modes of operation are described in the following paragraphs Compressed Memory I...

Page 191: ...utes ac companying the CPU access along with the U bus access 4 4 2 Slave Operation The burst buffer module is operating as a U bus slave module when the instruction memory protection unit IMPU registers are accessed by the user in order to be pro grammed This programming is done using the mtspr mfspr instructions 4 4 3 Reset Operation On reset the BBC goes to an idle state and all pending U bus a...

Page 192: ...The BBC has the ability to relocate the exception table Exception table relocation is a feature to save memory space in the exception table See 3 11 5 Exception Vector Table for normal operation of the exception vector table This is done by mapping ex ceptions to be separated by eight bytes instead of 256 bytes see Table 4 1 The re location feature maps the exception table into the internal memory...

Page 193: ...ture is enabled the BBC translates the starting address of the ex ception routine into the address located at the lowest portion of the internal memory At that location the user must insert a series table of consecutive branch instructions that point to the appropriate exception routines NOTE These branch instructions must utilize absolute addressing modes of the RCPU relative branches can not be ...

Page 194: ...0x0028 0x8028 Alignment 0xFFF0_0600 0x0030 0x8030 Program 0xFFF0_0700 0x0038 0x8038 Floating Point unavailable 0xFFF0_0800 0x0040 0x8040 Decrementer 0xFFF0_0900 0x0048 0x8048 Reserved 0xFFF0_0A00 0x0050 0x8050 Reserved 0xFFF0_0B00 0x0058 0x8058 System Call 0xFFF0_0C00 0x0060 0x8060 Trace 0xFFF0_0D00 0x0068 0x8068 Floating Point Assist 0xFFF0_0E00 0x0070 0x8070 Implementation Dependant Software Emu...

Page 195: ...nch to branch to branch to branch to branch to branch to branch to branch to branch to branch to branch to branch to branch to branch to Main code can start here F8 0 branch to branch to branch to branch to branch to branch to branch to branch to branch to branch to branch to branch to branch to branch to branch to branch to Freescale Semiconductor I Freescale Semiconductor Inc For More Informatio...

Page 196: ... fault region Each of the four MI_RAx registers contains access permission attributes The MI_GRA global region attribute register contains two additional bits to enable each of the MI_RBAx registers The BBC holds only one register the BBC module configuration register BBCMCR Table 4 2 Region Base Address Registers RBA 0 1 Register Name Address Decimal ub_addr 18 27 hex MI_RBA 0 784 0x2180 MI_RBA 1...

Page 197: ...ble 4 5 MI_RBA 0 3 Bit Descriptions Bit s Name Description 0 19 RA Region address This field defines the base address most significant 20 bits for the region 20 31 Reserved MI_RA 0 3 Region Attribute Register SPR 816 819 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RS HRESET U U U U U U U U U U U U U U U U 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LSB 31 RS PP RESERVED G CMPR1 NOTES 1 Available on...

Page 198: ... 1 Gbyte 0111_1111_1111_1111_1111 2 Gbytes 1111_1111_1111_1111_1111 4 Gbytes 20 31 PP1 NOTES 1 G and PP attributes perform similar protection activities on a region The more protective attribute will be implied on the region if the attributes programming oppose each other Protection bits 00 Supervisor No Access User No Access 01 Supervisor Fetch User No Access 1x Supervisor Fetch User Fetch 22 24 ...

Page 199: ...3 ENR3 Enable region 3 of IMPU 0 Region 3 is off 1 Region 3 is on 4 19 Reserved 20 21 PP Protection bits 00 No supervisor access no user access 01 Supervisor fetch access no user access 10 Supervisor fetch access user fetch access 11 Supervisor fetch access user fetch access 22 24 Reserved 25 G Guarded attribute for region 0 Fetch is allowed from guarded region 1 Fetch is prohibited from guarded r...

Page 200: ...0 All exceptions except reset are mapped to the internal memory base address 1 All exceptions except reset are mapped to the internal memory base address 32 Kbytes 21 EN_COMP Enable COMPression This bit enables the operation of the MPC556 in Compression ON mode The default state is disabled This bit is read only 0 Decompression ON mode is disabled The MPC556 operates only in Decompression OFF mode...

Page 201: ...value is determined by configuration word bit 21 For further de tails regarding show cycles execution in Decompression ON mode see 4 3 9 Decompression 0 Decompression Show Cycle does not include the bit pointer 1 Decompression Show Cycles includes the bit pointer information on the data bus 24 31 Reserved Table 4 8 BBCMCR Bit Descriptions Continued Bit s Name Description Freescale Semiconductor I ...

Page 202: ...MPC555 MPC556 BURST BUFFER MOTOROLA USER S MANUAL Rev 15 October 2000 4 26 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 203: ...set sources and takes appro priate actions depending on the source The reset status register RSR reflects the most recent source to cause a reset Refer to SECTION 7 RESET for details The clock synthesizer generates the clock signals used by the SIU as well as the other modules and external devices This circuitry can generate the system clock from a 4 MHz or 20 MHz crystal The SIU supports various ...

Page 204: ...de The address shown for each register is relative to the base ad dress of the MPC555 MPC556 internal memory map The internal memory block can reside in one of eight possible 4 Mbyte memory spaces See Figure 1 3 in SECTION 1 OVERVIEW for details E bus I F U bus Address Data I F SGPIO Memory Control Lines Interface Memory Controller E Bus U Bus Slave Clocks RESET SW watch Dog Bus monitor Periodic i...

Page 205: ...O Data Register SGPIODT1 See Table 6 21 for bit descriptions 0x2F C028 USIU General Purpose I O Data Register 2 SGPIODT2 See Table 6 22 for bit descriptions 0x2F C02C USIU General Purpose I O Control Register SGPIOCR See Table 6 23 for bit descriptions 0x2F C030 External Master Mode Control Register EMCR See Table 6 12 for bit descriptions 0x2F C03C1 Pads Module Configuration Register PDMCR See Ta...

Page 206: ...ions 0x2F C224 Real Time Clock RTC See 6 13 4 6 Real Time Clock Register RTC for bit descriptions 0x2F C228 Real Time Alarm Seconds RTSEC Reserved 0x2F C22C Real Time Alarm RTCAL See 6 13 4 7 Real Time Clock Alarm Register RTCAL for bit de scriptions 0x2F C230 0x2F C23C Reserved 0x2F C240 PIT Status and Control PISCR See Table 6 18 for bit descriptions 0x2F C244 PIT Count PITC See Table 6 19 for b...

Page 207: ...0 0x2F C31C Reserved 0x2F C320 Real Time Clock Status and Control Key RTCSCK See Table 8 8 for bit descriptions 0x2F C324 Real Time Clock Key RTCK See Table 8 8 for bit descriptions 0x2F C328 Real Time Alarm Seconds Key RTSECK See Table 8 8 for bit descriptions 0x2F C32C Real Time Alarm Key RTCALK See Table 8 8 for bit descriptions 0x2F C330 0x2F C33C Reserved 0x2F C340 PIT Status and Control Key ...

Page 208: ...ose Registers Internal Address 0 31 Register Decimal Address spr 5 9 spr 0 4 1 NOTES 1 Bits 0 17 and 28 31 are all 0 0x2C00 Decrementer DEC 22 0x1880 Time Base Read TB 268 0x1A80 Time Base Upper Read TBU 269 0x3880 Time Base Write TB 284 0x3A80 Time Base Upper Write TBU 285 0x3B30 Internal Memory Mapping Register IMMR 638 Table 5 3 PowerPC Address Range 0 17 18 27 28 31 0 0 spr 0 9 0000 Freescale ...

Page 209: ... to external transfers A transfer error acknowledge TEA is asserted if the TA re sponse limit is exceeded This function can be disabled Software Watchdog Timer SWT The SWT asserts a reset or non maskable interrupt as selected by the system protection control register if the software fails to service the SWT for a designated period of time e g because the software is trapped in a loop or lost After...

Page 210: ...askable interrupt is generated when the counter reach es the value programmed in the alarm register The RTC is clocked by the same clock as the PIT Freeze Support The SIU allows control of whether the SWT PIT TB DEC and RTC should continue to run during the freeze mode Figure 6 1 shows a block diagram of the system configuration and protection logic Figure 6 1 System Configuration and Protection L...

Page 211: ... loca tions The internal memory map is organized as a single 4 Mbyte block The user can assign this block to one of eight locations by programming the ISB field in the internal memory Table 6 1 USIU Pins Multiplexing Control Pin Name Multiplexing Controlled By IRQ0 SGPIOC0 IRQ1 RSV SGPIOC1 IRQ2 CR SGPIOC2 MTS IRQ3 KR RETRY SGPIOC3 IRQ4 AT2 SGPIOC4 IRQ5 SGPIOC5 MODCK1 IRQ6 MODCK2 IRQ7 MODCK3 At Pow...

Page 212: ...ly or externally If EARB is cleared internal arbitration the external arbitration request priority EARP bit deter mines the priority of an external master s arbitration request The operation of the in ternal arbiter is described in 9 5 6 4 Internal Bus Arbiter 0x0000 0000 0x003F FFFF 0x0040 0000 0X007F FFFF 0X0080 0000 0x00BF FFFF 0x00C0 0000 0x00FF FFFF 0x0100 0000 0x013F FFFF 0x0140 0000 0x017F ...

Page 213: ...ternal memories See SECTION 10 MEMORY CON TROLLER for details 6 2 1 Operation of External Master Modes The external master modes are controlled by the EMCR register which contains the internal bus attributes The default attributes in the EMCR enable the external master to configure EMCR with the required attributes and then access the internal registers The external master must be granted external...

Page 214: ...nt address bits ADDR 0 7 The address compare sequence can be summarized as follows Normal external access If the CONT bit in EMCR is cleared the address is com pared to the internal address map MPC555 MPC556 special register external access If the CONT bit in EMCR is set by the previous external master access the address is compared to the MPC555 MPC556 special address range See 5 4 USIU PowerPC M...

Page 215: ... Registers Figure 6 3 illustrates the functionality of the SGPIO Table 6 2 SGPIO Configuration SGPIO Group Name Individual Pin Control Direction Control Available When SC 00 32 bit Port Size Mode Available When SC 01 16 bit Port Size Mode Available When SC 10 Single Chip Mode with Trace Available When SC 11 Single Chip Mode SGPIOD 0 7 GDDR0 X X SGPIOD 8 15 GDDR1 X X SGPIOD 16 23 GDDR2 X X X SGPIOD...

Page 216: ...s from internal sources such as the PIT and RTC from the IMB3 module which has its own interrupt controller and from external pins IRQ 0 7 An overview of the MPC555 MPC556 interrupt structure is shown in Figure 6 4 Read OE Internal Write Clk Bus SGPIO Pad Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 217: ...ns IRQ 1 7 has its own dedicated assigned priority level IRQ 0 is also mapped but should be used only as a status bit indicating that IRQ 0 was asserted and generated an NMI interrupt There are eight additional interrupt pri Level 2 Level 7 Level 6 Level 5 Level 4 Level 3 Level 1 Level 0 NMI IREQ NMI Generate RCPU SIU TB PIT RTC Change of Lock SWT IRQ0 Interrupt Controller DEC DEC Debug Debug IRQO...

Page 218: ...errupt source can be configured to any IMB3 interrupt level The 32 bit UIPEND register in the UIMB holds the pending IMB3 interrupt requests IMB3 interrupt request levels zero to six are mapped to USIU interrupt levels zero to six respectively IMB3 interrupt request levels seven to 31 are mapped to USIU request level seven The user must read the UIPEND register to determine the actual source of th...

Page 219: ...Q pins IRQ 0 should be masked since it generates a NMI and eight interrupt levels The priority between all interrupt sources is shown in Table 6 3 SIPEND SIMASK Interrupt Request S I V E C Priority Interrupt Detector 8 IRQ 0 Interrupt Vector NMI to RCPU to RCPU and Pads Interrupt Level 0 7 IRQ 0 7 latch 1 from 16 Highest Enables Branch to the Highest Priority Interrupt Routine Freescale Semiconduc...

Page 220: ...e bus monitor The bus monitor is always enabled however when freeze is asserted or when a de bug mode request is pending regardless of the state of this bit 6 6 MPC555 MPC556 Decrementer The decrementer DEC is a 32 bit decrementing counter defined by the MPC555 MPC556 architecture to provide a decrementer interrupt This binary counter is clocked by the same frequency as the time base also defined ...

Page 221: ...quest to be pending in the RCPU When the decrementer exception is taken the decrementer interrupt request is automatically cleared Table 6 4 illustrates some of the periods available for the decrementer assuming a 4 MHz or 20 MHz crystal and TBS 0 which selects tbclk division to FOUR NOTE Time base must be enabled to use the decrementer See 6 13 4 4 Time Base Control and Status Register for more i...

Page 222: ...ed when the TB count reaches to the value programmed in one of the two reference registers Two status bits in the time base control and sta tus register TBSCR indicate which one of the two reference registers generated the interrupt Refer to 6 13 4 System Timer Registers for diagrams and bit descriptions of time base registers Refer to 3 9 4 Time Base Facility TB OEA and to RCPU Refer ence Manual ...

Page 223: ...arts over again When a new value is loaded into the PITC the periodic timer is updated the divider is reset and the counter begins counting If the PS bit is not cleared an interrupt request is generated The request remains pending until PS is cleared If the PS bit is set again prior to being cleared the interrupt remains pending until PS is cleared Any write to the PITC stops the current countdown...

Page 224: ...eriodic basis If this periodic servicing action does not occur the SWT times out and issues a reset or a non maskable interrupt NMI depending on the value of the SWRI bit in the SYPCR The SWT can be disabled by clearing the SWE bit in the SYPCR Once the SYPCR is written by software the state of the SWE bit cannot be changed The SWT service sequence consists of the following two steps 1 Write 0x556...

Page 225: ...k An additional divide by 2048 prescaler is used if necessary The decrementer begins counting when loaded with a value from the software watchdog timing count field SWTC After the timer reaches 0x0 a software watchdog expiration request is issued to the reset or NMI control logic Upon reset the value in the SWTC is set to the maximum value and is again loaded into the software watchdog register SW...

Page 226: ...power mode doze sleep or deep sleep the soft ware watchdog timer is frozen It remains frozen and maintain its count value until the processor exits this state and resumes executing instructions The periodic interrupt timer decrementer and time base are not affected by these low power modes They continue to run at their respective frequencies These timers are capable of generating an interrupt to b...

Page 227: ...nternal data bus lines WARNING Software must not change any SIUMCR fields controlled by the reset configuration word while the functions that these fields control are ac tive SIUMCR SIU Module Configuration Register 0x2F C000 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 EARB EARP RESERVED DSHW DBGC DBPC ATWC GPC DLK RESET ID0 0 0 0 0 0 0 0 0 ID 9 10 ID11 ID12 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27...

Page 228: ...oses 0 WE 0 3 BE 0 3 AT 0 3 functions as WE 0 3 BE 0 3 1 1 WE 0 3 BE 0 3 AT 0 3 functions as AT 0 3 NOTES 1 WE BE is selected per memory region by WEBS in the approprite BR register in the memory controller 13 14 GPC This bit configures the pins as shown in Table 6 8 15 DLK Debug register lock 0 Normal operation 1 SIUMCR is locked and can be written only in test mode or when the internal freeze si...

Page 229: ...ns Configuration GPC Pin Function FRZ PTR SGPIOC6 IRQOUT LWP0 SGPIOC7 00 PTR LWP0 01 SGPIOC6 SGPIOC7 10 FRZ LWP0 11 FRZ IRQOUT Table 6 9 Single Chip Select Field Pin Configuration SC Pin Function DATA 0 15 SGPIOD 0 15 DATA 16 31 SGPIOD 16 31 ADDR 8 31 SGPIOA 8 31 00 multiple chip 32 bit port size DATA 0 15 DATA 16 31 ADDR 8 31 01 multiple chip 16 bit port size DATA 0 15 SPGIOD 16 31 ADDR 8 31 10 s...

Page 230: ...t Configuration Word Table 6 10 Multi Level Reservation Control Pin Configuration MLRC Pin Function IRQ 0 SGPIOC 0 IRQ 1 RSV SGPIOC 1 IRQ 2 CR SGPIOC 2 MTS IRQ 3 KR RETRY SGPIOC 3 IRQ 4 AT 2 SGPIOC 4 IRQ 5 SGPI OC 5 MODCK 1 1 NOTES 1 Operates as MODCK 1 during reset 00 IRQ 0 IRQ 1 IRQ 2 2 2 This holds if MTSC bit is reset to 0 Otherwise IRQ 2 CR SGPIOC 2 MTS will function as MTS IRQ 3 IRQ 4 IRQ 5 ...

Page 231: ...ved 20 FLEN Flash enable is a read write bit The default state of FLEN is negated meaning that the boot is performed from external memory This bit can be set at reset by the reset configuration word 0 On chip flash memory is disabled and all internal cycles to the allocated flash address space are mapped to external memory 1 On chip flash memory is enabled 21 22 Reserved 23 CLES Core little endian...

Page 232: ...ribute If SIZEN 1 the SIZE bits controls the internal bus attributes as follows 00 Double word 8 bytes 01 Word 4 bytes 10 Half word 2 bytes 11 Byte 21 SUPU Supervisor user attribute SUPU controls the supervisor user attribute as follows 0 Supervisor mode access permitted to all registers 1 User access permitted to registers designated user access 22 INST Instruction attribute INST controls the int...

Page 233: ... interrupt and if the corre sponding bit is set it indicates that a falling edge was detected on the line and the bit can be reset by software by writing a 1 to it 6 13 2 2 SIU Interrupt Mask Register SIMASK The SIMASK is a 32 bit read write register Each bit corresponds to an interrupt re quest bit in the SIPEND register Setting a bit in this register allows the interrupt re quest to reach the RC...

Page 234: ...senting the unmasked interrupt source of the highest priority level The SIVEC can be read as ei ther a byte half word or word When read as a byte a branch table can be used in which each entry contains one instruction branch When read as a half word each entry can contain a full routine of up to 256 instructions The interrupt code is defined such that its two least significant bits are 0 thus allo...

Page 235: ... 28 29 30 LSB 31 BMT BME RESERVED SWF SWE SWRI SWP RESET 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 Table 6 13 SYPCR Bit Descriptions Bit s Name Description 0 15 SWTC Software watchdog timer count This field contains the count value of the software watchdog tim er 16 23 BMT Bus monitor timing This field specifies the time out period in eight system clock resolution of the bus monitor 24 BME Bus monitor enabl...

Page 236: ...at any time but returns all zeros when read 30 SWRI Software watchdog reset interrupt select 0 Software watchdog time out causes a non maskable interrupt to the RCPU 1 Software watchdog time out causes a system reset 31 SWP Software watchdog prescale 0 Software watchdog timer is not pre scaled 1 Software watchdog timer is prescaled by 2048 Table 6 13 SYPCR Bit Descriptions Continued Bit s Name Des...

Page 237: ...s and the other with data trans fers SWSR Software Service Register 0x2F C00E MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 SWSR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6 14 SWSR Bit Descriptions Bit s Name Description 0 15 SWSR SWT servicing sequence is written to this register To prevent SWT time out the user should write a 0x556C followed by 0xAA39 to this register The SWSR can be written a...

Page 238: ...ter DEC for more information on this register 6 13 4 2 Time Base SPRs The TB is a 64 bit register containing a 64 bit integer that is incremented periodically There is no automatic initialization of the TB the system software must perform this Table 6 15 TESR Bit Descriptions Bit s Name Description 0 17 Reserved 18 IEXT Instruction external transfer error acknowledge This bit is set if the cycle w...

Page 239: ...egister a maskable interrupt is generated 6 13 4 4 Time Base Control and Status Register The TBSCR is 16 bit read write register It controls the TB decrementer count enable and interrupt generation and is used for reporting the source of the interrupts The reg ister can be read anytime A status bit is cleared by writing a one to it Writing a zero has no effect More than one bit can be cleared at a...

Page 240: ...etermine the interrupt priority level of the time base Re fer to 6 4 Interrupt Controller for interrupt level encodings 8 REFA Reference A TBREF0 interrupt status 0 No match detected 1 TBREF0 value matches value in TBL 9 REFB Reference B TBREF1 interupt status 0 No match detected 1 TBREF1 value matches value in TBL 10 11 Reserved 12 REFAE Reference A TBREF0 interrupt enable If this bit is set the ...

Page 241: ...C Bit Descriptions Bit s Name Description 0 7 RTCIRQ Real time clock interrupt request Thee bits determine the interrupt priority level of the RTC Re fer to 6 4 Interrupt Controller for interrupt level encodings 8 SEC Once per second interrupt This status bit is set every second It should be cleared by the soft ware 9 ALR Alarm interrupt This status bit is set when the value of the RTC equals the ...

Page 242: ...pt request These bits determine the interrupt priority level of the PIT Refer to 6 4 Interrupt Controller for interrupt level encodings 8 PS Periodic interrupt status This bit is set if the PIT issues an interrupt The PIT issues an interrupt after the modulus counter counts to zero PS can be negated by writing a one to it A write of zero has no affect 9 12 Reserved 13 PIE Periodic interrupt enable...

Page 243: ...modulus counter that is loaded into the periodic timer This register is readable and writeable at any time 16 31 Reserved PITR Periodic Interrupt Timer Register 0x2F C248 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PIT RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LSB 31 RESERVED RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 6 20 PIT Bit Descriptions Bit s Name Des...

Page 244: ...pins SGPIOD 8 15 The direction input or output of this group of pins is con trolled by the GDDR1 bit in the SGPIO control register 16 23 SGPI OD 16 23 SIU general purpose I O Group D 16 23 This 8 bit register controls the data of the gen eral purpose I O pins SGPIOD 16 23 The direction input or output of this group of pins is controlled by the GDDR2 bit in the SGPIO control register 24 31 SGPI OD ...

Page 245: ...PIOA 24 31 SIU general purpose I O Group A 24 31 This 8 bit register controls the data of the gener al purpose I O pins SGPIOA 24 31 The GDDR5 bit in the SGPIO control register config ures these pins as a group as general purpose input or output SGPIOCR SGPIO Control Register 0x2F C02C MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SDDRC 0 7 RESERVED RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20...

Page 246: ... 38 Table 6 24 describes the bit values for data direction control Table 6 24 Data Direction Control SDDR GDDR Operation 0 SGPIO configured as input 1 SGPIO configured as output Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 247: ...nfiguration The reset status register RSR reflects the most recent source to cause a reset 7 1 1 Power On Reset The power on reset pin PORESET is an active low input In a system with power down low power mode this pin should be activated only as a result of a voltage failure in the KAPWR pin After detecting the assertion of PORESET the MPC555 MPC556 enters the power on reset state During this stat...

Page 248: ...onfiguration is sampled from data pins refer to 7 5 1 Hard Reset Configuration and the chip stops driving the HRESET and SRESET pins An external pull up resistor should drive the HRESET and SRESET pins high After detecting the negation of HRESET or SRESET the MCU waits 16 clock cycles before testing the presence of an external hard or soft reset The HRESET pin has a glitch detector to ensure that ...

Page 249: ...the checkstop reset is enabled the CSR bit in the PLPRCR is set a checkstop reset is asserted The enabled checkstop event generates an internal hard reset sequence Refer to the RCPU Reference Man ual RCPURM AD for more information 7 1 8 Debug Port Hard Reset When the development port receives a hard reset request from the development tool an internal hard reset sequence is generated see SECTION 8 ...

Page 250: ... while asserting external reset EXT_RESET if the data coherency mechanism is required and thus enables a cycle to complete while external hardware drives the data for the configuration word See Table 7 2 for a description of the required EXT_RESET line source in a system Table 7 1 Reset Action Taken For Each Reset Cause Reset Source Reset Logic and PLL States Reset System Configura tion Reset Cloc...

Page 251: ...escriptions Bit s Name Description 0 EHRS1 External hard reset status 0 No external hard reset has occurred 1 An external hard reset has occurred 1 ESRS1 External soft reset status 0 No external soft reset has occurred 1 An external soft reset has occurred 2 LLRS Loss of lock reset status 0 No enabled loss of lock reset has occurred 1 An enabled loss of lock reset has occurred 3 SWRS Software watc...

Page 252: ... 11 locked by the MFPDL bit DIVF 0 4 locked by the MFPDL bit 10 GPOR Glitch detected on PORESET pin This bit is set when the PORESET pin is asserted for more than TBD ns 0 No glitch was detected on the PORESET pin 1 A glitch was detected on the PORESET pin 11 GHRST Glitch detected on HRESET pin This bit is set when the HRESET pin is asserted for more than TBD ns 0 No glitch was detected on the HRE...

Page 253: ...ip assumes the default reset configuration This assumed configuration changes if the input signal RSTCONF is as serted when the PORESET is negated or the CLKOUT starts to oscillate To ensure Table 7 4 Reset Configuration Options RSTCONF Has Configuration HC Internal Configuration Word 0 x DATA 0 31 pins 1 0 NVM flash EEPROM register CMFCFIG 1 1 Internal data word default 0x0000 0000 Dx Data line M...

Page 254: ...ck cycles In systems where an external reset configuration word and the TEXP output function are both required RSTCONF should be asserted until SRESET is negated Figure 7 2 to Figure 7 5 provide sample reset configuration timings Figure 7 2 Reset Configuration Sampling Scheme For Short PORESET Assertion Limp Mode Disabled CLKOUT PORESET HRESET RSTCONF Internal PORESET Default RSTCONF Controlled Ts...

Page 255: ... Configuration Timing for CLKOUT PORESET HRESET RSTCONF Internal PORESET Default RSTCONF Controlled Tsup Internal DATA 0 31 Backup Clock SRESET CLKOUT PORESET HRESET RSTCONF Internal PORESET Default RSTCONF Controlled Tsup Internal DATA 0 31 PLL lock Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 256: ... RESET MOTOROLA USER S MANUAL Rev 15 October 2000 7 10 Long PORESET Assertion Limp Mode Disabled Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 257: ... 5 6 7 8 9 10 11 12 13 14 15 16 Maximum time of reset recognition RESET CONFIGURATION WORD Tsup Minimum Setup time of reset recognition 15 clocks Sample Data Configuration Sample Data Configuration maximum rise time up to 6 clocks Internal reset Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 258: ...med 1 IP Initial interrupt prefix This bit defines the initial value of the MSR IP bit immediately after re set MSR IP defines the interrupt table location 0 MSR IP 0 after reset 1 MSR IP 1 after reset 2 BDRV Bus pins drive strength This bit determines the driving capability of the bus pins address data and control and the CLKOUT pin For details refer to description of the COM bits in 8 12 1 Syste...

Page 259: ... disabled The default state is disabled Refer to SECTION 4 BURST BUFFER for details 20 FLEN Flash Enable This field determines whether the on chip flash memory is enabled or dis abled out of reset The default state is disabled which means that by default the boot is from external memory 0 Flash disabled boot is from external memory 1 Flash enabled 21 EN_ COMP1 Enable Compression This bit enables t...

Page 260: ...MPC555 MPC556 RESET MOTOROLA USER S MANUAL Rev 15 October 2000 7 14 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 261: ...oscillator TB DEC RTC and the PIT are powered from the keep alive power supply KAPWR pin This allows the counters to continue to count increment decre ment at the oscillator frequency even when the main power to the MCU is off While the power is off the PIT may be used to signal to the power supply IC to enable power to the system at specific intervals This is the power down wake up feature When t...

Page 262: ...MBclk TMBCLK Lock VDDSYN Drivers Driver Main Clock XTAL EXTAL 3 1 MUX RTC PIT Clock and DRIVER Oscillator MUX TBCLK 4 or 16 MODCK 1 3 PITRTCLK EXTCLK 2 1 MUX Low Power Dividers 1 2N 4 or 256 GCLK2 Back_Up Clock Detector Oscillator Loss ENGCLK VSSSYN Drivers SYSTEM CLOCK SYSTEM CLOCK TO RCPU AND BBC Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www...

Page 263: ...to continue minimum functionality until the system is fixed The BUCLK frequency is approximately 7 MHz see APPENDIX G ELECTRICAL CHAR ACTERISTICS for the complete frequency range For normal operation at least one clock source EXTCLK or OSCM must be active A configuration with both clock sources active is possible as well At this configuration EXTCLK provides the OSCCLK and OSCM provides the PITRTC...

Page 264: ...own in Figure 8 3 the reference signal OSCCLK goes to the phase compara tor The phase comparator controls the direction up or down that the charge pump drives the voltage across the external filter capacitor XFC The direction depends on whether the feedback signal phase lags or leads the reference signal The output of the charge pump drives the VCO The output frequency of the VCO is divided down a...

Page 265: ...eration VDDSYN Drain voltage This is the VDD dedicated to the analog PLL circuits The voltage should be well regulated and the pin should be provided with an ex tremely low impedance path to the VDD power rail VDDSYN should be bypassed to VSSSYN by a 0 1 µF capacitor located as close as possible to the chip pack age VSSSYN Source voltage This is the VSS dedicated to the analog PLL circuits The pin...

Page 266: ... both set the system clock switches to the backup clock and the chip operates in limp mode until STBUC is cleared Every change in the lock status of the PLL can generate a maskable interrupt NOTE When the VCO is the system clock source chip operation is unpre dictable while the PLL is unlocked Note further that a switch to the backup clock is possible only if the LME bit in the SCCR is set 8 5 Low...

Page 267: ...ing as the system clock the backup clock is automatically selected as the time base clock source and is twice the MPC555 MPC556 system clock Figure 8 4 MPC555 MPC556 Clocks Note that GCLK1_50 GCLK2_50 and CLKOUT can have a lower frequency than GCLK1 and GCLK2 This is to enable the external bus operation at lower frequencies controlled by EBDF in the SCCR GCLK2_50 always rises simultaneously with G...

Page 268: ...ake up stage When MODCK1 is cleared the output of the main oscillator OSCM is selected as the input to the SPLL When MODCK1 is asserted the external clock input EXTCLK is selected as the input to the SPLL In all cases the system clock frequency freqgclk2 can be reduced by the DFNH 0 2 bits in the SCCR Note that freqgclk2 max occurs when the DFNH bits are cleared The TBS bit in the SCCR selects the...

Page 269: ... 1 Reset Clocks Source Configuration MODCK 1 3 1 NOTES 1 For other implementations in the MPC500 family MODCK2 could be inverted LME Default Values PORESET SPLL Options MF 1 PITCLK Division TMBCLK Division 000 0 513 4 4 Used for testing purposes 001 0 1 256 16 Normal operation PLL enabled Main timing reference is freq OSCM 20 MHz Limp mode disabled 010 1 5 256 4 Normal operation PLL enabled Main t...

Page 270: ...ncy operation provides but must consume less power than in maximum frequency operation The MPC555 MPC556 provides a method to automatically switch between low and high frequency operation whenever one of the following conditions exists There is a pending interrupt from the interrupt controller This option is maskable by the PRQEN bit in the SCCR The POW bit in the MSR is clear in normal operation ...

Page 271: ...quency is Figure 8 7 shows the timing of USIU clocks when DFNH 1 or DFNL 0 GCLK1 Divide by 1 GCLK2 Divide by 1 GCLK1 Divide by 2 GCLK2 Divide by 2 GCLK1 Divide by 4 GCLK2 Divide by 4 FREQsys FREQsysmax 2 DFNH or 2 DFNL 1 where FREQsysmax System Frequency FREQSYS 2 System Frequency FREQSYS OSCCLK DIVF 1 x MF 1 2DFNH or 2DFNL 1 2 2 x FREQ50 FREQsysmax 2 DFNH or 2 DFNL 1 1 EBDF 1 Freescale Semiconduc...

Page 272: ...n the PLL is acquiring lock the CLKOUT signal is disabled and remains in the low state provided that BUCS 0 8 6 3 Engineering Clock ENGCLK is an output clock with a 50 duty cycle Its frequency defaults to VCO 1281 which is one sixtyfourth of the main system frequency ENGCLK frequency can be pro grammed to the main system frequency divided by a factor from one to 64 as con trolled by the ENGDIV 0 5...

Page 273: ...SCCR Switching from limp mode to normal system operation is accomplished by clearing STBUC and LOCSS bits This operation also asserts hard reset to the chip At HRESET assertion if the PLL output clock is not valid the BUCLK will be selected until software clears LOCSS bit in SCCR At HRESET assertion if the PLL output clock is valid the system will switch to oscillator external clock If during HRES...

Page 274: ...t locked the loss of clock sticky bit LOCSS is asserted and the chip should operate with BU CLK hreset_b 1 b u c l k _ e n a b l e 1 a s s e r t h r e s e t _ b buclk enable 1 hreset_b 0 LME 1 poreset_b 0 1 BUCLK 2 BUCLK 5 osc poreset_b 1 LME 1 3 BUCLK 4 osc 6 BULCK poreset_b 0 hresert_b 0 hreset_b 1 b u c l k _ e n a b l e 1 h r e s e t _ b 1 buclk_enable 0 hreset_b 1 else hreset_b 0 LOCS LME 0 b...

Page 275: ...ode exit signal arrives There are four low power modes Doze mode Sleep mode Deep sleep mode Power down mode 8 8 1 Entering a Low Power Mode Low power modes are enabled by setting the POW bit in the MSR and clearing the LPML low power mode lock bit in the PLPRCR Once enabled a low power mode is entered by setting the LPM bits to the appropriate value This can be done only in one of the normal modes...

Page 276: ...tem response to asynchronous interrupts is fast The wake up time from nor mal low doze high doze low and sleep mode due to an asynchronous interrupt or Table 8 4 Power Mode Control Bit Descriptions Power Mode LPM 0 1 CSRC TEXPS Normal high 00 0 X Normal low gear 00 1 X Doze high 01 0 X Doze low 01 1 X Sleep 10 X X Deep sleep 11 X 1 Power down 11 X 0 Table 8 5 Power Mode Descriptions Operation Mode...

Page 277: ...mode if either of the following conditions is met An interrupt is pending from the interrupt controller or The MSR POW bit is cleared power management is disabled When neither of these conditions are met the PLPRCR CSRC bit is set and the asyn chronous interrupt status bits are reset the system returns to normal low mode 8 8 3 2 Exiting from Doze Mode The system changes from doze mode to normal hi...

Page 278: ...ugh hard reset External logic should assert HRESET in response to the TEXPS bit being set and TEXP pin being asserted The TEXPS bit is set by an enabled RTC PIT time base or decrementer interrupt The hard reset should be asserted for no longer than the time it takes for the power supply to wake up in addition to the PLL lock time When the TEXPS bit is cleared and the TEXP signal is negated asserti...

Page 279: ...Wake up or Interrupt Wake up Frequency Clocks Wake up 3 4 SysFreq Clocks 500 Input Software is active only in normal high low modes Software RTC PIT TB DEC Interrupt followed Hard Reset Asynchronous Wake up 3 4 SysFreqmax Interrupts Clocks TEXPS 1 TEXPS 0 TEXPS receives the zero value by writing one Writing of zero has no effect on TEXPS by External Hard Reset Software The switch from normal high ...

Page 280: ...ormal operation VDDSRAM 1 4 V during standby operation VPP VDDL 0 3 V but VPP VDDL 4 0 volts 8 9 2 Chip Power Structure The MPC555 MPC556 provides a wide range of possibilities for power supply con nections Figure 8 10 illustrates the different power supply sources for each of the ba sic units on the chip 8 9 2 1 VDDL The I O buffers and logic are fed by a 3 3 V power supply 8 9 2 2 VDDI VDDI powe...

Page 281: ...rs driving these inputs should be pow ered by KAPWR 8 9 2 5 VDDA VSSA VDDA supplies power to the analog subsystems of the QADC_A and QADC_B mod ules it is nominally 5 0 V VDDA is the ground reference for the analog subsystems 8 9 2 6 VPP VPP supplies the programming and erase voltage for the CMF flash modules It is nominally 5 0 V for program or erase operations and can be lowered to a nominal 3 3...

Page 282: ...an example of a switching scheme for an optimized low power system SW1 and SW2 can be unified in only one switch if VDDSYN and VDDI VDDL are supplied by the same source Clock Control PLL PIT RTC TB and DEC Internal Logic VDDL I O VDDI VDDSYN KAPWR TEXP Oscillator VDDSRAM VDDI VDDH VPP VDDF FLASH SRAM Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to w...

Page 283: ...nd time base registers are pow ered by the KAPWR supply When the main power supply is disconnected after power down mode is entered the value stored in any of these registers is preserved If pow er down mode is not entered before power disconnect there is a chance of data loss in these registers To minimize the possibility of data loss the MPC555 MPC556 in cludes a key mechanism that ensures data ...

Page 284: ...se Reference 1 TBREF1 See 6 13 4 3 Time Base Reference Reg isters for bit descriptions 0x2F C308 Time Base Reference 1 Key TBREF1K 0x2F C220 Real Time Clock Status and Control RTCSC See Table 6 17 for bit descriptions 0x2F C320 Real Time Clock Status and Control Key RTCSCK 0x2F C224 Real Time Clock RTC See 6 13 4 6 Real Time Clock Register RTC for bit descriptions 0x2F C324 Real Time Clock Key RTC...

Page 285: ...hat for each of the conditions detailing the voltage re lationships the absolute bounds of the minimum and maximum voltage supply cannot be violated i e the value of VDDL cannot fall below 3 0 V or exceed 3 6 V and the value of VDDH cannot fall below 4 5 V or exceed 5 5 V for normal operation Further information detailing the functionality of the VPP signal for flash program and erase is outlined ...

Page 286: ...ip is greater than 0 74 V for the 3 V supply and greater than 0 8 V for the 5 V supply then the circuitry inside the MPC555 MPC556 will act as a load to the respective supply and will dis charge the supply line down to these values Since the 3 V logic represents a larger load to the supply chip the 3 V supply line will decay faster than the 5 V supply line Figure 8 13 No Standby No KAPWR All Syste...

Page 287: ...re negated 2 If keep alive functions are NOT used then when system power is on KAPWR VDDSRAM VDDL 0 35 V 3 If keep alive functions ARE used then KAPWR VDDSRAM VDDL 3 3 V 0 35 V when system power is on VDDSRAM 1 8 V and optionally KAPWR 3 3 V 0 3 V when system power is off Normal system power is defined as VDDL VDDI VDDF VDDSYN VPP VDDSRAM KAPWR 3 3 0 3 V and VDDA VDDH 5 0 0 5 V Power On Power Off ...

Page 288: ...cted from the indicated internal data bus lines Refer to 7 5 2 Hard Reset Configuration Word U Unaffected by reset 2 RTDIV will be 0 if MODCK 1 3 0b000 3 EQ2 MODCK1 4 EQ3 MODCK1 MODCK2 MODCK3 MODCK1 MODCK2 MODCK3 MODCK1 MODCK2 MODCK3 See Table 8 1 5 On mask sets prior to K62N ENGDIV defaults to 0b000001 SCCR System Clock Control Register 0x2F C280 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DBCT COM...

Page 289: ...l the PLL aquires lock 0 Enable clock switching if the PLL loses lock during reset 1 Disable clock switching if the PLL loses lock during reset 4 MFPDL MF and pre divider lock Setting this control bit disables writes to the MF and DIVF bits This helps prevent runaway software from changing the VCO frequency and causing the SPLL to lose lock In addition to protect against hardware interference a ha...

Page 290: ...ss of clock will switch the system clock automatically to backup clock It is also possible to switch to the backup clock by setting the STBUC bit If LME is cleared the option of using limp mode is disabled The loss of clock detector is not active and any write to STBUC is ignored The LME bit is writable once by software after power on reset when the system clock is not backup clock BUCS 0 During p...

Page 291: ...ide by 4 010 Divide by 8 011 Divide by 16 100 Divide by 32 101 Divide by 64 110 Reserved 111 Divide by 256 28 Reserved 29 31 DFNH Division factor high frequency These bits determine the general system clock frequency dur ing normal mode Changing the value of these bits does not result in a loss of lock condition These bits are cleared by power on or hard reset The user can load these bits at any t...

Page 292: ...F field should not be modified when entering or exiting from low power mode LPM change or when back up clock is active The normal reset value for the DFNH bits is zero divide by one When the PLL is operating in one to one mode the multiplication factor is set to x1 MF 0 12 Reserved 13 LOCS Loss of clock status When the oscillator or external clock source is not at the minimum fre quency the loss o...

Page 293: ...he TMIST bit is set even if the CSRC bit in the PLPRCR is set DFNL enabled and conditions to switch to normal low mode do not exist This bit is cleared during power on or hard reset 0 No timer expired event was detected 1 A timer expire event was detected 20 Reserved 21 CSRC Clock source This bit is cleared at hard reset 0 General system clock is determined by the DFNH value 1 General system clock...

Page 294: ...d and written at any time However the DIVF field can be write protected by setting the MF and pre divider lock MFPDL bit in the SCCR Changing the DIVF bits causes the SPLL to lose lock COLIR Change of Lock Interrupt Register 0x2F C28C MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 COLIRQ COLIS Re served COLIE Reserved RESET 0 0 0 0 0 0 0 0 0 0 U U U U U U Table 8 11 COLIR Bit Descriptions Bit s Nam...

Page 295: ...ndicate whether a VDDSRAM supply failure oc curred In addition when the power is turned on for the first time VDDSRAM rises and these bits are set The LVSRS bits are cleared by writing them to ones A write of zero has no effect on these bits 0 No VDDSRAM supply failure was detected 1 VDDSRAM supply failure was detected 5 VSRDE VDDSRAM detector disable 0 VDDSRAM detection circuit is enabled 1 VDDSR...

Page 296: ...PC555 MPC556 CLOCKS AND POWER CONTROL MOTOROLA USER S MANUAL Rev 15 October 2000 8 36 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 297: ...ble and non burstable Supports non wrap bursts Flash ROM programming support Compatible with PowerPC architecture Easy to interface to slave devices Bus is synchronous all signals are referenced to rising edge of bus clock Bus can operate at the same frequency as the MPC555 MPC556 or half the fre quency 9 2 Bus Transfer Signals The bus transfers information between the MPC555 MPC556 and external m...

Page 298: ...p and hold times for deterministic opera tion all input signals must obey the protocols described in this section Figure 9 1 Input Sample Window 9 3 Bus Control Signals The MPC555 MPC556 initiates a bus cycle by driving the address size address type cycle type and read write outputs At the beginning of a bus cycle TSIZ0 and TSIZ1 are driven with the address type signals TSIZ0 and TSIZ1 indicate th...

Page 299: ...d descriptions can be found in subsequent subsections ADDR 0 31 RD WR BURST TSIZ 0 1 AT 0 3 STS BI TS BI STS KR DATA 0 31 TA TEA BDIP BR BG BB CR 32 1 1 2 4 1 1 1 1 1 32 1 1 1 1 1 1 Address and Transfer Attributes Transfer Start Arbitration Data Transfer Termination Reservation Protocol Cycle RSV 1 PTR 1 RETRY 1 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Pro...

Page 300: ...r nal bus Driven low indicates that a burst transfer is in progress Driven high indicates that the current trans fer is not a burst The MPC555 MPC556 does not support burst accesses to internal slaves TSIZ 0 1 Transfer size 2 High O Driven by the MPC555 MPC556 along with the ad dress when it owns the external bus Specifies the data transfer size for the transaction I Driven by an external master w...

Page 301: ...ses to internal slaves Transfer Start TS Transfer start 1 Low O Driven by the MPC555 MPC556 when it owns the external bus Indicates the start of a transaction on the external bus I Driven by an external master when it owns the exter nal bus It indicates the start of a transaction on the external bus or in show cycle mode signals the be ginning of an internal transaction STS Special transfer start ...

Page 302: ... re ceived the data on the write cycle or returned data on the read cycle If the transaction is a burst TA should be asserted for each one of the transaction beats O Driven by the MPC555 MPC556 when the slave de vice is controlled by the on chip memory controller or when an external master initiated a transaction to an internal slave module TEA Transfer error acknowledge 1 Low I Driven by the slav...

Page 303: ...ven by the MPC555 MPC556 when the internal arbiter is disabled and the chip is not parked BG Bus grant 1 Low O When the internal arbiter is enabled the MPC555 MPC556 asserts this signal to indicate that an exter nal master may assume ownership of the bus and be gin a bus transaction The BG signal should be qualified by the master requesting the bus in order to ensure it is the bus owner Qualified ...

Page 304: ...f data 16 x 1 bytes 9 5 2 Single Beat Transfer During the data transfer phase the data is transferred from master to slave in write cycles or from slave to master on read cycles During a write cycle the master drives the data as soon as it can but never earlier than the cycle following the address transfer phase The master has to take into consider ation the one dead clock cycle switching between ...

Page 305: ... bus BR Receive bus grant BG from arbiter Assert bus busy BB if no other master is driving bus Assert transfer start TS Drive address and attributes Receive address Return data Assert transfer acknowledge TA Receive data Slave Master Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 306: ...ycle Basic Timing Zero Wait States CLKOUT ADDR 0 31 TS BR BG BB Data TA RD WR Receive bus grant and bus busy negated Assert BB drive address and assert TS Data is valid BURST BDIP TSIZ 0 1 O O O O O Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 307: ...ress transfer then the data transfer The handshakes are illustrated in the following flow and timing diagrams as applicable to the fixed transaction protocol CLKOUT ADDR 0 31 TS BR BG BB Data TA RD WR Receive bus grant and bus busy negated assert BB drive address and assert TS Data is valid BURST BDIP TSIZ 0 1 Wait state O O O O O Freescale Semiconductor I Freescale Semiconductor Inc For More Info...

Page 308: ...ter Slave Request bus BR Receive bus grant BG from arbiter Assert bus busy BB if no other master is driving bus Assert transfer start TS Drive address and attributes Drive data Assert transfer acknowledge TA Interrupt data driving Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 309: ...ite Cycle Timing Zero Wait States CLKOUT ADDR 0 31 TS BR BG BB Data TA RD WR Receive bus grant and bus busy negated Assert BB drive address and assert TS Data is sampled BURST BDIP TSIZ 0 1 O O O O O Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 310: ...transfer as in the normal case If the bus interface receives a small port size 16 or 8 bits indication before the transfer acknowledge to the first beat through the internal memory controller the MCU initiates successive transactions until the completion of the data transfer Note that all the transactions initiated to complete the data transfer are considered to be part of an atomic transaction so...

Page 311: ...rapping burst transfers to access operands of up to 16 bytes four words A non wrapping burst access stops accessing the external device when the word address is modulo four The MPC555 MPC556 begins the ac cess by supplying a starting address that points to one of the words and requiring the memory device to sequentially drive or sample each word on the data bus The select CLKOUT ADDR 0 1 TS BR BG ...

Page 312: ...these devices when they are controlled by the internal memory controller In this case the MPC555 MPC556 attempts to initiate a burst transfer as in the normal case If the memory controller signals to the bus interface that the external device has a small port size 8 or 16 bits and if the burst is accepted the bus interface completes a burst of 8 or 16 beats Each of the data beats of the burst tran...

Page 313: ...y during cy cles for which the memory controller generates TA internally Refer to SECTION 10 MEMORY CONTROLLER for more information In the MPC555 MPC556 no internal master initiates write bursts The MPC555 MPC556 is designed to perform this kind of transaction in order to support an external master that is using the memory controller services Refer to 10 7 Memory Controller External Master Support...

Page 314: ...URST Asserted Assert BDIP BDIP Asserted Yes Return Data Assert Transfer Acknowledge TA Receive Data BDIP Asserted Yes Return Data Assert Transfer Acknowledge TA Receive Data BDIP Asserted Yes Return Data Assert Transfer Acknowledge TA Receive Sata BDIP Asserted Yes Negate Burst Data in Progress BDIP No Drive Last Data Assert TA No Drive Last Data Assert TA No Drive Last Data Assert TA No Drive Las...

Page 315: ...t Size Zero Wait State CLKOUT ADDR 0 31 TS BR BG BB Data TA RD WR BURST TSIZ 0 1 BDIP Data Data Data Data is Valid is Valid is Valid is Valid Last Beat Expects Another Data 00 ADDR 28 31 0000 O O O O O O O O Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 316: ...Wait State CLKOUT ADDR 0 31 TS BR BG BB Data TA RD WR BURST TSIZ 0 1 BDIP Data Data Data Data is Valid is Valid is Valid is Valid Last Beat Expects Another Data 00 Wait State ADDR 28 31 0000 Normal Late O O O O O O O O Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 317: ... Between Beats CLKOUT ADDR 0 31 TS BR BG BB Data TA RD WR BURST TSIZ 0 1 BDIP Data Data Data Data is Valid is Valid is Valid is Valid Last Beat Expects Another Data 00 Wait State ADDR 28 31 0000 Normal or Late O O O O O O O O Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 318: ...October 2000 9 22 Figure 9 15 Burst Read Cycle 16 Bit Port Size CLKOUT ADDR 0 31 TS BR BG BB Data 0 15 TA RD WR BURST TSIZ 0 1 BDIP 00 ADDR 28 31 0000 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 319: ...erted Assert BDIP BDIP Asserted Yes Sample Data Assert Transfer Acknowledge TA Drive Data BDIP Asserted Yes Sample Data Assert Transfer Acknowledge TA Drive Data BDIP Asserted Yes Sample Data Assert Transfer Acknowledge TA Stop Driving Data BDIP Asserted Yes Negate Burst Data in Progress BDIP No Don t Sample Next Data No Don t Sample Next Data No Don t Sample Next Data No Don t Sample Next Data AD...

Page 320: ...Data Data Data is Sampledis Sampledis Sampledis Sampled Last Beat Will Drive Another Data ADDR 28 29 00 O O O O O O O O from external master from external master from external master from external master from external master CLKOUT master Data TA TS from external master from external 00 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale c...

Page 321: ...LKOUT ADDR 0 27 TS BR BG BB Data TA RD WR BURST TSIZ 0 1 BDIP 00 BI ADDR 28 29 ADDR 30 31 0 1 2 3 BURST and BDIP will be asserted for one cycle if the RCPU core requests a burst but the USIU splits it into a sequence of normal cycles Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 322: ...26 Figure 9 19 Non Wrap Burst with Three Beats CLKOUT ADDR 0 29 TS BR BG BB Data TA RD WR BURST TSIZ 0 1 BDIP 00 BI ADDR 30 31 n n modulo 4 1 Expects Another Data O O Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 323: ...n Wrap Burst with One Data Beat CLKOUT ADDR 0 29 TS BR BG BB Data TA RD WR BURST TSIZ 0 1 BDIP DATA is Sampled First and Last Beat 00 ADDR 30 31 00 n n modulo 4 3 Is Never Asserted O Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 324: ... reside on DATA 0 15 and an 8 bit port must reside on DATA 0 7 The MPC555 MPC556 always tries to transfer the maximum amount of data on all bus cycles For a word operation it always assumes that the port is 32 bits wide when beginning the bus cycle In Figure 9 21 Figure 9 22 Table 9 2 and Table 9 3 the following conventions are used OP0 is the most significant byte of a word operand and OP3 is the...

Page 325: ... the bytes required on the data bus for read cycles 0 31 32 bit Port Size OP0 OP1 OP2 OP3 OP0 OP1 OP2 OP3 OP0 OP1 OP2 OP3 OP0 OP1 OP2 OP3 16 bit Port Size 8 bit Port Size DATA 0 7 DATA 8 15 DATA 16 23 DATA 24 31 Interface Output Register Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 326: ...he device that needs the bus asserts BR The device then waits for the arbiter to assert BG In addition the new master must look at BB to ensure that no other mas ter is driving the bus before it can assert BB to assume ownership of the bus Any time the arbiter has taken the bus grant away from the master and the master wants to ex Table 9 2 Data Bus Requirements For Read Cycles Transfer Size TSIZE...

Page 327: ...ot busy and the new master can drive the bus If more requests are pending the master can keep asserting its bus request as long as needed When configured for external central arbitration the MPC555 MPC556 drives this signal when it requires bus mastership When the internal on chip arbiter is used this signal is an input to the internal arbiter and should be driven by the external bus master Reques...

Page 328: ...es that the current bus master is using the bus New masters should not begin transfer until this signal is negated The bus owner should not relin quish or negate this signal until the transfer is complete To avoid contention on the BB line the master should three state this signal when it gets a logical one value This requires the connection of an external pull up resistor to ensure that a master ...

Page 329: ...rnal device relative to the internal MPC555 MPC556 bus mas ters is programmed in the SIU module configuration register If the external device re quests the bus and the MPC555 MPC556 does not require it or if the external device has higher priority than the current internal bus master the MPC555 MPC556 grants the bus to the external device Table 9 4 describes the priority mechanism used by the inte...

Page 330: ...al access pri ority Type Direction Priority Parked access2 2 Parked access is instruction or data access from the RCPU which is initiated on the internal bus without requesting it first in order to improve performance Internal external 0 Instruction access Internal external 3 Data access Internal external 4 External access external external internal EARP3 could be programmed to 0 7 3 Refer to 6 13...

Page 331: ...ame time as the address bus IDLE BG 1 BB t s External BG 0 External Master B R 0 Ext Master Release Bus BG 1 BB t s BB t s BB 0 BG 1 BB 0 BB 1 B B 1 B R 1 BR 0 Requests Bus BR 1 External Device With Higher Priority than the Current Internal Bus Master Requests the Bus Internal Master With Higher Priority than the External Device Requires the Bus MCU Needs No Longer the Bus Needs the Bus Still Need...

Page 332: ...until the bus master receives the transfer acknowl edge signal from the slave To distinguish the individual byte the slave device must observe the TSIZ signals 9 5 7 3 Read Write A high value on the RD WR line indicates a read access A low value indicates a write access 9 5 7 4 Burst Indicator BURST is driven by the bus master at the beginning of the bus cycle along with the address to indicate th...

Page 333: ...nstruction or data type The address type signals are valid at the rising edge of the clock in which the special transfer start STS signal is asserted A special use of the PTR and RSV signals is for the reservation protocol described in 9 5 9 Storage Reservation Refer to 9 5 13 Show Cycle Transactions for informa tion on show cycles Table 9 7 summarizes the pins used to define the address type Tabl...

Page 334: ... x x 1 1 No transfer 0 01 NOTES 1 Cases in which both TS and STS are asserted indicate normal cycles with the show cycle attribute 0 0 0 0 0 1 RCPU normal instruction program trace supervisor mode 1 1 1 RCPU normal instruction supervisor mode 1 0 1 0 RCPU reservation data supervisor mode 1 1 1 RCPU normal data supervisor mode 1 0 0 0 1 RCPU normal instruction program trace user mode 1 1 1 RCPU nor...

Page 335: ...ls Protocol The transfer protocol was defined to avoid electrical contention on lines that can be driven by various sources To this end a slave must not drive signals associated with the data transfer until the address phase is completed and it recognizes the address as its own The slave must disconnect from signals immediately after it has acknowl edged the cycle and no later than the termination...

Page 336: ...on protocol makes the following assumptions Each processor has at most one reservation flag lwarx sets the reservation flag lwarx by the same processor clears the reservation flag related to a previous lwarx instruction and again sets the reservation flag stwcx by the same processor clears the reservation flag Store by the same processor does not clear the reservation flag Some other processor or ...

Page 337: ...KOUT When this signal is asserted the reservation flag is reset The EBI samples the logical value of the reservation flag prior to externally starting a bus cycle initiated by the RCPU stwcx instruction If the reservation flag is set the EBI begins with the bus cycle If the reservation flag is reset no bus cycle is initiated ex ternally and this situation is reported to the RCPU The reservation pr...

Page 338: ...e If the MPC555 MPC556 begins a memory cycle to the previously reserved address located in the remote bus as a result of an stwcx in struction the following two cases can occur If the reservation flag is set the buses interface acknowledges the cycle in a nor mal way If the reservation flag is reset the bus interface should assert the KR However S R Buses Interface External Bus Interface Q KR Exte...

Page 339: ... next initiated bus cycle TEA is an open drain pin that allows the wired or of any different sources of error generation 9 5 10 1 Retrying a Bus Cycle When an external device asserts the RETRY signal during a bus cycle the MPC555 MPC556 enters a sequence in which it terminates the current transaction relinquishes the ownership of the bus and retries the cycle using the same address address at trib...

Page 340: ...re 9 31 Retry Transfer Timing Internal Arbiter CLKOUT ADDR 0 31 TS BR BG output BB Data TA RD WR BURST TSIZ 0 1 RETRY input ADDR ADDR Allow External Master to Gain the Bus O Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 341: ...knowledged by the slave device When the RETRY signal is asserted as a termina tion signal on any data beat of the access after the first being the first data beat ac knowledged by a normal TA assertion the MPC555 MPC556 recognizes RETRY as a transfer error acknowledge CLKOUT ADDR 0 31 TS BR output BG BB Data TA RD WR BURST TSIZ 0 1 RETRY input ADDR ADDR Allow External Master to Gain the Bus O Free...

Page 342: ...sfer recognizes the RETRY signal assertion as a transfer er ror acknowledge In the case in which a small port size causes the MPC555 MPC556 to break a bus transaction into several small transactions terminating any transaction with RETRY CLKOUT ADDR 0 31 TS BR BG output BB Data TA RD WR BURST TSIZ 0 1 RETRY ADDR ADDR Allow External Master to Gain the Bus BI If Asserted Will Cause Transfer Error O ...

Page 343: ...EA or RETRY If the access completes successfully the MPC555 MPC556 asserts TA and the external master can proceed with another ex ternal master access or relinquish the bus If an address or data error is detected in ternally the MPC555 MPC556 asserts TEA for one clock TEA should be negated before the second rising edge after it is sampled asserted in order to avoid the detec tion of an error for t...

Page 344: ... Arbiter Asserts Bus Busy BB if No Other Master is Driving Assert Transfer Start TS Drives Address and Attributes Receives Address Returns Data Asserts Transfer Acknowledge TA Receives Data Address in Internal Memory Map No Yes Asserts CSx If In Range Memory Controller MPC555 MPC556 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com n...

Page 345: ...C556 Note that the mini External Master Request Bus BR Receives Bus Grant BG From Arbiter Asserts Bus Busy BB if No Other Master is Driving Assert Transfer Start TS Drives Address and Attributes Asserts Transfer Acknowledge TA Address in Internal Memory Map No Yes Asserts CSx If In Range Memory Controller Drives Data Receives Address Receives Data MPC555 MPC556 Freescale Semiconductor I Freescale ...

Page 346: ...e 9 36 Peripheral Mode External Master Reads from MPC555 MPC556 Two Wait States CLKOUT ADDR 0 31 TS input BR input BG BB Data TA output RD WR Receive Bus Grant and Bus Busy Negated Assert BB Drive Address and Assert TS DATA is valid BURST TSIZ 0 1 Minimum 2 Wait States BDIP Use the Internal Arbiter O O O O O Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product...

Page 347: ...ait States CLKOUT ADDR 0 31 TS input BR input BG BB Data TA output RD WR Receive Bus Grant and Bus Busy Negated Assert BB Drive Address and Assert TS DATA is sampled BURST TSIZ 0 1 Minimum 2 Wait States BDIP Use the Internal Arbiter O O O O O Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 348: ...a pending internal to external access to be executed The RETRY signal functions as an output that signals the external master to release the bus ownership and retry the access after one clock Figure 9 38 describes the flow of an external master retried access Figure 9 39 shows the timing when an external access is retried and a pending internal to external access follows Freescale Semiconductor I ...

Page 349: ...Attributes Receives Address Returns Data Asserts Transfer Acknowledge TA Receives Data Address in Internal Memory Map No Yes Asserts CSx If In Range Memory Controller Assert Retry Release Bus Request BR for One Clock and Request Bus BR Again Wait Until Bus Busy Negated No Other Master is Driving Assert Transfer Start TS Drives Address and Attributes Assert Bus Busy BB MPC555 MPC556 Freescale Semic...

Page 350: ... cycle can be a write or a read access The data for both the read and write accesses should be driven by the bus master This is different from normal bus read and write accesses The address and data of the show cycle must each be valid on the bus for one clock The data phase must not require a transfer ac CLKOUT ADDR 0 31 TS BR BG output BB Data TA RD WR BURST TSIZ 0 1 RETRY output ADDR ext ernal ...

Page 351: ...bus transactions have the following characteristics see Figure 9 40 One clock cycle Address phase only STS assertion only no TA assertion I Figure 9 40 Instruction Show Cycle Transaction CLKOUT ADDR 0 31 BR in BG out BB Data three state TA RD WR BURST TSIZ 0 1 ADDR1 ADDR2 STS TS Normal Non Show Cycle Bus Transaction Instruction Show Cycle Bus Transaction Freescale Semiconductor I Freescale Semicon...

Page 352: ...lock cycles Data is valid only in the second clock cycle STS signal only is asserted no TA or TS Figure 9 41 Data Show Cycle Transaction CLKOUT ADDR 0 31 BR in BG out BB Data TA RD WR BURST TSIZ 0 1 ADDR1 ADDR2 STS TS DATA1 DATA2 Read Data Show Cycle Bus Transaction Write Data Show Cycle Bus Transaction Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go t...

Page 353: ...mory regions is initiated the memory controller takes ownership of the external signals and controls the access until its ter mination Refer to Figure 10 1 Figure 10 1 Memory Controller Function Within the USIU 10 1 Overview The memory controller provides a glueless interface to EPROM static RAM SRAM Flash EPROM FEPROM and other peripherals The general purpose chip selects are available on lines C...

Page 354: ...not sent to the MPC555 MPC556 pins Each memory bank includes a variable block size of 32 Kbytes 64 Kbytes and up to 4 Gbytes Each memory bank can be selected for read only or read write operation The access to a memory bank can be restricted to certain address type codes for sys tem protection The address type comparison occurs with a mask option as well INTERNAL ADDRESSES 0 16 AT 0 2 ATTRIBUTES W...

Page 355: ... for the 32 bit SRAM The WE BE 0 3 signals are used both to program the EPROM and to enable write access to various bytes in the RAM Figure 10 3 MPC555 MPC556 Simple System Configuration 10 2 Memory Controller Architecture The memory controller consists of a basic machine that handles the memory access cycle the general purpose chip select machine GPCM When a new access to external memory is reque...

Page 356: ...tus register MSTAT The MSTAT reports write protect violations for all the banks Each of the four banks has a base register BR and an option register OR The BRx and ORx registers contain the attributes specific to bank x The base register contains a valid bit V that indicates that the register information for that chip select is valid 10 2 2 Port Size Configuration The memory controller supports dy...

Page 357: ...anks If a match is found the attributes defined for this bank in its BR and OR are used to control the memory access If a match is found in more than one bank the lowest bank matched handles the memory access e g bank zero is selected over bank one Note that when an external master access es a slave on the bus the internal AT 0 2 lines reaching the memory controller are forced to 100 10 2 5 Burst ...

Page 358: ...ck cycles The internal TA generation mode is enabled if the SETA bit in the OR register is ne gated However if the TA pin is asserted externally at least two clock cycles before the Table 10 1 Timing Attributes Summary Timing Attribute Bits Fields Description Access speed TRLX The TRLX timing relaxed bit determines strobe timing to be fast or re laxed Intercycle space time EHTR The EHTR extended h...

Page 359: ...e respective W in the memory device where each WE BE line corresponds to a different data byte Figure 10 5 MPC555 MPC556 GPCM Memory Devices Interface In Figure 10 6 the CSx timing is the same as that of the address lines output The strobes for the transaction are supplied by the OE and the WE BE lines if pro grammed as WE BE Because the ACS bits in the corresponding ORx register 00 CS is asserted...

Page 360: ...al Devices Interface Example Figure 10 7 illustrates the basic connection between the MPC555 MPC556 and an external peripheral device In this case CSx is connected directly to the chip enable CE of the memory device and the R W line is connected to the R W in the peripheral device The CSx line is the strobe output for the memory access Clock Address CS WE BE OE Data TS TA CSNT 1 ACS 00 Freescale S...

Page 361: ...required by the peripheral device This is accomplished through the ACS field in the base register In Figure 10 8 the ACS bits are set to 11 so CSx is asserted half a clock cycle after the address lines are valid Figure 10 8 Peripheral Devices Basic Timing ACS 11 TRLX 0 Peripheral Address CE R W Data Address CSx RD WR Data MPC555 MPC556 CLOCK Address TS TA CS RD WR Data ACS 11 CSNT 1 Freescale Semi...

Page 362: ... and TRLX 1 the memory controller does not support external devices providing TA to complete the transfer with zero wait states The minimum access du ration in this case equals three clock cycles Figure 10 9 shows a read access with relaxed timing Note the following Strobes OE and CS assertion time is delayed one clock relative to address TRLX bit set effect Strobe CS is further delayed half clock...

Page 363: ...1 Figure 10 9 Relaxed Timing Read Access ACS 11 SCY 1 TRLX 1 CLOCK Address TS TA CS RD WR WE BE Data OE ACS 11 TRLX 1 ACS 00 TRLX 1 WEBS 0 Line Acts as BE in Read Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 364: ...S assertion is delayed an additional one quarter clock cycle because ACS 10 The total cycle length three clock cycles determined as follows The basic memory cycle requires two clock cycles An extra clock cycle is required due to the effect of TRLX on the strobes Figure 10 10 Relaxed Timing Write Access ACS 10 SCY 0 CSNT 0 TRLX 1 CLOCK Address TS TA CS RD WR WE BE Data OE ACS 10 Freescale Semicondu...

Page 365: ...cle earlier than normal Refer to Figure 10 6 The total cycle length is four clock cycles determined as follows The basic memory cycle requires two clock cycles Two extra clock cycles are required due to the effect of TRLX on the assertion and negation of the CS and WE strobes Figure 10 11 Relaxed Timing Write Access ACS 11 SCY 0 CSNT 1 TRLX 1 Clock Address TS TA CS RD WR WE BE Data OE ACS 11 ACS 0...

Page 366: ...d due to the effect of TRLX on the negation of the WE BE strobes Figure 10 12 Relaxed Timing Write Access ACS 00 SCY 0 CSNT 1 TRLX 1 10 3 4 Extended Hold Time on Read Accesses For devices that require a long disconnection time from the data bus on read access es the bit EHTR in the corresponding OR register can be set In this case any MPC555 MPC556 access to the external bus following a read acces...

Page 367: ...er tim ing Figure 10 13 shows a write access following a read access Because EHTR 0 no extra clock cycle is inserted between memory cycles Figure 10 13 Consecutive Accesses Write After Read EHTR 0 CLOCK Address TS TA CSx CSy RD WR Data OE Tdt Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 368: ... cycles For a write cycle following a read this is true re gardless of whether both accesses are to the same region Figure 10 14 Consecutive Accesses Write After Read EHTR 1 CLOCK Address TS TA CSx CSy RD WR Data OE Tdt Long Tdt allowed Extra clock before next cycle starts Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 369: ...he accesses are to different banks an extra clock cycle is inserted Figure 10 15 Consecutive Accesses Read After Read From Different Banks EHTR 1 Clock Address TS TA CSx CSy RD WR Data OE Tdt Long Tdt Allowed Extra Clock Before Next Cycle Starts Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 370: ...he case of two consecutive read cycles to the same region data contention is not a concern Figure 10 16 Consecutive Accesses Read After Read From Same Bank EHTR 1 10 3 5 Summary of GPCM Timing Options Table 10 2 summarizes the different combinations of timing options CLOCK Address TS TA CSx CSy RD WR Data OE Tdt Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Pro...

Page 371: ...dress to CS Asserted CS Negated to Add Data Invalid Address to WE BE or OE Asserted WE BE Negated to Add Data Invalid OE Negated to Add Data Invalid Total Number of Cycles 0 Read 00 X 0 1 4 clock 3 4 clock X 1 4 clock 2 SCY 0 Read 10 X 1 4 clock 1 4 clock 3 4 clock X 1 4 clock 2 SCY 0 Read 11 X 1 2 clock 1 4 clock 3 4 clock X 1 4 clock 2 SCY 0 Write 00 0 0 1 4 clock 3 4 clock 1 4 clock X 2 SCY 0 W...

Page 372: ...l address types CS 0 operates in this way until the first write to the CS 0 option register OR0 The pin can be programmed to continue decoding a range of addresses after this write provided the preferred address range is first loaded into base register zero After the first write to OR0 the global chip select can only be re started with a system reset The memory controller operates in boot mode unt...

Page 373: ...3 BE 3 indicates that the lower eight bits of the data bus contains valid data during a write cycle The write byte enable lines affected in a transaction for 32 bit port PS 00 a 16 bit port PS 10 and a 8 bit port PS 01 are shown in Table 10 4 This table shows which write enables are asserted indicated with an X for different combina tions of port size and transfer size 10 6 Dual Mapping of the Int...

Page 374: ...he location of the address map of the MPC555 MPC556 With dual mapping aliasing of address spaces may occur This happens when the user maps the dual mapped region into a region which is also mapped into one of the four regions available in the memory controller If the user writes code or data to the dual mapped region care must be taken to avoid overwriting this code or data by nor mal accesses of ...

Page 375: ...the MPC555 MPC556 internal flash memory Hence caution should be taken to change the dual mapping setup before the first data ac cess NOTE Dual mapping is not supported for an external master when the mem ory controller serves the access In such a case the MPC555 MPC556 terminates the cycle by asserting TEA MPC555 MPC556 Memory Map CSx Physical External Memory External CSx Flash Dual Mapping Dual M...

Page 376: ...the internal space the actual ad dess that is used for comparing against the memory controller regions is in the format of 00000000 bits 8 16 of the external address In the case where a match is found the controls to the memory devices are generated and the transfer acknowledge indi cation TA is supplied to the master Since it takes two clocks for the external address to be recognized and handled ...

Page 377: ...vices Memory Address CE OE W Data Address CSx OE WE BE Data Synchronous External Master TS TA TA TS ADDR Data BDIP BDIP BDIP BURST Note that the memory controller s BDIP line is used as a burst_in_progress signal BURST BURST MTS TS MPC555 MPC556 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 378: ...PC556 has only 24 address pins the eight most sig nificant internal address lines are driven as 0x0000_0000 and so compared in the memory controller s regions CLOCK ADDR 0 31 CS WE BE OE Data TS TA Address Match Compare Memory Device Access RD WR BURST TSIZE MTS Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 379: ...r then it can support access es to 32 bit port devices only This is because the MPC555 MPC556 external bus interface cannot initiate extra cycles to complete an access to a smaller port size device as it does not own the external bus 3 When the SETA bit in the base register is set then the timing programming for the various strobes CS OE and WE BE may become meaningless Table 10 5 Memory Controlle...

Page 380: ...on 0 7 Reserved 8 11 WPER0 WPER3 Write protection error for bank x This bit is asserted when a write protect error occurs for the associated memory bank A bus monitor responding to TEA assertion will if enabled prompt the user to read this register if TA is not asserted during a write cycle WPERx is cleared by writ ing one to the bit or by performing a system reset Writing a zero has no effect on ...

Page 381: ...nable byte select This bit controls the functionality of the WE BE pads 0 The WE BE pads operate as WE 1 The WE BE pads operate as BE 27 TBDIP Toggle burst data in progress TBDIP determines how long the BDIP strobe will be asserted for each data beat in the burst cycles 28 LBDIP Late burst data in progress LBDIP This bit determines the timing of the first assertion of the BDIP pin in burst cycles ...

Page 382: ...This field can be read or written at anytime Following a system reset the AM bits are reset in OR0 17 19 ATM Address type mask This field masks selected address type bits allowing more than one address space type to be assigned to a chip select Any set bit causes the corresponding address type code bits to be used as part of the address comparison Any cleared bit masks the corresponding address ty...

Page 383: ...xternal memory access and thus us ing SCY 0 3 as the main parameter for determining the length of that cycle The total cycle length may vary depending on the settings of other timing attributes The total memory access length for the beat is is 1 BSCY x Clocks If the user has selected an external TA response for this memory bank by setting the SETA bit then BSCY 0 3 are not used 000 0 clock cycle 1...

Page 384: ...type These bits are used in conjunction with the ATM bits in the OR The default value at reset is to map data only For a full definition of address types refer to 9 5 7 6 Address Types 13 27 Reserved 28 30 DMCS Dual mapping chip select This field determines which chip select pin is assigned for dual mapping 000 CS 0 001 CS 1 010 CS 2 011 CS 3 1xx Reserved 31 DME Dual mapping enabled This bit indic...

Page 385: ...e than one area of the address map This field can be read or written at any time 7 9 Reserved 10 12 ATM Address type mask This field can be used to mask certain address type bits allowing more than one address space type to be assigned to a chip select Any set bit causes the corre sponding address type code bits to be used as part of the address comparison Any cleared bit masks the corresponding a...

Page 386: ...MPC555 MPC556 MEMORY CONTROLLER MOTOROLA USER S MANUAL Rev 15 October 2000 10 34 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 387: ... bus when U bus pipe depth is zero or one Does not accept back to back accesses from the U bus master Non pipelined master and slave on the L bus Generates module selects for L bus memory mapped resources within a pro grammable contiguous block of storage Programmable data memory protection unit DMPU L bus and U bus snoop logic for PowerPC reservation protocol L2U does not support dual mapping of ...

Page 388: ...pr instructions to from imple mentation specific special purpose registers No protection for accesses to the SRAM module on the L bus SRAM has its own protection options 11 3 L2U Block Diagram Figure 11 1 shows a block diagram of the L bus to U bus interface Figure 11 1 L2U Bus Interface Block Diagram 11 4 Modes Of Operation The L2U Module can operate in the following modes Normal Mode Reset Opera...

Page 389: ...s of reservations on the L bus and the U bus For the L bus and the U bus the L2U detects reservation losses and up dates the RCPU core with the reservation status 11 4 2 Reset Operation Upon soft reset assertion the L2U goes to an idle state and all pending accesses are ignored The L2U module control registers are not initialized on the assertion of a soft reset keeping the system configuration un...

Page 390: ... information region protection on off region base address region size and the region s access permissions Each region s protection attributes can be turned on off by configuring the enable attribute bit ENRx located in the global region attribute register During each load store access from the RCPU core to the U bus the address is com pared to the value in the region base address register of each ...

Page 391: ...is event as a data storage violation only when the access becomes non speculative Note that access protection is active only when the PowerPC s MSR DR 1 When MSR DR 0 DMPU exceptions are disabled all accesses are considered to be to a guarded memory area and no speculative accesses are allowed In this case if the L bus master RCPU initiates a non SRAM cycle access through the L2U that is marked sp...

Page 392: ...e effective base address of region zero is 0 x 0 See Figure 11 3 Figure 11 3 Region Base Address Example It is the user s responsibility to program only legal region sizes The L2U does not check whether the value is legal If the user programs an illegal region size the region calculation may not be successful Table 11 1 DMPU Registers Name Description L2U_RBA0 Region Base Address Register 0 L2U_RB...

Page 393: ...nstruction and sets again the reservation flag A stwcx instruction by same processor clears the reservation flag A store instruction by same processor does not clear the reservation flag Some other processor or other mechanism store to an address with an existing reservation clears the reservation flag In case the storage reservation is lost it is guaranteed that stwcx will not modify the storage ...

Page 394: ... Storage reservation is cleared regardless of the data phase ter mination status of the stwcx access if the address phase is terminated normally Storage reservation will be cleared regardless of the data phase termination status of the write requests by another master to the reserved address if the address phase of the write access is terminated normally on the destination U bus L bus bus If the p...

Page 395: ... does not have enough time to stop the write access from completing In this case the L2U will drive cancel reservation signal back to the core as soon as it comes to know that the alternate master on the U bus has touched the reserved location U Master Request to cancel the reservation U bus L Master Block stwcx2 2 If the RCPU tries to modify stwcx that location the L2U does not start the cycle on...

Page 396: ... the U bus transfer as a a bus master and then completes the ad dress phase and data phase of the cycle as a slave The L2U follows U bus protocol of in order termination of the data phase The USIU can control the start of show cycles on the U bus by asserting the no show cycle indicator This will cause the L2U module to release the U bus for at least one clock before retrying the show cycle 11 7 4...

Page 397: ... 11 7 6 Show Cycle Support Guidelines The following are the guidelines for L2U show cycle support The L2U module provides address and data for all qualifying L bus cycles when the appropriate mode bits are set in the L2U_MCR The L2U module only show cycles L bus activity that is not targeted for the U bus or the L2U module internal registers irrespective of the termination status of such activity ...

Page 398: ...peripheral mode access Table 11 4 L2U Show Cycle Support Chart Case Destination LB AACK LB ABORT Comments 1 L bus Slave1 No X Not show cycled Cycle will be retried one clock later 4 2 L2U 2 X X Not show cycled 3 U bus E bus 3 X X Not show cycled 4 L bus slave Yes No Show cycled 5 L bus slave Yes Yes Not show cycled L bus will be released next clock Table 11 5 L2U PPC Register Decode Name SPR SPR5 ...

Page 399: ...isters There is no PowerPC instruction to access either a half word or a byte of the special purpose register All L2U registers are only word accessible read and write in peripheral mode A half word or byte access in peripheral mode will result in a word transaction 11 8 3 L2U Module Configuration Register L2U_MCR The L2U module configuration register L2U_MCR is used to control the L2U module oper...

Page 400: ...on the U bus If L bus show cycles are enabled setting this bit will disable L bus SRAM show cycles 1 2 LSHOW LSHOW bits are used to configure the show cycle mode for cycles accessing the L bus slave e g SRAM 00 Disable show cycles 01 Show address and data of all L bus space write cycles 10 Reserved 11 Show address and data of all L bus space read and write cycles 3 31 Reserved L2U_RBAx L2U Region ...

Page 401: ...22 23 24 25 26 27 28 29 30 LSB 31 RS PP RESERVED G RESERVED RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 11 9 L2U_RAx Bit Descriptions Bit s Name Description 0 7 Reserved 8 19 RS Region size 0000_0000_0000 4 Kbytes 0000_0000_0001 8 Kbytes 0000_0000_0011 16 Kbytes 0000_0000_0111 32 Kbytes 0000_0000_1111 64 Kbytes 0000_0001_1111 128 Kbytes 0000_0011_1111 256 Kbytes 0000_0111_1111 512 Kbytes 0000_1111...

Page 402: ...able attribute for region 1 0 Region attribute is off 1 Region attribute is on 2 ENR2 Enable attribute for region 2 0 Region attribute is off 1 Region attribute is on 3 ENR3 Enable attribute for region 3 0 Region attribute is off 1 Region attribute is on 4 19 Reserved 20 21 PP Protection bits 00 No supervisor access no user access 01 Supervisor read write access no user access 10 Supervisor read w...

Page 403: ...te interfacing between the U bus and the IMB3 15 bits 32 Kbytes of address decode on IMB3 32 bit data bus Read write access to IMB3 module registers1 Interrupt synchronizer Monitoring of accesses to unimplemented addresses within UIMB interface address range Burst inhibited accesses to the modules on IMB3 Support of 32 bit and 16 bit BIUs for IMB3 modules Half and full speed operation of IMB3 bus ...

Page 404: ...ed If the STOP bit is 0 and the HSPEED bit is 0 the IMB clock is generated as the inversion of the internal system clock This is the same frequency as the CLKOUT if EBDF is 0b00 full speed external bus See Figure 12 2 If the HSPEED bit is 1 then the IMB clock is one half of the internal system frequency See Figure 12 3 Table 12 1 STOP and HSPEED Bit Functionality STOP HSPEED Functionality 0 0 IMB ...

Page 405: ...al port size signal 12 4 Interrupt Operation The interrupts from the modules on the IMB3 are propagated to the interrupt controller in the USIU through the UIMB interface The UIMB interrupt synchronizer latches the Interrupts from the IMB3 and drives them onto the U bus where they are latched by the USIU interrupt controller Table 12 2 Bus Cycles and System Clock Cycles Bus Cycle from U bus Transf...

Page 406: ...levels to the interrupt synchronizer A diagram of the interrupt flow is shown in Figure 12 4 Figure 12 4 Interrupt Synchronizer Signal Flow Latching 32 interrupt levels using eight IMB interrupt lines is accomplished with a 4 1 time multiplexing scheme The UIMB drives two signals ILBS 0 1 with a multiplexer select code that tells all interrupting modules on the IMB about which group of signals to ...

Page 407: ...ure 12 5 Time Multiplexing Protocol for IRQ pins The IRQMUX bits determine how many levels of IMB interrupts are sampled Refer to Table 12 4 Table 12 3 ILBS Signal functionality ILBS 0 1 Description 00 IMB interrupt sources mapped onto 0 7 levels will drive interrupts onto IMB IRQ 0 7 01 IMB interrupt sources mapped onto 8 15 levels will drive interrupts onto IMB IRQ 0 7 10 IMB interrupt sources m...

Page 408: ...g register UIPEND in the UIMB If any of the reg ister bits 7 to 31 are set then bit 7 will be set as well Software must poll this register to find out which of the levels 7 to 31 are asserted The UIPEND register contains a status bit for each of the 32 interrupt levels Each bit of the register is a read only status bit reflecting the current state of the corresponding interrupt signal For each of ...

Page 409: ...on to be asserted Unimplemented bits in a register return zero when read 12 5 1 UIMB Module Configuration Register UMCR The UIMB module configuration register UMCR is accessible in supervisor mode only Table 12 5 UIMB Interface Register Map Access Base Address Register S1 NOTES 1 S Supervisor mode only T Test mode only 0x30 7F80 UIMB Module Configuration Register UMCR See Table 12 6 for bit descri...

Page 410: ... 8 0 7 interrupt request lines to the interrupt controller 01 Enables the IMB IRQ control logic to perform a 2 to 1 multiplexing to allow transferring of 16 0 15 interrupt sources 10 Enables the IMB IRQ control logic to perform a 3 to 1 multiplexing to allow transferring of 24 0 23 interrupt sources 11 Enables the IMB IRQ control logic to perform a 4 to 1 multiplexing to allow transferring of 32 0...

Page 411: ...it Descriptions Bit s Name Description 0 31 LVLx Pending interrupt request level Accessible only in supervisor mode LVLx identifies the interrupt source as UIMB LVLx where x is the interrupt number Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 412: ... MPC556 U BUS TO IMB3 BUS INTERFACE UIMB MOTOROLA USER S MANUAL Rev 15 October 2000 12 10 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 413: ...sion is performed by the digital to analog converter DAC resistor capacitor array a high gain comparator and a successive approximation register SAR The digital control section contains the conversion sequencing logic Also included are the periodic interval timer control and status registers the conversion command word CCW table RAM and the result word table RAM Figure 13 1 QADC64 Block Diagram QU...

Page 414: ...mmand queues 1 and 2 Single scan or continuous scan of queues 64 result registers Output data readable in three formats Right justified unsigned Left justified signed Left justified unsigned Unused analog channels can be used as digital ports 13 3 QADC64 Pin Functions The two QADC64 modules use the following 38 pins Two analog reference pins to which all analog input voltages are scaled shared by ...

Page 415: ... are referred to as PQA when used as a bidirectional 8 bit digital input out put port These eight pins may be used for general purpose digital input signals or dig ital output signals QADC64 PINOUT AN52 MA0 PQA0 AN53 MA1 PQA1 AN54 MA2 PQA2 AN55 PQA3 AN56 PQA4 AN57 PQA5 AN58 PQA6 AN59 PQA7 AN0 ANW PQB0 AN1 ANX PQB1 AN2 ANY PQB2 AN3 ANZ PQB3 AN48 PQB4 AN49 PQB5 AN50 PQB6 AN51 PQB7 DIGITAL RESULTS AN...

Page 416: ... 7 0 when used as an 8 bit digital input only port In addition to functioning as analog input pins the port B pins are also connected to the input of a synchronizer during reads and may be used as general purpose digital inputs Since port B pins are input only there is no associated data direction register Digital input signal states are read from the PORTQB data register Since a port B read cap t...

Page 417: ... power supply pins allows for additional external filtering which increases reference voltage precision and stability and subsequently contributes to a higher degree of conversion accuracy 13 3 7 Dedicated Analog Supply Pins VDDA and VSSA pins supply power to the analog subsystems of the QADC64 module Dedicated power is required to isolate the sensitive analog circuitry from the normal levels of n...

Page 418: ...s the QADC64 and not changed thereafter Refer to 13 12 1 QADC64 Module Configuration Register for register and bit descriptions 13 5 1 Low Power Stop Mode When the STOP bit in QADC64MCR is set the clock signal to the A D converter is dis abled effectively turning off the analog circuitry This results in a static low power con sumption idle condition Low power stop mode aborts any conversion sequen...

Page 419: ... normal operation The QADC64 looks at the queue operating modes the current queue pointer and any pending trigger events to decide which CCW to ex ecute If the FRZ bit is clear assertion of the IMB FREEZE line is ignored 13 5 3 Supervisor Unrestricted Address Space The QADC64 memory map is divided into two segments supervisor only data space and assignable data space Access to supervisor only data...

Page 420: ...lexed address outputs are driven The data returned during a port data register read is the value of the multiplexed address latches which drive MA 2 0 regardless of the data direction setting 13 6 1 Port Data Register QADC64 ports A and B are accessed through two 8 bit port data registers PORTQA and PORTQB Port A pins are referred to as PQA when used as an 8 bit input output port Port A can also b...

Page 421: ...y high speed digital signals near the MCU The QADC64 can use from one to four external multiplexers to expand the number of analog signals that may be converted Up to 32 analog channels can be converted through external multiplexer selection The externally multiplexed channels are auto matically selected from the channel field of the CCW table the same as internally mul tiplexed channels All of th...

Page 422: ...ed address outputs 13 8 Analog Input Channels The number of available analog channels varies depending on whether or not external multiplexing is used A maximum of 16 analog channels are supported by the internal multiplexing circuitry of the converter Table 13 2 shows the total number of analog in put channels supported with zero to four external multiplexers AN52 MA0 PQA0 AN53 MA1 PQA1 AN54 MA2 ...

Page 423: ...ds into the SAR Figure 13 4 shows a block diagram of the QADC64 analog submodule Table 13 2 Analog Input Channels Number of Analog Input Channels Available Directly Connected External Multiplexed Total Channels1 NOTES 1 When external multiplexing is used three input channels become multiplexed address out puts and for each external multiplexer chip one input channel becomes a multiplexed ana log i...

Page 424: ...s Final sample time can be 2 4 8 or 16 QCLK cycles depending on the value of the IST field in the CCW Resolution time is ten QCLK cycles Sample and resolution require a minimum of 14 QCLK clocks 7 µs with a 2 MHz QCLK If the maximum final sample time period of 16 QCLKs is selected the total conversion time is 13 0 µs with a 2 MHz QCLK Figure 13 5 illustrates the timing for conversions This diagram...

Page 425: ... the ex ternal circuit should be of low source impedance typically less than 10 kΩ Also the loading effects of the external circuitry by the QADC64 need to be considered since the benefits of the sample amplifier are not present NOTE Because of internal RC time constants a sample time of two QCKLs in bypass mode for high frequency operation is not recommended Figure 13 6 Bypass Mode Conversion Tim...

Page 426: ...ic 13 9 4 Comparator The comparator is used during the approximation process to sense whether the digi tally selected arrangement of the DAC array produces a voltage level higher or lower than the sampled input The comparator output feeds into the SAR which accumulates the A D conversion result sequentially starting with the MSB 13 9 5 Successive Approximation Register The input of the successive ...

Page 427: ... active trigger event occurs for Queue 2 Queue 2 cannot begin execution until queue 1 reaches completion or the paused state The status register records the trigger event by reporting the queue 2 status as trigger pending Additional trigger events for queue 2 which occur before execution can begin are recorded as trigger overruns Queue 2 active trigger event occurs for Queue 1 The current queue 2 ...

Page 428: ... continue with the next CCW which is the beginning of the next sub queue A sub queue cannot be executed a second time before the overall queue execution has been completed Trigger events which occur during the execution of a sub queue are ignored except that the trigger overrun flag is set When continuous scan mode is selected a trigger event occurring after the completion of the last sub queue af...

Page 429: ...n flag is set and the queue becomes idle A conversion is not performed BQ2 beginning of queue 2 is set beyond the end of the CCW table 64 127 and a trigger event occurs on queue 2 Refer to 7 6 3 Control Register two for in formation on BQ2 The end of queue condition is recognized immediately the completion flag is set and the queue becomes idle A conversion is not per formed NOTE Multiple end of q...

Page 430: ...ernal trigger single scan mode External gated single scan mode queue 1 only Interval timer single scan mode Software initiated continuous scan mode External trigger continuous scan mode External gated continuous scan mode queue 1 only Interval timer continuous scan mode The following paragraphs describe the disabled reserved single scan and continu ous scan operations 13 10 3 1 Disabled Mode When ...

Page 431: ...eue operating mode the new queue operating mode and the value of the single scan enable bit are recognized immediately The conver sion in progress is aborted and the new queue operating mode takes effect In the software initiated single scan mode the writing of a one to the single scan en able bit causes the QADC64 to internally generate a trigger event and the queue exe cution begins immediately ...

Page 432: ...e scan mode is useful when the input trigger rate can exceed the queue execution rate Analog samples can be taken in sync with an external event even though the software is not interested in data taken from every edge The software can start the external trigger single scan mode and get one set of data and at a later time start the queue again for the next set of samples When a pause bit is encount...

Page 433: ...When the queue execution reaches an end of queue situation the single scan enable bit is cleared Software may set the single scan enable bit again allowing another scan of the queue to be initiated by the interval timer The interval timer generates a trigger event whenever the time interval elapses The trigger event may cause the queue execution to continue following a pause or may be considered a...

Page 434: ...es queue execution to begin again starting with the first CCW in the queue NOTE In this version of QADC64 coherent samples can be guaranteed The time between consecutive conversions has been designed to be consistent provided the sample time bits in both the CCW and IST are identical However there is one exception For queues that end with a CCW containing EOQ code channel 63 the last queue con ver...

Page 435: ...can mode is selected a transition on the associated external trigger pin initiates queue ex ecution The polarity of the external trigger signal is programmable so that the soft ware can choose to begin queue execution on the rising or falling edge Each CCW is read and the indicated conversions are performed until an end of queue condition is encountered When the next external trigger edge is detec...

Page 436: ...d or queue 2 Software se lects a programmable timer interval ranging from 128 to 128 Kbytes times the QCLK period in binary multiples The QCLK period is prescaled down from the intermodule bus IMB MCU clock When a periodic timer continuous scan mode is selected for queue 1 and or queue 2 the timer begins counting After the programmed interval elapses the timer generated trigger event starts the ap...

Page 437: ... most software applications initialize the prescaler once and do not change it write operations to the prescaler fields are permitted NOTE For software compatibility with earlier versions of QADC64 the defi nition of PSL PSH and PSA have been maintained However the requirements on minimum time and minimum low time no longer ex ist CAUTION A change in the prescaler value while a conversion is in pr...

Page 438: ...rm with the PSH prescaler clock high time field in QACR0 and selects the basic low phase of QCLK with the prescaler clock low time PSL field The combination of the PSH and PSL pa rameters establishes the frequency of the QCLK PRESCALER RATE SELECTION FROM CONTROL REGISTER 0 BINARY COUNTER PERIODIC INTERVAL TIMER SELECT 2 15 214 213 2 12 211 2 10 2 9 28 27 216 2 17 ONE S COMPLEMENT COMPARE CLOCK GE...

Page 439: ...ator looks for a one s com plement match with the 3 bit PSL value which is the end of the low phase of the QCLK The PSA bit was maintained for software compatibility but has no effect on QADC64 The following equations define QCLK frequency High QCLK Time PSH 1 FSYS Low QCLK Time PSL 1 FSYS FQCLK 1 High QCLK Time Low QCLK Time Where PSH 0 to 31 the prescaler QCLK high cycles in QACR0 PSL 0 to 7 the...

Page 440: ...at the IMB clock frequency be at least twice the QCLK frequency The QCLK frequency is established by the combination of the PSH and PSL parameters in QACR0 The 5 bit PSH field selects the number of IMB clock cycles in the high phase of the QCLK wave The 3 bit PSL field selects the number of IMB clock cycles in the low phase of the QCLK wave Example 1 in Figure 13 9 shows that when PSH 11 the QCLK ...

Page 441: ...ting mode change from one periodic interval timer mode to another periodic in terval timer mode while queue 1 is in an active periodic interval timer mode During the low power stop mode the periodic interval timer is held in reset Since low power stop mode causes QACR1 and QACR2 to be reset to zero a valid periodic or interval timer mode must be written after stop mode is exited to release the tim...

Page 442: ...o one then writing zeros to the flags that are to be cleared A flag can be cleared only if the flag was a logic one at the time the register was read by the CPU If a new event occurs between the time that the register is read and the time that it is written the associated flag is not cleared Table 13 5 QADC64 Status Flags and Interrupt Sources Queue Queue Activity Status Flag Interrupt Enable Bit ...

Page 443: ...urthermore if more than one source on a module requests an interrupt at the same level the system software must assign a priority to each source requesting at that level Figure 13 11 displays the interrupt levels on IRQ with ILBS Figure 13 11 Interrupt Levels on IRQ with ILBS 13 12 Programming Model Each QADC64 occupies 1 Kbyte 512 16 bit entries of address space The address space consists of ten ...

Page 444: ...B_x S U 0x30 4808 0x30 4C08 Port A Data Direction Register DDRQA_x See Table 13 10 for bit descriptions S U 0x30 480A 0x30 4C0A QADC64 Control Register 0 QACR0_x See Table 13 11 for bit descriptions S U 0x30 480C 0x30 4C0C QADC64 Control Register 1 QACR1_x See Table 13 12 for bit descriptions S U 0x30 480E 0x30 4C0E QADC64 Control Register 2 QACR2_x See Table 13 14 for bit descriptions S U 0x30 48...

Page 445: ...OP Low power stop mode enable When the STOP bit is set the clock signal to the QADC64 is dis abled effectively turning off the analog circuitry 0 Enable QADC64 clock 1 Disable QADC64 clock 1 FRZ FREEZE assertion response The FRZ bit determines whether or not the QADC64 responds to assertion of the IMB3 FREEZE signal 0 QADC64 ignores the IMB3 FREEZE signal 1 QADC64 finishes any current conversion t...

Page 446: ...quest 10 15 Reserved PORTQA Port QA Data Register 0x30 4806 PORTQB Port QB Data Register 0x30 4C06 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 PQA7 PQA6 PQA5 PQA4 PQA3 PQA2 PQA1 PQA0 PQB7 PQB6 PQB5 PQB4 PQB3 PQB2 PQB1 PQB0 RESET U U U U U U U U U U U U U U U U ANALOG CHANNEL AN59 AN58 AN57 AN56 AN55 AN54 AN53 AN52 AN51 AN50 AN49 AN48 AN3 AN2 AN1 AN0 MULTIPLEXED ADDRESS OUTPUTS MA2 MA1 MA0 MULTIP...

Page 447: ... 4C08 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 DDQA7 DDQA 6 DDQA 5 DDQA 4 DDQA 3 DDQA 2 DDQA 1 DDQA 0 RESERVED RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 13 10 DDRQA Bit Descriptions Bit s Name Description 0 7 DDQA 7 0 Bits in this register control the direction of the port QA pin drivers when pins are configured for I O Setting a bit configures the corresponding pin as an output clearing a ...

Page 448: ...ltiplexed 16 possible channels 1 Externally multiplexed 41 possible channels 1 2 Reserved 3 TRG Trigger assignment TRG allows the software to assign the ETRIG 2 1 pins to queue 1 and queue 2 0 ETRIG1 triggers queue 1 ETRIG2 triggers queue 2 1 ETRIG1 triggers queue 2 ETRIG2 triggers queue 1 4 6 Reserved 7 11 PSH Prescaler clock high time The PSH field selects the QCLK high time in the prescaler PSH...

Page 449: ...interrupts disabled 1 Generate an interrupt request after completing a CCW in queue 1 which has the pause bit set 2 SSE1 Queue 1 single scan enable SSE1 enables a single scan of queue 1 after a trigger event occurs The SSE1 bit may be set to a one during the same write cycle that sets the MQ1 bits for the sin gle scan queue operating mode The single scan enable bit can be written as a one or a zer...

Page 450: ...e time QCLK period x 214 0b01100 Interval timer single scan mode time QCLK period x 215 0b01101 Interval timer single scan mode time QCLK period x 216 0b01110 Interval timer single scan mode time QCLK period x 217 0b01111 External gated single scan mode started with SSE1 0b10000 Reserved mode 0b10001 Software triggered continuous scan mode 0b10010 External trigger rising edge continuous scan mode ...

Page 451: ...nt oc curs The SSE2 bit may be set to a one during the same write cycle that sets the MQ2 bits for the single scan queue operating mode The single scan enable bit can be written as a one or a zero but is always read as a zero The SSE2 bit allows a trigger event to initiate queue execution for any single scan operation on queue 2 The QADC64 clears SSE2 when the single scan is complete 3 7 MQ2 Queue...

Page 452: ... scan mode interval QCLK period x 214 0b01100 Interval timer single scan mode interval QCLK period x 215 0b01101 Interval timer single scan mode interval QCLK period x 216 0b01110 Interval timer single scan mode interval QCLK period x 217 0b01111 Reserved mode 0b10000 Reserved mode 0b10001 Software triggered continuous scan mode started with SSE2 0b10010 External trigger rising edge continuous sca...

Page 453: ...hed a pause PF2 is set by the QADC64 when the current queue 2 CCW has the pause bit set the selected input channel has been converted and the result has been stored in the result table 0 Queue 2 has not reached a pause 1 Queue 2 has reached a pause 4 TOR1 Queue 1 trigger overrun TOR1 indicates that an unexpected queue 1 trigger event has oc curred TOR1 can be set only while queue 1 is active A tri...

Page 454: ... to it have no effect Table 13 17 Queue Status QS Description 0b0000 Queue 1 idle queue 2 idle 0b0001 Queue 1 idle queue 2 paused 0b0010 Queue 1 idle queue 2 active 0b0011 Queue 1 idle queue 2 trigger pending 0b0100 Queue 1 paused queue 2 idle 0b0101 Queue 1 paused queue 2 paused 0b0110 Queue 1 paused queue 2 active 0b0111 Queue 1 paused queue 2 trigger pending 0b1000 Queue 1 active queue 2 idle 0...

Page 455: ...irst location in the CCW table Table 13 18 QASR0 Bit Descriptions Bit s Name Description 0 1 Reserved 2 7 CWPQ1 Command word pointer for queue 1 This field is a software read only field and write operations have no effect CWPQ1 allows software to read the last executed CCW in queue 1 regardless which queue is active The CWPQ1 field is a CCW word pointer with a valid range of 0 to 63 In contrast to...

Page 456: ...can sequence may be initiated by the following A software command QADC64 C 00 BEGIN Queue 1 BQ2 63 END OF Queue 1 BEGIN Queue 2 END OF Queue 2 P IST CHAN 6 8 7 9 11 12 13 14 10 15 P PAUSE AFTER CONVERSION UNTIL NEXT TRIGGER IST INPUT SAMPLE TIME CHAN CHANNEL NUMBER AND END OF QUEUE CODE 10 BIT CONVERSION COMMAND WORD FORMAT 00 63 RESULT RESULT S RESULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RIGHT JUS...

Page 457: ...ntil the end of the queue is detected or a pause bit is found in a CCW When the pause bit is set in the current CCW the QADC64 stops execution of the queue until a new trigger event occurs The pause status flag bit is set which may cause an interrupt to notify the software that the queue has reached the pause state After the trigger event occurs the paused state ends and the QADC64 continues to ex...

Page 458: ...disabled mode does not power down the converter Software can change the queue operating mode to another valid mode Any con version in progress for that queue is aborted The queue restarts at the beginning of the queue once an appropriate trigger event occurs For low power operation software can set the stop mode bit to prepare the mod ule for a loss of clocks The QADC64 aborts any conversion in pr...

Page 459: ...L period x 8 11 QCKL period x 16 10 15 CHAN Channel number The CHAN field selects the input channel number corresponding to the analog input pin to be sampled and converted The analog input pin channel number assignments and the pin definitions vary depending on whether the QADC64 is operating in multiplexed or non multiplexed mode The queue scan mechanism sees no distinction between an internally...

Page 460: ...I O I I 111010 111011 111100 111101 58 59 60 61 VRH VRL 2 End of Queue Code 111110 111111 62 63 Table 13 21 Multiplexed Channel Assignments and Pin Designations Multiplexed Input Pins Channel Number in CHAN Port Pin Name Analog Pin Name Other Functions Pin Type I O Binary Decimal PQB0 PQB1 PQB2 PQB3 ANw ANx ANy ANz I I I I 00xxx0 00xxx1 01xxx0 01xxx1 0 to 14 even 1 to 15 odd 16 to 30 even 17 to 31...

Page 461: ...stified with zeros in the unused lower order bits The left justified signed format corresponds to a half scale offset binary two s com plement data format The data is routed onto the IMB according to the selected format The address used to access the table determines the data alignment format All write operations to the result word table are right justified The conversion result is unsigned right ...

Page 462: ...ed left justified data Unused bits return zero when read LJURR Left Justified Unsigned Result Register 0x30 4B80 0x30 4BFE 0x30 4F80 0x30 4FFE MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 RESULT RESERVED RESET 0 0 0 0 0 0 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 463: ...PI is fully compatible with the SPI sys tems found on other Motorola devices The dual independent SCIs are used to communicate with external devices and other MCUs via an asynchronous serial bus Each SCI is a full duplex universal asynchro nous receiver transmitter UART serial interface The original QSMCM SCI is en hanced by the addition of an SCI and a common external baud clock source The SCI1 h...

Page 464: ... The QSMCM memory map shown in Table 14 1 includes the global registers the QSPI and dual SCI control and status registers and the QSPI RAM The QSMCM memory map can be divided into supervisor only data space and assignable data space The address offsets shown are from the base address of the QSMCM module Refer to 1 3 MPC555 MPC556 Address Map for a diagram of the MPC555 MPC556 internal memory map ...

Page 465: ...Register PORTQS See 14 6 1 Port QS Data Register PORTQS for bit descriptions S U 0x30 5016 QSMCM Pin Assignment Register PQSPAR See Table 14 10 for bit descriptions QSMCM Data Direction Register DDRQS See Table 14 11 for bit descriptions S U 0x30 5018 QSPI Control Register 0 SPCR0 See Table 14 13 for bit descriptions S U 0x30 501A QSPI Control Register 1 SPCR1 See Table 14 15 for bit descriptions ...

Page 466: ...well as the QSPI RAM All registers and RAM can be accessed on byte 8 bits half word 16 bits and word 32 bit boundaries Word accesses require two consecutive IMB3 bus cycles 14 5 QSMCM Global Registers The QSMCM global registers contain system parameters used by the QSPI and SCI submodules for interfacing to the CPU and the intermodule bus The global registers are listed in Table 14 2 QSMCM Global ...

Page 467: ...FREEZE assertion 14 5 3 Access Protection The SUPV bit in the QMCR defines the assignable QSMCM registers as either super visor only data space or unrestricted data space When the SUPV bit is set all registers in the QSMCM are placed in supervisor only space For any access from within user mode the IMB3 address acknowledge AACK signal is asserted and a bus error is generated Because the QSMCM cont...

Page 468: ... quest lines The QSMCM module is capable of generating one of the 32 possible interrupt levels on the IMB3 The levels that the interrupt will drive can be programmed into the inter rupt request level ILDSCI and ILQSPI bits located in the interrupt configuration reg ister QDSCI_IL and QSPI_IL This value determines which interrupt signal IRQB 0 7 is driven onto the bus during the programmed time slo...

Page 469: ... when the CPU is in supervisor mode QSMCMMCR QSMCM Configuration Register 0x30 5000 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 STOP FRZ1 RESERVED SUPV RESERVED IARB RESET 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 IRQ 7 0 Interrupt Level Encoder ILBS 1 0 SCI1 and 2 Int QSPI 4 0 Int Lev Reg 4 0 2 Lev Reg 4 0 5 5 SCI_1 Interrupt SCI_2 Interrupt QSPI Interrupt 8 Interrupt Level Decoder 8 8 Freescale Semicond...

Page 470: ...1 Low Power Stop Operation 0 Normal clock operation 1 Internal clocks stopped 1 FRZ1 Freeze1 bit Refer to 14 5 2 Freeze Operation 0 Ignore the FREEZE signal 1 Halt the QSMCM on transfer boundary 2 7 Reserved 8 SUPV Supervisor Unrestricted Refer to 14 5 3 Access Protection 0 Assigned registers are unrestricted user access allowed 1 Assigned registers are restricted only supervisor access allowed 9 ...

Page 471: ...ster DDRQS determines whether QSPI pins are in puts or outputs Clearing a bit makes the corresponding pin an input setting a bit makes the pin an output DDRQS affects both QSPI function and I O function Table 14 10 summarizes the effect of DDRQS bits on QSPI pin function QSPI_IL QSPI Interrupt Level Register 0x30 5006 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 RESERVED ILQSPI RESET 0 0 0 0 0 0 ...

Page 472: ...XDx is a dis crete input Writes to this register affect the pins defined as outputs reads of this register return the actual value of the pins Table 14 8 Effect of DDRQS on QSPI Pin Function QSMCM Pin Mode DDRQS Bit Bit State Pin Function MISO Master DDQS0 0 Serial data input to QSPI 1 Disables data input Slave 0 Disables data output 1 Serial data output from QSPI MOSI Master DDQS1 0 Disables data...

Page 473: ...tion of the SCI submodule Table 14 9 summarizes the QSMCM pin functions See bit descriptions in Table 14 11 PORTQS Port QS Data Register 0x30 5014 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 RESERVED QDRX D2 QDTX D2 QDRX D1 QDTX D1 0 QDPC S3 QDPC S2 QDPC S1 QDPC S0 QD SCK QD MOSI QDMI SO RESET 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 Table 14 9 QSMCM Pin Functions PORTQS Function QSMCM Function QGPI2 RXD...

Page 474: ...eserved 1 QPAPCS3 0 Pin is assigned QGPIO3 1 Pin is assigned PCS3 function 2 QPAPCS2 0 Pin is assigned QGPIO2 1 Pin is assigned PCS2 function 3 QPAPCS1 0 Pin is assigned QGPIO1 1 Pin is assigned PCS1 function 4 QPAPCS0 0 Pin is assigned QGPIO0 1 Pin is assigned PCS 0 function 5 Reserved 6 QPAMOSI 0 Pin is assigned QGPIO5 1 Pin is assigned MOSI function 7 QPAMISO 0 Pin is assigned QGPIO4 1 Pin is a...

Page 475: ...6 2 PORTQS Pin Assignment Register PQSPAR 8 Reserved 9 QDDPCS3 QSPI pin data direction for the pin PCS3 0 Pin direction is input 1 Pin direction is output 10 QDDPCS2 QSPI pin data direction for the pin PCS2 0 Pin direction is input 1 Pin direction is output 11 QDDPCS1 QSPI pin data direction for the pin PCS1 0 Pin direction is input 1 Pin direction is output 12 QDDPCS0 QSPI pin data direction for ...

Page 476: ...17 clocks 0 425 µs at 40 MHz Programmable delay simplifies the interface to devices that require different delays between transfers QSPI BLOCK CONTROL REGISTERS END QUEUE POINTER QUEUE POINTER STATUS REGISTER DELAY COUNTER COMPARATOR PROGRAMMABLE LOGIC ARRAY 160 BYTE QSPI RAM CHIP SELECT COMMAND DONE 4 4 2 BAUD RATE GENERATOR PCS 2 1 PCS 0 SS MISO MOSI SCK M S M S 8 16 BIT SHIFT REGISTER Rx Tx DAT...

Page 477: ...Wrap around mode allows continuous execution of queued commands In wrap around mode newly received data replaces previously received data in the receive RAM Wrap around mode can simplify the interface with A D converters by continu ously updating conversion values stored in the RAM Continuous transfer mode allows transfer of an uninterrupted bit stream From 8 to 512 bits can be transferred without...

Page 478: ...alized before QSPI operation begins Writing a new value to SPCR0 while the QSPI is enabled disrupts operation Table 14 12 QSPI Register Map Access1 NOTES 1 S Supervisor access only S U Supervisor access only or unrestricted user access assignable data space Address MSB2 2 8 bit registers such as SPCR3 and SPSR are on 8 bit boundaries 16 bit registers such as SPCR0 are on 16 bit boundaries LSB S U ...

Page 479: ...o eight bits Table 14 14 shows the number of bits per transfer 6 CPOL Clock polarity CPOL is used to determine the inactive state of the serial clock SCK It is used with CPHA to produce a desired clock data relationship between master and slave devices 0 The inactive state of SCK is logic zero 1 The inactive state of SCK is logic one 7 CPHA Clock phase CPHA determines which edge of SCK causes data...

Page 480: ...5 6 7 8 9 10 11 12 13 14 LSB 15 SPE DSCKL DTL RESET 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 Table 14 15 SPCR1 Bit Descriptions Bit s Name Description 0 SPE QSPI enable Refer to 14 7 4 1 Enabling Disabling and Halting the SPI 0 QSPI is disabled QSPI pins can be used for general purpose I O 1 QSPI is enabled Pins allocated by PQSPAR are controlled by the QSPI 1 7 DSCKL Delay before SCK When the DSCK bit is ...

Page 481: ...bled 1 Wraparound mode enabled 2 WRTO Wrap to When wraparound mode is enabled and after the end of queue has been reached WRTO determines which address the QSPI executes next The end of queue is determined by an address match with ENDQP 0 Wrap to pointer address 0x0 1 Wrap to address in NEWQP 3 7 ENDQP Ending queue pointer This field determines the last absolute address in the queue to be com plet...

Page 482: ...path disabled 1 Feedback path enabled 6 HMIE HALTA and MODF interrupt enable HMIE enables interrupt requests generated by the HALTA status flag or the MODF status flag in SPSR 0 HALTA and MODF interrupts disabled 1 HALTA and MODF interrupts enabled 7 HALT Halt QSPI When HALT is set the QSPI stops on a queue boundary It remains in a defined state from which it can later be restarted Refer to 14 7 4...

Page 483: ...ddress in ENDQP in SPCR2 If wraparound mode is enabled WREN 1 the SPIF is set after completion of the command defined by ENDQP each time the QSPI cycles through the queue 0 QSPI is not finished 1 QSPI is finished 9 MODF Mode fault flag The QSPI asserts MODF when the QSPI is in master mode MSTR 1 and the SS input pin is negated by an external driver Refer to 14 7 8 Mode Fault for more information 0...

Page 484: ...and to be executed If the corresponding peripheral such as a serial input port is used solely to input data then this segment does not need to be initialized Data must be written to transmit RAM in a right justified format The QSPI cannot mod ify information in the transmit RAM The QSPI copies the information to its data serial izer for transmission Information remains in transmit RAM until overwr...

Page 485: ...eripheral Chip Select Table 14 19 Command RAM Bit Descriptions Bit s Name Description 0 CONT Continue 0 Control of chip selects returned to PORTQS after transfer is complete 1 Peripheral chip selects remain asserted after transfer is complete 1 BITSE Bits per transfer enable 0 Eight bits 1 Number of bits set in BITS field of SPCR0 2 DT Delay after transfer 0 Delay after transfer is 17 FSYS 1 SPCR1...

Page 486: ... being executed The completed queue pointer CPTQP contained in SPSR points to the last command executed The end queue pointer ENDQP contained in SPCR2 points to the final command in the queue The internal pointer is initialized to the same value as NEWQP During normal opera tion the command pointed to by the internal pointer is executed the value in the inter nal pointer is copied into CPTQP the i...

Page 487: ...command control segment and can write only the re ceive data segment of the QSPI RAM The QSPI turns itself off automatically when it is finished by clearing SPE An error condition called mode fault MODF also clears SPE This error occurs when PCS 0 SS is configured for input the QSPI is a system master MSTR 1 and PCS 0 SS is driven low externally Setting the HALT bit in SPCR3 stops the QSPI on a qu...

Page 488: ...en an external device initiates transfers Switching between these modes is controlled by MSTR in SPCR0 Before entering either mode appropriate QSMCM and QSPI registers must be initialized properly In master mode the QSPI executes a queue of commands defined by control bits in each command RAM queue entry Chip select pins are activated data is transmitted from the transmit RAM and received by the r...

Page 489: ...ion data for subsequent transmissions can be written at any time Figure 14 6 Flowchart of QSPI Initialization Operation Initialize QSMCM Global Registers Initialize QSPI Control Registers Initialize PQSPAR PORTQS and DDRQS Initialize QSPI RAM Enable QSPI Begin A2 QSPI Initialization MSTR 1 A1 Y N in this Order Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Produ...

Page 490: ... Working Queue Pointer Changed to NEWQP Is QSPI Disabled N Y N Execute Serial Transfer Store Received Data In RAM Using Queue Pointer Address B1 QSPI Cycle Begins Master Mode Y Assert Peripheral Chip Select s Is PCS To SCK Delay Programmed N Execute Standard Delay Y Execute Programmed Delay Has NEWQP Been Written Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Pr...

Page 491: ...ster Operation Part 2 Is Delay After Transfer Asserted Y N Execute Programmed Delay B1 Write Queue Pointer To CPTQP Status Bits C1 Negate Peripheral Chip Selects Y N Is Continue Bit Asserted Execute Standard Delay Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 492: ...s Wrap Enable Bit Set Y N Reset Working Queue Pointer to NEWQP or 0x0000 Y Disable QSPI A1 N Increment Working Queue Pointer N Is HALT Or FREEZE Asserted A1 Halt QSPI and Set HALTA N Is Interrupt Enable Bit HMIE Set Y Y N Is HALT Or FREEZE Asserted C1 Y N Y Is this the Last Command in the Queue Request Interrupt Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Pro...

Page 493: ...ess A2 Queue Pointer Changed to NEWQP N Y N Write Queue Pointer to CPTQP Status Bits Store Received Data In RAM Using Queue Pointer Address B2 QSPI Cycle Bgins Slave Mode Y Execute Serial Transfer When SCK Received N Y Is Slave Select Pin Asserted Has NEWQP Been Written Is QSPI Disabled Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale c...

Page 494: ...t SPIF Status Flag Request Interrupt Is Interrupt Enable Bit SPIFIE Set Is Wrap Enable Bit Asserted Y N Reset Working Queue Pointer To NEWQP or 0x0000 Y Disable QSPI A2 N Increment Working Queue Pointer N Is HALT or FREEZE Asserted A2 Halt QSPI and Set HALTA N Is Interrupt Enable Bit HMIE Set Y Y N Is HALT Or FREEZE Asserted C2 Y N Y Is this the Last Command in the Queue QSPI SLV2 FLOW6 Request In...

Page 495: ... both may be necessary de pending on the particular application SCK is the serial clock output in master mode and must be assigned to the QSPI for proper operation The PORTQS data register must next be written with values that make the QGPIO 6 SCK bit 13 QDSCK of PORTQS and QGPIO 3 0 PCS 3 0 bits 12 9 QDPCS 3 0 of PORTQS outputs inactive when the QSPI completes a series of transfers Pins allo cate...

Page 496: ...sfers the original pattern is driven until execution of the follow ing transfer begins When CONT is cleared the data in register PORTQS is driven be tween transfers The data in PORTQS must match the inactive states of SCK and any peripheral chip selects used When the QSPI reaches the end of the queue it sets the SPIF flag If the SPIFIE bit in SPCR2 is set an interrupt request is generated when SPI...

Page 497: ...L causes a delay of 128 IMB clocks which equals 3 2 µs for a 40 MHz IMB clock Because of design limits a DSCKL value of one defaults to the same timing as a value of two When DSCK equals zero DSCKL is not used Instead the PCS valid to SCK transi tion is one half the SCK period 14 7 5 4 Delay After Transfer Delay after transfer can be used to provide a peripheral deselect interval A delay can also ...

Page 498: ...er length options The user can choose a default value of eight bits or a programmed value from eight 0b1000 to 16 0b0000 bits inclusive Re served values from 0b0001 to 0b0111 default to eight bits The programmed value must be written into the BITS field in SPCR0 The BITSE bit in each command RAM byte determines whether the default value BITSE 0 or the BITS value BITSE 1 is used 14 7 5 6 Peripheral...

Page 499: ...dur ing servicing can be prevented by clearing SPIFIE but SPIFIE is buffered Clearing it does not end the current request Wraparound mode is exited by clearing the WREN bit or by setting the HALT bit in SPCR3 Exiting wraparound mode by clearing SPE is not recommended as clearing SPE may abort a serial transfer in progress The QSPI sets SPIF clears SPE and stops the first time it reaches the end of...

Page 500: ...red the QSPI stores the working queue pointer value in CPTQP increments the working queue pointer and loads new transmit data from transmit RAM into the data serializer The working queue pointer address is used the next time PCS 0 SS is asserted unless the RCPU writes to NEWQP first The QSPI shifts one bit for each pulse of SCK until the slave select input goes high If SS goes high before the numb...

Page 501: ...tore the incoming bit stream in sequential receive data segment addresses until either the value in BITS is reached or the end of queue address is used with wraparound mode disabled When the end of the queue is reached the SPIF flag is asserted optionally causing an interrupt If wraparound mode is disabled any additional incoming bits are ignored If wraparound mode is enabled storing continues at ...

Page 502: ... is toggled between serial transfers Receiving the proper number of bits caus es the received data to be stored The QSPI always transmits as many bits as it receives at each queue address until the BITS value is reached or PCS 0 SS is ne gated 14 7 7 Slave Wraparound Mode When the QSPI reaches the end of the queue it always sets the SPIF flag whether wraparound mode is enabled or disabled An optio...

Page 503: ...PE in SPCR1 is cleared dis abling the QSPI The QSPI pins revert to control by QPDR If MODF is set and HMIE in SPCR3 is asserted the QSPI generates an interrupt to the CPU The CPU may clear MODF by reading SPSR with MODF asserted followed by writing SPSR with a zero in MODF After correcting the mode fault problem the QSPI can be re enabled by asserting SPE The PCS 0 SS pin may be configured as a ge...

Page 504: ...D SCxDR Tx BUFFER TRANSFER Tx BUFFER SHIFT ENABLE JAM ENABLE PREAMBLE JAM 1 s BREAK JAM 0 s FORCE PIN DIRECTION OUT SIZE 8 9 PARITY GENERATOR TRANSMITTER BAUD RATE CLOCK TC TDRE SCI Rx REQUESTS SCI INTERRUPT REQUEST FE NF OR IDLE RDRF TC TDRE SCxSR STATUS REGISTER PF INTERNAL DATA BUS RAF TIE TCIE SCCxR1 CONTROL REGISTER 1 0 15 15 0 START STOP OPEN DRAIN OUTPUT MODE ENABLE WRITE ONLY Freescale Sem...

Page 505: ...1 0 15 FE NF OR IDLE RDRF TC TDRE SCxSR STATUS REGISTER PF RAF 15 0 WAKE UP LOGIC PIN BUFFER RxD STOP 8 7 6 5 4 3 2 1 0 10 11 BIT Rx SHIFT REGISTER START MSB ALL ONES DATA RECOVERY 16 PARITY DETECT RECEIVER BAUD RATE CLOCK SCxDR Rx BUFFER READ ONLY SCI Tx REQUESTS SCI INTERRUPT REQUEST INTERNAL DATA BUS L H Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product ...

Page 506: ... to initialize SCIx and enable the trans mitter and receiver Table 14 22 SCI Registers Address Name Usage 0x30 5008 SCC1R0 SCI1 Control Register 0 See Table 14 23 for bit descriptions 0x30 500A SCC1R1 SCI1 Control Register 1 See Table 14 24 for bit descriptions 0x30 500C SC1SR SCI1 Status Register See Table 14 25 for bit descriptions 0x30 500E non queue mode only SC1DR SCI1 Data Register Transmit ...

Page 507: ...cumstances Changing the value of SCCxR1 bits during a transfer operation can disrupt the trans fer Before changing register values allow the SCI to complete the current transfer then disable the receiver and transmitter SCCxR0 SCI Control Register 0 0x30 5008 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 OTHR LNK BD 0 SCxBR RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Table 14 23 SCCxR0 Bit Descriptions ...

Page 508: ... Parity Checking 0 SCI parity disabled 1 SCI parity enabled 6 M Mode select Refer to 14 8 7 2 Serial Formats 0 10 bit SCI frame 1 11 bit SCI frame 7 WAKE Wakeup by address mark Refer to 14 8 7 9 Receiver Wake Up 0 SCI receiver awakened by idle line detection 1 SCI receiver awakened by address mark last bit set 8 TIE Transmit interrupt enable 0 SCI TDRE interrupts disabled 1 SCI TDRE interrupts ena...

Page 509: ...ignal for setting a status bit comes after the CPU has read the as serted status bits but before the CPU has read or written the SCxDR the newly set status bit is not cleared Instead SCxSR must be read again with the bit set and SCxDR must be read or written before the status bit is cleared NOTE None of the status bits are cleared by reading a status bit while it is set and then writing zero to th...

Page 510: ...t bit and is cleared when the chosen type of idle line is detected RAF can be used to reduce collisions in systems with multiple masters 0 SCI receiver is idle 1 SCI receiver is busy 11 IDLE Idle line detected IDLE is set when the receiver detects an idle line condition reception of a min imum of 10 or 11 consecutive ones as specified by ILT in SCCxR1 This bit is not set by the idle line condition...

Page 511: ...ata 1 Noise detected in the received data For receiver queue operation NF is cleared when SCxSR is read with NF set followed by a read of SCRQ 0 15 14 FE Framing error FE is set when the receiver detects a zero where a stop bit one was expected A framing error results when the frame boundaries in the received bit stream are not synchro nized with the receiver bit counter FE is not set until the en...

Page 512: ... The SCI can use 10 bit or 11 bit frames Data frame A start bit a specified number of data or information bits and at least one stop bit Idle frame A frame that consists of consecutive ones An idle frame has no start bit Table 14 26 SCxSR Bit Descriptions Bit s Name Description 0 6 Reserved 7 15 R 8 0 T 8 0 R 7 0 T 7 0 contain either the eight data bits received when SCxDR is read or the eight dat...

Page 513: ...11 bit data frame contains one start bit eight data bits a parity or control bit and one stop bit Ten bit and 11 bit frames are shown in Table 14 28 14 8 7 3 Baud Clock The SCI baud rate is programmed by writing a 13 bit value to the SCxBR field in SCI control register zero SCCxR0 The baud rate is derived from the MCU IMB clock by a modulus counter Writing a value of zero to SCxBR 12 0 disables th...

Page 514: ...s the number of data bits in a frame which can in turn affect frame size Table 14 24 shows possible data and parity formats 14 8 7 5 Transmitter Operation The transmitter consists of a serial shifter and a parallel data register TDRx located in the SCI data register SCxDR The serial shifter cannot be directly accessed by the CPU The transmitter is double buffered which means that data can be loade...

Page 515: ...a frame If TC 0 the current opera tion continues until the final bit in the frame is sent then the preamble is transmitted The TC bit is set at the end of preamble transmission The SBK bit in SCCxR1 is used to insert break frames in a transmission A non zero integer number of break frames are transmitted while SBK is set Break transmission begins when SBK is set and ends with the transmission in p...

Page 516: ... the transmit data line TXDx pin marks idle logic one until TDRx is written In addition if the last data frame of the first message finishes shifting out including the stop bit and TE is clear TC goes high and transmission is considered complete The TXDx pin reverts to being a general purpose output pin 14 8 7 6 Receiver Operation The receiver can be divided into two segments The first is the rece...

Page 517: ...ro transition or each RT16 The beginning of a bit time is thus defined as RT1 and the end of a bit time as RT16 Upon detection of a valid start bit synchronization is established and is maintained through the reception of the last stop bit after which the procedure starts all over again to search for a new valid start bit During a frame s reception SCIx resynchronizes the RT clock on any one to ze...

Page 518: ...ailed in the Queued Serial Module Reference Manual QSMRM AD The number of bits shifted in by the receiver depends on the serial format However all frames must end with at least one stop bit When the stop bit is received the frame is considered to be complete and the received data in the serial shifter is transferred to the RDRx The receiver data register flag RDRF is set when the data is trans fer...

Page 519: ...me are logic ones the start bit provides one logic zero bit time during the frame An idle line is a sequence of contiguous ones equal to the current frame size Frame size is determined by the state of the M bit in SCCxR1 The SCI receiver has both short and long idle line detection capability Idle line detec tion is always enabled The idle line type ILT bit in SCCxR1 determines which type of detect...

Page 520: ...here must be no idle time between frames within a transmission Address mark wake up uses a special frame format to wake up the receiver When the MSB of an address mark frame is set that frame contains address information The first frame of each transmission must be an address frame When the MSB of a frame is set the receiver clears RWU and wakes up The data frame is received normally transferred t...

Page 521: ...queue uses the following registers QSCI1 control register QSCI1CR address offset 0x28 QSCI1 status register QSCI1SR address offset 0x2A 14 9 2 1 QSCI1 Control Register QSCI1CR QSCI1 Control Register 0x30 5028 MSB LSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 QTPNT QTH FI QBH FI QTHE I QB HEI 0 QTE QRE QTW E QTSZ RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Freescale Semiconductor I Freescale Semiconductor In...

Page 522: ... set The interrupt is blocked by negating QBHEI This bit refers to the queue locations SCTQ 8 15 0 QBHE interrupt inhibited 1 Queue bottom half empty QBHE interrupt enabled 8 Reserved 9 QTE Queue transmit enable When set the transmit queue is enabled and the TDRE bit should be ignored by software The TC bit is redefined to indicate when the entire queue is finished trans mitting When clear the SCI...

Page 523: ...F Receiver queue bottom half full QBHF is set when the receive queue locations SCRQ 8 15 are completely filled with new data received via the serial shifter QBHF is cleared when register QSCI1SR is read with QBHF set followed by a write of QBHF to zero 0 The queue locations SCRQ 8 15 are partially filled with newly received data or is empty 1 The queue locations SCRQ 8 15 are completely full of ne...

Page 524: ... as previously defined Locations SCTQ 0 15 can be used as general pur pose 9 bit registers All other bits pertaining to the queue should be ignored by software Programmable queue up to 16 transmits SCTQ 0 15 which may allow for infi nite and continuous transmits Available transmit wrap function to prevent message breaks for transmits greater 10 11 BIT Tx Shift Register STOP START H 8 7 6 5 4 3 2 1...

Page 525: ...d by a write of QBHE to zero In order to implement the transmit queue QTE must be set QSCI1CR TE must be set SCC1R1 QTHE must be cleared QSCI1SR and TDRE must be set SC1SR Enable and disable options for the interrupts QTHE and QBHE as controlled by QTHEI and QBHEI respectfully Programmable 4 bit register queue transmit size QTSZ for configuring the queue to any size up to 16 transfers at a time Th...

Page 526: ...ent QTPNT QTPNT 1000 QBHE 0 Reset QTPNT to 0000 Write QTSZ n Clear QTHE TC Write SCTQ 0 n Set TE QTE 1 TE 1 No Yes TDRE 1 QTHE 0 Refers to Action Performed in Parallel QTE TE 1 No Yes QTPNT 1111 QTWE 1 Set QTHE QBHE Clear QTE no Set QTHE Set QBHE no yes No Yes Yes Yes Write QTSZ for Wrap Clear QTHE Possible Set of QTWE Clear QBHE Clear QTWE TE 0 TC 1 TDRE 1 QTE 0 QTPNT 0 QTWE 0 QTHEI 0 QTHE 1 QBHE...

Page 527: ...ed Transmitting Then Clear QTE and or TE If Finished Transmitting Then Clear QTE and or TE DONE DONE Read Status Register with TC 1 Write SCTQ 0 n Clears TC Read Status Register with QTHE 1 Write QTHE 0 and QBHE if Transmitting More than 8 Data Must Have Equaled 16 Read QTHE 1 Write QTHE 0 Write New Data SCTQ 0 7 To Wrap Write New QTSZ n Set QTWE Previous QTSZ If Transmitting Greater Than 8 Data F...

Page 528: ...11 QTPNT QPEND 1111 1000 0111 0000 QTSZ 1111 16 Data Frames SCTQ 0 SCTQ 7 SCTQ 8 SCTQ 15 Write New QTSZ for When Wrap Occurs QTSZ 0 16 1 17 Set QTWE Clear QTHE Write SCTQ 0 for 17th Transfer 0000 0111 1000 1111 QTPNT QPEND 0000 QTSZ 0000 1 Data Frame SCTQ 0 SCTQ 7 SCTQ 8 SCTQ 15 Load QPEND with QTSZ 0 Reset QTPNT 0000 0111 1000 1111 QTPNT QPEND 1111 1000 0111 0000 QTSZ 1111 16 Data Frames SCTQ 0 S...

Page 529: ...Q 15 0000 0111 1000 1111 QTPNT QPEND 1111 1000 0111 0000 QTSZ 1111 16 Data Frames SCTQ 0 SCTQ 7 SCTQ 8 SCTQ 15 0001 0000 0111 1000 1111 QTPNT QPEND 1000 QTSZ 1000 9 Data Frames SCTQ 0 SCTQ 7 SCTQ 8 SCTQ 15 0000 0000 0001 Data to be Transferred Available Register Space 1001 1111 QTHE Interrupt Received Write QTSZ 8 16 9 25 Write SCTQ 0 7 for 8 More Data Frames Set QTWE Clear QTHE Load QPEND with QT...

Page 530: ...ware When the queue is enabled software should ig nore the RDRF bit When the queue is disabled QRE 0 the SCI functions in single buffer receive mode as originally designed and RDRF and OR function as previously defined RxD Receiver Baud Rate Clock 10 11 BIT Rx Shift Register STOP START H 8 7 6 5 4 3 2 1 0 L SCRQ 0 SCRQ 1 SCRQ 15 16 1 Mux 4 bits QRE QTHFI QBHFI Queue Control QRPNT 0 3 QTHF QBHF Que...

Page 531: ...ble options for the interrupts QTHF and QBHF as controlled by the QTHFI and QBHFI respectfully 4 bit counter QRPNT is used as a pointer to indicate where the next valid data frame will be stored A queue overrun error flag QOR to indicate when the queue is already full when another data frame is ready to be stored into the queue similar to the OR bit in single buffer mode The QOR bit can be set for...

Page 532: ...fore OR SC1SR is set which occurs when a new data frame is re ceived in the shifter but the data register SC1DR is still full The data in the shifter that generated the OR assertion is overwritten by the next received data frame but the data in the SC1DR is not lost Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 533: ...ardware Software Refers to Action Performed In Parallel QTHF 1 QBHF 1 QTHFI 0 QBHFI 0 No Yes Set QTHFI QBHFI Clear QTHF QBHF Set RE Reset Increment QRPNT QRE RE 1 No Yes QRE RE 1 QTHF QOR 0 FE PE OR 0 QRPNT 8 QBHF QRPNT 0 QTHF FE PE 0 QRPNT 1000 Reset QRPNT to 0000 RDRF 1 Clear QRE Set QTHF Set QBHF Yes No No Set QOR Clear QTHF Clear QBHF Yes Yes No No Yes Freescale Semiconductor I Freescale Semic...

Page 534: ...egister With QBHF 1 Read SCRQ 8 15 Read Status Register With QTHFI QBHFI 1 Set QRE and RE 1 QTHF 1 Read SCRQ 0 7 Read Status Register with QTHF QBHF 1 Write QTHF QBHF 0 FunctionCan Be Used To Indicate When a Group Of Serial Transmissions Is Finished Enable ILIE 1 to Detect An Idle Line IDLE 1 Yes No Clear QRE and or RE To Exit the Queue DONE Write QTHF 0 Write QBHF 0 Freescale Semiconductor I Free...

Page 535: ... 14 23 Queue Receive Example for 17 Data Bytes 0000 0111 1000 1111 QRPNT SCRQ 0 SCRQ 7 SCRQ 8 SCRQ 15 0000 0111 1000 1111 QRPNT SCRQ 0 SCRQ 7 SCRQ 8 SCRQ 15 Read SCSR and SCRQ 0 7 Clear QTHF 0000 0111 1000 1111 QRPNT SCRQ 0 SCRQ 7 SCRQ 8 0000 0111 1000 1111 QRPNT SCRQ 0 SCRQ 7 0001 Data Available Received Space QTHF Interrupt Received SCRQ 15 Read SCRQ 8 15 Clear QBHF QBHF Interrupt Received SCRQ ...

Page 536: ...MPC556 QUEUED SERIAL MULTI CHANNEL MODULE MOTOROLA USER S MANUAL Rev 15 October 2000 14 74 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 537: ...the silicon implementation level Disable capability in each submodule to allow power saving when its function is not needed Two 16 bit buses to allow action submodules to use counter data When not used for timing functions every channel pin can be used as a port pin I O output only or input only depending on the channel function Submodules pin status bits MIOS counter prescaler submodule MCPSM Cen...

Page 538: ...IOS pulse width modulation submodules MPWMSM each with these features Output pulse width modulated PWM signal generation with no software in volvement Built in 8 bit programmable prescaler clocked by the MCPSM PWM period and pulse width values provided by software Double buffered for glitch free period and pulse width changes 2 cycle minimum output period pulse width increment 50 ns at fSYS 40 MHz...

Page 539: ...nd the MCPSM are unique in the MIOS1 and do not need a number The MIRSMs are numbered incrementally starting from zero The MIOS1 base address is defined at the chip level and is referred to as the MIOS1 base address The MIOS1 addressable range is four Kbytes The base address of a given implemented submodule within the MIOS1 is the sum of the base address of the MIOS1 and the submodule number multi...

Page 540: ...ne For example a MDASM placed as submodule number n would have its corre sponding channel I O pin named MDAn MPWMSM submodule short_prefix PWM pin attribute suffix none For example a MPWMSM placed as submodule number n would have its cor responding channel I O pin named MPWMn MPIOSM submodule short_prefix PIO pin attribute suffix B For example a MPIOSM placed as submodule number n would have its c...

Page 541: ...SM32 MPWM19 PWM MPWMSM19 MPWM16 PWM MPWMSM16 MDA31 Double Action MDASM31 MDA27 Double Action MDASM27 5xDASM Modulus Counter MMCSM22 C L To all Submodules MDA14 MDA13 MDA12 MDA11 Submodules Interrupt MPWM3 PWM MPWMSM3 MPWM0 PWM MPWMSM0 MDA15 Double Action MDASM15 MDA11 Double Action MDASM11 5xDASM Channel and I O Pins 34 Pins 4xPWMSM 4xPWMSM MCPSM IMB3 IMB3 Clock FSYS Counter Clock Freescale Semico...

Page 542: ...ith I O submodule identification and priority information to the MBISM Note that some submodules do not generate interrupts and are therefore independent of the RQB 15 5 3 Counter Bus Set The 16 bit counter bus set CBS is a set of two 16 bit counter buses The CBS makes it possible to transfer information between submodules Typically counter submod ules drive the CBS while action submodules process...

Page 543: ...0 6C40 MPWMSM0 MPWMSM1 MPWMSM2 MPWMSM3 0x30 6000 0x30 6008 0x30 6010 0x30 6018 Reserved MMCSM6 Reserved MDASM11 0x30 6030 0x30 6058 MDASM12 MDASM13 MDASM14 MDASM15 0x30 6060 0x30 6068 0x30 6070 0x30 6078 MPWMSM16 MPWMSM17 MPWMSM18 MPWMSM19 0x30 6088 0x30 6098 0x30 6080 0x30 6090 Reserved MMCSM22 Reserved MDASM27 0x30 60B0 0x30 60D8 MDASM28 MDASM29 MDASM30 0x30 60E8 0x30 60F8 MDASM31 MPIOSM32 0x30 ...

Page 544: ...les 15 8 1 MIOS Bus Interface MBISM Registers Table 15 2 is the address map for the MBISM submodule 15 8 1 1 MIOS1 Test and Pin Control Register Table 15 1 MIOS1 I O Ports Submodule Number Type MPIOSM 16 I O MMCSM 2 I MDASM 1 I O MPWMSM 1 I O Table 15 2 MBISM Address Map Address Register 0x30 6800 MIOS1 Test and Pin Control Register MIOS1TPCR See Table 15 3 for bit descriptions 0x30 6802 Reserved ...

Page 545: ...pins Refer to the pad ring specification of the chip for details about the usage of this bit This bit is set to 0 by reset 0 the concerned pins are dedicated to the MIOS1 1 alternate function 15 VFLS Pin multiplex This bit is used to determine the usage of the MIOS1 pins Refer to the pad ring specification of the chip for details about the usage of this bit This bit is set to 0 by reset 0 the conc...

Page 546: ...s written to zero or the IMB3 FREEZE signal is negated The FRZ bit is cleared by reset 0 Ignores the FREEZE signal on the IMB3 allowing MIOS1 operation 1 Selectively stops MIOS1 operation when the FREEZE signal appears on the IMB3 3 RST Module reset The RST bit always returns 0 when read and can be written to 1 When the RST bit is written to 1 the MBISM activates the reset signal on the MIOB This ...

Page 547: ...its in this register three bits repre sent one of eight levels and the two other represent the four time multiplex slots Ac MIOS1LVL0 MIOS1 Interrupt Level Register 0 0x30 6C30 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 RESERVED LVL TM RESERVED RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 15 7 MIOS1LVL0 Bit Descriptions Bit s Name Description 0 4 Reserved 5 7 LVL Interrupt request level This fie...

Page 548: ... counter clock It is designed to provide all the submodules with the same division of the main MIOS1 clock division of FSYS It uses a 4 bit modulus counter The clock signal is prescaled by loading the value of the clock prescaler register into the prescaler counter every time it overflows This allows all prescaling factors be tween two and 16 Counting is enabled by asserting the PREN bit in the co...

Page 549: ...e high read write control bit enables the MCPSM counter The PREN bit is cleared by reset 0 MCPSM counter disabled 1 MCPSM counter enabled 1 FREN Freeze enable This active high read write control bit when set make possible a freeze of the MCPSM counter if the MIOB freeze line is activated Note that this line is active when the MIOS1MCR STOP bit is set or when the MIOS1MCR FREN bit and the IMB3 FREE...

Page 550: ...ions 1 When an overflow occurs 2 When an appropriate transition occurs on the external load pin 3 When the program writes to the counter register In this case the value is first written into the modulus register and immediately transferred to the counter Software can also write a value to the modulus register for later loading into the counter with one of the two first criteria A software control ...

Page 551: ...ol Register Duplicated for bit descriptions 0x30 6036 MMCSM6 Status Control Register MMCSMSCR MMCSM22 0x30 60B0 MMCSM Up Counter Register MMCSMCNT 0x30 60B2 MMCSM Modulus Latch Register MMCSMML 0x30 60B4 MMCSM Status Control Register Duplicated MMCSMSCRD 0x30 60B6 MMCSM Status Control Register MMCSMSCR 16 bit Up Counter Register Edge 16 bit Counter Bus Clock input pin Overflow MIOB Detect Load Con...

Page 552: ...0 6030 0x30 60B0 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 CNT RESET U U U U U U U U U U U U U U U U Table 15 12 MMCSMCNT Bit Descriptions Bit s Name Description 0 15 CNT Counter value These read write data bits represent the 16 bit value of the up counter CNT con tains the value that is driven onto the 16 bit counter bus MMCSMML MMCSM Modulus Latch Register 0x30 6032 0x30 60B2 MSB 0 1 2 3 4 5...

Page 553: ...d write control bit enables the MMCSM to recognize the MIOB freeze signal 3 4 EDGN EDGP Modulus load falling edge rising edge sensitivity These active high read write control bits set falling edge and rising edge sensitivity respectively for the MMCnL pin MDA12 or MDA14 00 Disabled 01 MMCSMCNT load on rising edges 10 MMCSMCNT load on falling edges 11 MMCSMCNT load on rising and falling edges 5 6 C...

Page 554: ...ut put compare The MDASM has six different software selectable modes Disable mode Pulse width measurement Period measurement Input capture mode Single pulse generation Continuous pulse generation The MDASM has three data registers that are accessible to the software from the var ious modes For some of the modes two of the registers are cascaded together to pro vide double buffering The value in on...

Page 555: ...submodule is shown in the table below 16 bit Comparator A 4 X 16 bit Counter Bus Control Register Bits MIOB Select Output Flip Flop I O Pin Edge Detect Output Buffer CBn 3 CBn 2 16 bit Comparator B EDPOL CBn CBn 1 BSL1 BSL0 FORCA FORCB FLAG MODE3 MODE2 MODE1 MODE0 WOR PIN Counter Buses Request Bus 16 bit Register B2 Register B 16 bit Register B1 16 bit Register A Freescale Semiconductor I Freescal...

Page 556: ...C MDASM13 Status Control Register Duplicated MDASMSCRD 0x30 606E MDASM13 Status Control Register MDASMSCR MDASM14 0x30 6070 MDASM14 Data A Register MDASMAR 0x30 6072 MDASM14 Data B Register MDASMBR 0x30 6074 MDASM14 Status Control Register Duplicated MDASMSCRD 0x30 6076 MDASM14 Status Control Register MDASMSCR MDASM15 0x30 6078 MDASM15 Data A Register MDASMAR 0x30 607A MDASM15 Data B Register MDAS...

Page 557: ...15 16 for a complete list of all the base addresses for the MDASM registers 15 11 1 2 MDASM Data B Register MDASMBR MDASMBR is the data register associated with channel B Its use varies with the mode of operation Depending on the mode selected software access is to register B1 or register B2 0x30 60EA MDASM29 Data B Register MDASMBR 0x30 60EC MDASM29 Status Control Register Duplicated MDASMSCRD 0x...

Page 558: ...r register B1 is hidden and cannot be accessed In the OPWM mode MDASMBR is loaded with the value corresponding to the trailing edge of the PWM pulse to be generated In this mode register B1 is ac cessed buffer register B2 is hidden and cannot be accessed Refer to Table 15 16 for a complete list of all the base addresses for the MDASM registers 15 11 1 3 MDASM Status Control Register Duplicated The...

Page 559: ... is not used reading it returns the last value written In the IPWM mode this bit is used to select the capture edge sensitivity of channels A and B 0 Channel A captures on a rising edge Channel B captures on a falling edge 1 Channel A captures on a falling edge Channel B captures on a rising edge In the IPM and IC modes the EDPOL bit is used to select the input capture edge sensitivity of channel ...

Page 560: ... the mode of operation of the MDASM To avoid spurious interrupts it is recommended that MDASM interrupts are disabled before changing the operating mode It is also imperative to go through the disable mode before changing the oper ating mode See Table 15 18 for details Table 15 18 MDASM Mode Selects MDASM Control Register Bits Bits of Resolution Counter Bus Bits Ignored MDASM Mode of Operation MOD...

Page 561: ... to divide by 4096 the period of the PWM output can range from 3 28 ms to 6 7 s assum ing a fSYS of 40 MHz By reducing the counting value the output signal period can be reduced The period can be as fast as 205 µs 4 882 KHz with twelve bits of resolu tion as fast as 12 8 µs 78 125 KHz with eight bits of resolution and as fast as 3 2 µs 312 500 KHz with six bits of resolution still assuming a fSYS ...

Page 562: ...SM2 Period Register MPWMSMPERR 0x30 6012 MPWMSM2 Pulse Register MPWMSMPULR 0x30 6014 MPWMSM2 Count Register MPWMSMCNTR 0x30 6016 MPWMSM2 Status Control Register MPWMSMSCR MPWMSM3 0x30 6018 MPWMSM3 Period Register MPWMSMPERR 0x30 601A MPWMSM3 Pulse Register MPWMSMPULR 0x30 601C MPWMSM3 Count Register MPWMSMCNTR 0x30 601E MPWMSM3 Status Control Register MPWMSMSCR MPWMSM16 0x30 6080 MPWMSM16 Period R...

Page 563: ...09C MPWMSM19 Count Register MPWMSMCNTR 0x30 609E MPWMSM19 Status Control Register MPWMSMSCR MPWMSMPERR MPWMSM Period Register 0x30 6000 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 PER RESET U U U U U U U U U U U U U U U U Table 15 20 MPWMSMPERR Bit Descriptions Bit s Name Description 0 15 PER Period These bits contain the binary value corresponding to the period to be generated MPWMSMPULR MPWMSM...

Page 564: ... read write control bits Refer to Table 15 19 for a complete list of all the base addresses for the MPWMSM registers MPWMSMCNTR MPWMSM Counter Register 0x30 6004 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 CNT RESET U U U U U U U U U U U U U U U U Table 15 22 MPWMSMCNTR Bit Descriptions Bit s Name Description 0 15 CNT Counter These bits reflect the actual value of the MPWMSM counter MPWMSMSCR MP...

Page 565: ...mode activated 4 POL Output polarity control The POL bit works in conjunction with the EN bit and controls whether the MPWMSM drives the pin with the true or the inverted value of the output flip flop Table 15 24 lists the different uses for the polarity POL bit the enable EN bit and the data direction register DDR bit 5 EN Enable PWM signal generation The EN bit defines whether the MPWMSM generat...

Page 566: ...I O pin implementation 15 13 1 MIOS 16 bit Parallel Port I O Submodule MPIOSM Registers One set of registers is associated with the MPIOSM submodule The base addresses of the submodules are given in the table below 15 13 1 1 MPIOSM Data Register MPIOSMDR This read write register defines the value to be driven to the pad in output mode for each implemented I O pin of the MPIOSM Table 15 25 MPIOSM A...

Page 567: ...D0 RESET U U U U U U U U U U U U U U U U Table 15 26 MPIOSMDR Bit Descriptions Bit s Name Description 0 15 D 15 0 Data BITS These bits are read write data bits that define the value to be driven to the pad in output mode for each implemented I O pin of the MPIOSM While in output mode a read returns the value of the pad Note that when little endian bit ordering is used bit 0 corresponds to D15 and ...

Page 568: ... Figure 15 8 MIOS Interrupt Structure 15 14 1 MIOS Interrupt Request Submodule MIRSM Each submodule that is capable of generating an interrupt can assert a flag line when an event occurs In the MIOS1 configuration there are eighteen flag lines and two MIRSMs are needed Submodule 13 IMB3 MBISM Status Register Enable Register IRQ Pend Register RQSM 0 Interrupt Control Section Level n Flags RQSM 1 Su...

Page 569: ...ters If a flag bit is set and the level enable bit is also set then the IRQ pending bit is set and the information is transferred to the interrupt control section that is in charge of sending the corresponding level to the CPU The IRQ pending register is read only NOTE When the enable bit is not set for a particular submodule the corre sponding status register bit is still set when the correspondi...

Page 570: ...ap Address Register 0x30 6C00 MIRSM0 Interrupt Status Register MIOS1SR0 See Table 15 29 for bit descriptions 0x30 6C02 Reserved 0x30 6C04 MIRSM0 Interrupt Enable Register MIOS1ER0 See Table 15 30 for bit descriptions 0x30 6C06 MIRSM0 Request Pending Register MIOS1RPR0 See Table 15 31 for bit descriptions MIOS1SR0 RQSM0 Interrupt Status Register 0x30 6C00 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB ...

Page 571: ...EN6 RESERVED EN3 EN2 EN1 EN0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 15 30 MIOS1ER0 Bit Descriptions Bit s Name Description 0 EN15 MDASM15 interrupt enable bit 1 EN14 MDASM14 interrupt enable bit 2 EN13 MDASM13 interrupt enable bit 3 EN12 MDASM12 interrupt enable bit 4 EN11 MDASM11 interrupt enable bit 5 8 Reserved 9 EN6 MMCSM6 interrupt enable bit 10 11 Reserved 12 EN3 MPWMSM3 interrupt enabl...

Page 572: ...g bit 5 8 Reserved 9 IRP6 MMCSM6 IRQ pending bit 10 11 Reserved 12 IRP3 MPWMSM3 IRQ pending bit 13 IRP2 MPWMSM2 IRQ pending bit 14 IRP1 MPWMSM1 IRQ pending bit 15 IRP0 MPWMSM0 IRQ pending bit Table 15 32 MIRSM1 Address Map Address Register 0x30 6C40 MIRSM1 Interrupt Status Register MIOS1SR1 See Table 15 33 for bit descriptions 0x30 6C42 Reserved 0x30 6C44 MIRSM1 Interrupt Enable Register MIOS1ER1 ...

Page 573: ...2 MMCSM22 flag bit 10 11 Reserved 12 FLG19 MPWMSM19 flag bit 13 FLG18 MPWMSM18 flag bit 14 FLG17 MPWMSM17 flag bit 15 FLG16 MPWMSM16 flag bit MIOS1ER1 Interrupt Enable Register 0x30 6C44 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 EN31 EN30 EN129 EN28 EN27 RESERVED EN22 RESERVED EN19 EN18 EN17 EN16 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 15 34 MIOS1ER1 Bit Descriptions Bit s Name Description...

Page 574: ...SM has two capture registers so that only one interrupt is needed after the second edge The software can read both edge samples and subtract them to get the pulse width The leading edge sample is double latched so that the software has the time of one full period of the input signal to read the samples to be sure that nothing is lost De pending on the prescaler divide ratio pulse width from 50 ns ...

Page 575: ...pulse After the trailing edge the software has one cycle time of the input signal to obtain the values for each edge When software attention is not needed for every pulse the interrupt can be disabled The software can read registers A and B2 coher ently using a 32 bit read instruction at any time to get the latest edge measurements The software work is less than half that needed with a timer that ...

Page 576: ...g or falling edge of the input signal is to be used for the measurements When the edge is detected the state of the 16 bit counter bus is stored in register A and the content of register B1 is transferred to register B2 After register B2 is safely latched the content of register A is transferred to register B1 This procedure gives the software coherent current and previous samples in registers A a...

Page 577: ...re value for one edge in register A and the other one in register B2 The MDASM automatically creates both edges and the pulse can be selected by software to be a high going or a low go ing After the trailing edge the MDASM stops to await further commands from the soft ware Note that a single edge output can be generated by writing to only one register Figure 15 11 MIOS1 Example Double Edge Output ...

Page 578: ... course the special case where the high and low times are equal When an MMCSM is used to drive the time base the modulus value is the period of the output PWM signal Figure 15 12 shows such an example The polarity of the leading edge of an output waveform is programmable for a rising or a falling edge The software selects the period of the output signal by programming the MMCSM with a modulus valu...

Page 579: ...be created when the pulse accumulation reaches a preprogrammed value To do that the two s complement of the value is put in the modulus register and the interrupt occurs when the counter overflows 15 16 MIOS1 Configuration The complete MIOS1 submodule and pin configuration is shown in Table 15 36 16 bit Up Counter Submodule Bus 16 bit Compare B Output Flip Flop Output Pin 16 bit Compare A 16 bit R...

Page 580: ... 15 CB6 CB22 0 15 0x30 6078 Channel I O MDA15 MDA15 MPWMSM 16 1 0 0x30 6080 PWM I O MPWM16 MPWM16 MPWMSM 17 1 1 0x30 6088 PWM I O MPWM17 MPWM17 MPWMSM 18 1 2 0x30 6090 PWM I O MPWM18 MPWM18 MPWMSM 19 1 3 0x30 6098 PWM I O MPWM19 MPWM19 Reserved 20 21 MMCSM 22 CB22 1 6 0x30 60B0 Clock In MDA13 Load In MDA14 Reserved 23 26 MDASM 27 CB6 CB22 1 11 0x30 60D8 Channel I O MDA27 MDA27 MDASM 28 CB6 CB22 1 ...

Page 581: ...0 Reserved 257 MCPSM 258 0x30 6810 Reserved 259 RQSM0 384 391 0x30 6C00 RQSM1 392 399 0x30 6C40 Reserved 400 511 NOTES 1 GP General purpose Table 15 36 MIOS1 Configuration Continued Submodule type Submodule Number connected to RQSM Number RQSM Bit Position Base Address Pin Function Input Pin Name Output Pin Name Alternate Pin Function CBA CBB CBC CBD BSL 00 BSL 01 BSL 10 BSL 11 Freescale Semicondu...

Page 582: ...PC556 MODULAR INPUT OUTPUT SUBSYSTEM MIOS1 MOTOROLA USER S MANUAL Rev 15 October 2000 15 46 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 583: ...ied in the CAN protocol specification revision 2 0 part B Each TouCAN module contains 16 message buffers which are used for transmit and receive functions It also contains message filters which are used to qualify the re ceived message IDs when comparing them to the receive buffer identifiers Figure 16 1 shows a block diagram of a TouCAN module Figure 16 1 TouCAN Block Diagram 16 1 Features Each T...

Page 584: ...medium external transceiver is assumed Open network architecture Multimaster concept High immunity to EMI Short latency time for high priority messages Low power sleep mode with programmable wakeup on bus activity Outputs have open drain drivers Can be used to implement recommended practices SAE J1939 and SAE J2284 Can also be used to implement popular industrial automation standards such as Devic...

Page 585: ...age buffers to be designated either a transmit Tx buffer or a receive Rx buffer In addition to reduce the CPU overhead required for message handling each message buffer is as signed an interrupt flag bit to indicate that the transmission or reception completed successfully 16 3 1 TX RX Message Buffer Structure Figure 16 3 displays the extended 29 bit ID message buffer structure Figure 16 4 display...

Page 586: ... RTR ID_LOW 0x6 DATA BYTE 0 DATA BYTE 1 0x8 DATA BYTE 2 DATA BYTE 3 0xA DATA BYTE 4 DATA BYTE 5 0xC DATA BYTE 6 DATA BYTE 7 0xE RESERVED1 NOTES 1 The reading of a reserved location in memory may cause an RCPU exception MSB 0 8 LSB 12 0x0 TIME STAMP CODE LENGTH CONTROL STATUS 0x2 ID 28 18 RTR 0 0 0 0 ID_HIGH 0x4 16 BIT TIME STAMP ID_LOW 0x6 DATA BYTE 0 DATA BYTE 1 0x8 DATA BYTE 2 DATA BYTE 3 0xA DA...

Page 587: ...ion Rx Code Af ter Rx New Frame Comment 0b0000 NOT ACTIVE message buffer is not active 0b0100 EMPTY message buffer is active and empty 0b0010 0b0010 FULL message buffer is full 0b0110 If a CPU read occurs before the new frame new receive code is 0010 0b0110 OVERRUN second frame was received into a full buffer before the CPU read the first one 0b0XY11 NOTES 1 For Tx message buffers upon read the BU...

Page 588: ...ld be set to one If zero standard format frame should be used ID 14 0 Bits 14 0 of the extended identifier located in the ID LOW word of the message buffer Remote Transmission Request RTR This bit is located in the least significant bit of the ID LOW word of the message buffer 0 Data Frame 1 Remote Frame Table 16 5 Standard Format Frames Field Description 16 bit Time Stamp The ID LOW word which is...

Page 589: ...frame transfers within the TouCAN Reading the control status word of a receive message buffer triggers the lock for that buffer While locked a received message cannot be transferred into that buffer from one of the serial message buffers If a message transfer between the message buffer and a serial message buffer is in progress when the control status word is read the BUSY status is indicated in t...

Page 590: ...match exists Table 16 7 Mask Examples for Normal Extended Messages Message Buffer MB Mask Base ID ID 28 18 IDE Extended ID ID 17 0 Match MB2 1 1 1 1 1 1 1 1 0 0 0 0 MB3 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MB4 0 0 0 0 0 0 1 1 1 1 1 0 MB5 0 0 0 0 0 0 1 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MB14 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RX Global Mask...

Page 591: ... another node occurs during the third bit of the intermission between messag es the TouCAN may not be able to prepare a message buffer for transmission in time to begin its own transmission and arbitrate against the message which trans mitted the early SOF The TouCAN bit time must be programmed to be greater than or equal to nine IMB clocks or correct operation is not guaranteed 16 3 4 Error Count...

Page 592: ... the Tx error counter is reset to zero If the TouCAN is in the bus off state the Tx error counter and an additional inter nal counter are cascaded to count 128 occurrences of 11 consecutive recessive bits on the bus To do this the Tx error counter is first reset to zero and then the internal counter begins counting consecutive recessive bits Each time the inter nal counter counts 11 consecutive re...

Page 593: ... configuration register are set In this state the TouCAN does not initiate frame transmissions or receive any frames from the CAN bus The contents of the message buffers are not changed following re set Any configuration change or initialization requires that the TouCAN be frozen by either the assertion of the HALT bit in the module configuration register or by reset 16 4 2 TouCAN Initialization I...

Page 594: ...f a message buffer for transmission as well as the internal steps performed by the TouCAN to decide which message to trans mit For the user this involves loading the message and ID to be transmitted into a message buffer and then activating that buffer as an active transmit buffer Once this is done the TouCAN performs all additional steps necessary to transmit the message onto the CAN bus The user...

Page 595: ... If the user deactivates the transmit message buffer after the message is transferred to the serial message buffer the message is transmitted but no interrupt is requested and the transmit code is not updated If a message buffer containing the lowest ID is deactivated while that message is un dergoing the internal arbitration process to determine which message should be sent then that message may ...

Page 596: ...s starts for another message buffer Only a single message buffer is locked at a time When a received message is read the only mandatory read operation is that of the control status word This ensures data coherency If the BUSY bit is set in the message buffer code the CPU should defer accessing that buffer until this bit is negated Refer to Table 16 2 NOTE The user should check the status of a mess...

Page 597: ... IDs are received while a message buffer with a matching ID is locked the last received frame with that ID is kept within the serial message buffer while all preceding ones are lost There is no indication when this occurs 6 If the user reads the control status word of a receive message buffer while a frame is being transferred from a serial message buffer the BUSY code is indi cated The user shoul...

Page 598: ...ield in receive frames A dominant bit in the eighth last bit of the error frame delimiter or overload frame delimiter 16 5 Special Operating Modes The TouCAN module has three special operating modes Debug mode Low power stop mode Auto power save mode 16 5 1 Debug Mode Debug mode is entered when the FRZ1 bit in CANMCR is set and one of the following events occurs The HALT bit in the CANMCR is set o...

Page 599: ...odule configuration register are set To exit low power stop mode Reset the TouCAN either by asserting one of the IMB3 reset lines or by asserting the SOFTRST bit CANMCR Clear the STOP bit in CANMCR The TouCAN module can optionally exit low power stop mode via the self wake mechanism If the SELFWAKE bit in CANMCR was set at the time the TouCAN entered stop mode then upon detection of a recessive to...

Page 600: ...in low power stop mode with the self wake mechanism engaged and is operating with a single IMB clock per time quantum there can be extreme cases in which TouCAN wake up on recessive to dominant edge may not con form to the CAN protocol TouCAN synchronization is shifted one time quantum from the wake up event This shift lasts until the next recessive to dominant edge which resynchronizes the TouCAN...

Page 601: ...egis ter Refer to 16 7 Programmer s Model for more information on these registers The TouCAN module is capable of generating one of the 32 possible interrupt levels on the IMB3 The 32 interrupt levels are time multiplexed on the IMB3 IRQ 0 7 lines All interrupt sources place their asserted level on a time multiplexed bus during four different time slots with eight levels communicated per slot The ...

Page 602: ...e upper 256 are fully used for the message buffer structures Of the lower 128 bytes some are not used Registers with bits marked as reserved should always be written as logic 0 Typically the TouCAN control registers are programmed during system initialization before the TouCAN becomes synchronized with the CAN bus The configuration reg isters can be changed after synchronization by halting the Tou...

Page 603: ...al Mask Low RXGMSKLO_x See Table 16 20 for bit descriptions S U 0x30 7094 0x30 7494 Receive Buffer 14 Mask High RX14MSKHI_x See 16 7 10 Receive Buffer 14 Mask Registers for bit descriptions S U 0x30 7096 0x30 7496 Receive Buffer 14 Mask Low RX14MSKLO_x See 16 7 10 Receive Buffer 14 Mask Registers for bit descriptions S U 0x30 7098 0x30 7498 Receive Buffer 15 FMask High RX15MSKHI_x See 16 7 11 Rece...

Page 604: ...6 3 and Table 16 4 for message buffer definitions S U 0x307170 0x30717F A 0x30 7570 0x30 757F B MBUFF71 TouCAN_A Message Buffer 7 See Table 16 3 and Table 16 4 for message buffer definitions S U 0x30 7180 0x30 718F A 0x30 7580 0x30 758F B MBUFF81 TouCAN_A Message Buffer 8 See Table 16 3 and Table 16 4 for message buffer definitions S U 0x30 7190 0x30 719F A 0x30 7590 0x30 759F B MBUFF91 TouCAN_A M...

Page 605: ...e the MBUFF arrays address 0x E is reserved and may cause a RCPU exception if read Table 16 10 TouCAN Register Map Continued Access Offset MSB 0 LSB 15 0x30 7100 0x30 7500 0x30 7102 0x30 7502 ID Low Message Buffer 0 0x307104 0x307504 0x30 7106 0x30 7506 0x30 710C 0x30 750C 0x30710E 0x30750E 0x30 7110 0x30 7510 Message Buffer 1 0x30 7120 0x30 7520 0x30 71FF 0x30 75FF Message Buffer 2 Message Buffer...

Page 606: ...N Module Configuration Register 0x30 7080 0x30 7480 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 STOP FRZ NOT USED HALT NOT RDY WAKE MSK SOFT RST FRZ ACK SUPV SELF WAKE APS STOP ACK RESERVED RESET 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 607: ...top mode or debug mode 1 TouCAN is in low power stop mode or debug mode 5 WAKEMSK Wakeup interrupt mask The WAKEMSK bit enables wake up interrupt requests 0 Wake up interrupt is disabled 1 Wake up interrupt is enabled 6 SOFTRST Soft reset When this bit is asserted the TouCAN resets its internal state machines sequencer error counters error flags and timer and the host interface registers CANMCR CA...

Page 608: ...sabled 1 Self wake enabled 10 APS Auto power save The APS bit allows the TouCAN to automatically shut off its clocks to save power when it has no process to execute and to automatically restart these clocks when it has a task to execute without any CPU intervention 0 Auto power save mode disabled clocks run normally 1 Auto power save mode enabled clocks stop and restart as needed 11 STOPACK Stop a...

Page 609: ...2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 BOFF MSK ERR MSK RESERVED RXMOD TXMODE CANCTRL1 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 16 13 CANCTRL0 Bit Descriptions Bit s Name Description 0 BOFFMSK Bus off interrupt mask The BOFF MASK bit provides a mask for the bus off interrupt 0 Bus off interrupt disabled 1 Bus off interrupt enabled 1 ERRMSK Error interrupt mask The ERRMSK bit provides a mask for ...

Page 610: ...on TXMODE 1 0 Transmit Pin Configuration 00 Full CMOS1 positive polarity CNTX0 0 CNTX12 1 is a dominant level 2 NOTES 1 Full CMOS drive indicates that both dominant and recessive levels are driven by the chip 2 The CNTX1 signal is not available on the MPC555 MPC556 01 Full CMOS negative polarity CNTX0 1 CNTX12 0 is a dominant level 1X Open drain3 positive polarity 3 Open drain drive indicates that...

Page 611: ...multiple TouCAN stations with a special SYNC message global network time 0 Timer synchronization disabled 1 Timer synchronization enabled Note there can be a bit clock skew of four to five counts between different TouCAN modules that are using this feature on the same network 11 LBUF Lowest buffer transmitted first The LBUF bit defines the transmit first scheme 0 Message buffer with lowest ID is t...

Page 612: ...RJW Resynchronization jump width The RJW field defines the maximum number of time quanta a bit time may be changed during resynchronization The valid programmed values are zero through three The resynchronization jump width is calculated as follows Resynchronizaton Jump Width RJW 1 Time Quanta 10 12 PSEG1 PSEG1 2 0 Phase buffer segment 1 The PSEG1 field defines the length of phase buffer segment o...

Page 613: ...ge on the bus it increments at the nominal bit rate The timer value is captured at the beginning of the identifier field of any frame on the CAN bus The captured value is written into the time stamp entry in a message buffer after a suc cessful reception or transmission of a message RXGMSKHI Receive Global Mask Register High 0x30 7090 0x30 7490 RXGMSKLO Receive Global Mask Register Low 0x30 7092 0...

Page 614: ...ame Description 0 31 MIDx The receive global mask registers use four bytes The mask bits are applied to all receive identifiers excluding receive buffers 14 and 15 which have their own specific mask regis ters Base ID mask bits MID 28 18 are used to mask standard or extended format frames Ex tended ID bits MID 17 0 are used to mask only extended format frames The RTR SRR bit of a received frame is...

Page 615: ...gister 1 A bit stuffing error was detected since the last read of this register 6 TXWARN Transmit error status flag The TXWARN status flag reflects the status of the TouCAN trans mit error counter 0 Transmit error counter 96 1 Transmit error counter 96 7 RXWARN Receiver error status flag The RXWARN status flag reflects the status of the TouCAN re ceive error counter 0 Receive error counter 96 1 Re...

Page 616: ...Status 00 No transmit bit error 01 At least one bit sent as dominant was received as recessive 10 At least one bit sent as recessive was received as dominant 11 Not used Table 16 23 Fault Confinement State Encoding FCS 1 0 Bus State 00 Error active 01 Error passive 1X Bus off IMASK Interrupt Mask Register 0x30 70A2 0x30 74A2 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 LSB 15 IMASKH IMASKL RESET 0 0 0 0...

Page 617: ...ing IMASK bit is set an interrupt request will be generated To clear an interrupt flag first read the flag as a one and then write it as a zero Should a new flag setting event occur between the time that the CPU reads the flag as a one and writes the flag as a zero the flag is not cleared This register can be written to zeros only NOTE Bit 15 LSB corresponds to message buffer 0 Bit 0 MSB correspon...

Page 618: ...555 MPC556 CAN 2 0B CONTROLLER MODULE MOTOROLA USER S MANUAL Rev 15 October 2000 16 36 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 619: ...two independent TPU3s Figure 17 1 is a simplified block diagram of a single TPU3 Figure 17 1 TPU3 Block Diagram 17 1 Overview The TPU3 can be viewed as a special purpose microcomputer that performs a pro grammable series of two operations match and capture Each occurrence of either op eration is called an event A programmed series of events is called a function TPU functions replace software funct...

Page 620: ...pin control logic The event register contains a 16 bit capture register a 16 bit compare match register and a 16 bit greater than or equal to comparator The direction of each pin either output or input is determined by the TPU microengine Each channel can either use the same time base for match and capture or can use one time base for match and the other for capture 17 2 3 Scheduler When a service...

Page 621: ...ermine precisely when a match or capture event occurs and respond rapidly An event register for each chan nel provides for simultaneous match capture event occurrences on all channels When a match or input capture event requiring service occurs the affected channel generates a service request to the scheduler The scheduler determines the priority of the request and assigns the channel to the micro...

Page 622: ...der a 32 bit counter value that is read and written as two 16 bit words The 32 bit value is read coherent only if both 16 bit portions are updated at the same time and write coherent only if both portions take effect at the same time Parameter RAM hardware supports coherent access of two adjacent 16 bit parameters The host CPU must use a long word operation to guaran tee coherency 17 3 6 Emulation...

Page 623: ...ICR each interrupt request level is driven during the time multiplexed bus during one of four different time slots with eight levels communicated per time slot No hard ware priority is assigned to interrupts Furthermore if more than one source on a mod ule requests an interrupt at the same level the system software must assign a priority to each source requesting at that level Figure 17 2 displays...

Page 624: ...aler is then divided by 1 2 4 or 8 depending on the value of the TCR1P field in the TPUMCR If the DIV2 bit is one the TCR1 counter increments at a rate of the internal clock divided by two If DIV2 is zero the TCR1 increment rate is defined by the output of the TCR1 prescaler which in turn takes as input the output of either the standard or enhanced prescaler Figure 17 3 shows a diagram of the TCR1...

Page 625: ...ncremented at the frequency of the DIV8 clock When T2CG is cleared an external clock from the TCR2 pin which has been synchronized and fed through a digital filter increments TCR2 The duration between active edges on the T2CLK clock pin must be at least nine IMB clocks The TCR2PSCK2 bit in TPUMCR3 determines whether the clock source is divided by two before it is fed into the TCR2 prescaler The TC...

Page 626: ...ll registers except the channel interrupt status register CISR must be read or written by means of half word 16 bit or word 32 bit accesses The address space of the TPU3 memory map occupies 512 bytes Unused registers within the 512 byte address space return zeros when read Table 17 5 shows the TPU3 address map Table 17 4 TCR2 Prescaler Control TCR2 Value Internal Clock Divide Ratio External Clock ...

Page 627: ...election Register 3 CFSR3 See Table 17 11 for bit descriptions 0x30 4014 0x30 4414 Host Sequence Register 0 HSQR0 See Table 17 12 for bit descriptions 0x30 4016 0x30 4416 Host Sequence Register 1 HSQR1 See Table 17 12 for bit descriptions 0x30 4018 0x30 4418 Host Service Request Register 0 HSRR0 See Table 17 13 for bit descriptions 0x30 401A 0x30 441A Host Service Request Register 1 HSRR1 See Tabl...

Page 628: ...0 4180 0x30 418F 0x30 4580 0x30 458F Channel 8 Parameter Registers 0x30 4190 0x30 419F 0x30 4590 0x30 459F Channel 9 Parameter Registers 0x30 41A0 0x30 41AF 0x30 45A0 0x30 45AF Channel 10 Parameter Registers 0x30 41B0 0x30 41BF 0x30 45B0 0x30 45BF Channel 11 Parameter Registers 0x30 41C0 0x30 41CF 0x30 45C0 0x30 45CF Channel 12 Parameter Registers 0x30 41D0 0x30 41DF 0x30 45D0 0x30 45DF Channel 13...

Page 629: ...RAM operate in emulation mode 6 T2CG TCR2 clock gate control 0 TCR2 pin used as clock source for TCR2 1 TCR2 pin used as gate of DIV8 clock for TCR2 Refer to 17 3 9 Prescaler Control for TCR2 for more information 7 STF Stop flag 0 TPU3 is operating normally 1 TPU3 is stopped STOP bit has been set 8 SUPV Supervisor data space 0 Assignable registers are accessible from user or supervisor privilege l...

Page 630: ...402 Used for factory test only 17 4 3 Development Support Control Register DSCR Development Support Control Register 0x30 4004 0x30 4404 MSB LSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HOT4 RESERVED BLC CLKS FRZ CCL BP BC BH BL BM BT RESET 0 0 0 0 0 0 0 0 0 0 0 0 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 631: ... written 0 Only the pin state condition of the new channel is latched as a result of the write CHAN reg ister microinstruction 1 Pin state MRL and TDL conditions of the new channel are latched as a result of a write CHAN register microinstruction 10 BP µPC breakpoint enable 0 Breakpoint not enabled 1 Break if µPC equals µPC breakpoint register 11 BC Channel breakpoint enable 0 Breakpoint not enabl...

Page 632: ...reakpoint register PCBK is negated when the BKPT flag is cleared 10 CHBK Channel register breakpoint flag CHBK is asserted if a breakpoint occurs because of a CHAN register match with the CHAN register breakpoint register CHBK is negated when the BKPT flag is cleared 11 SRBK Service request breakpoint flag SRBK is asserted if a breakpoint occurs because of any of the service request latches being ...

Page 633: ...el for all channels This field is used in conjunction with the ILBS field to determine the request level of TPU3 interrupts 8 9 ILBS Interrupt level byte select This field and the CIRL field determine the level of TPU3 interrupt re quests 00 IRQ 0 7 selected 01 IRQ 8 15 selected 10 IRQ 16 23 selected 11 IRQ 24 31 selected 10 15 Reserved Note that bits 10 11 represent channel interrupt base vector ...

Page 634: ...on Select Register 1 0x30 400E 0x30 440E MSB LSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CH 11 CH 10 CH 9 CH 8 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFSR2 Channel Function Select Register 2 0x30 4010 0x30 4410 MSB LSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CH 7 CH 6 CH 5 CH 4 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFSR3 Channel Function Select Register 3 0x30 4012 0x30 4412 MSB LSB 0 1 2 3 4 5 6 7 8 9...

Page 635: ... CH 8 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSQR1 Host Sequence Register 1 0x30 4016 0x30 4416 MSB LSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 17 12 HSQRx Bit Descriptions Name Description CH 15 0 Encoded host sequence The host sequence field selects the mode of operation for the time function selected on a given cha...

Page 636: ...i croengine on that channel The host can request service on a channel by writing the corresponding host service request field to one of three non zero states The CPU must monitor the host service request register until the TPU3 clears the service request to 0b00 before any parameters are changed or a new service request is issued to the channel CPR0 Channel Priority Register 0 0x30 401C 0x30 441C ...

Page 637: ...ter SGLR Service Grant Latch Register 0x30 4024 0x30 4424 Used for factory test only 17 4 14 Decoded Channel Number Register DCNR Decoded Channel Number Register 0x30 4026 0x30 4426 Used for factory test only Table 17 15 Channel Priorities CHx 1 0 Service Guaranteed Time Slots 00 Disabled 01 Low 1 out of 7 10 Middle 2 out of 7 11 High 4 out of 7 CISR Channel Interrupt Status Register 0x30 4020 0x3...

Page 638: ... bank select This field determines the bank where the microcoded entry table is situ ated After reset this field is 0b00 This control bit field is write once after reset ETBANK is used when the microcode contains entry tables not located in the default bank 0 To execute the ROM functions on this MCU ETBANK 1 0 must be 0b0 Refer to Table 17 18 NOTE This field should not be modified by the programme...

Page 639: ...0 442A MSB LSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RESERVED PWOD TCR2 PCK2 EP SCKE Re served EPSCK RESET 0 0 0 0 0 0 0 Table 17 20 TPUMCR3 Bit Descriptions Bit s Name Description 0 6 Reserved 7 PWOD Prescaler write once disable bit The PWOD bit does not lock the EPSCK field and the EPSCKE bit 0 Prescaler fields in MCR are write once 1 Prescaler fields in MCR can be written anytime 8 TCR2PSC K2 T...

Page 640: ...100 500 102 502 104 504 106 506 108 508 10A 50A 10C 50C 10E 50E 1 110 510 112 512 114 514 116 516 118 518 11A 51A 11C 51C 11E 51E 2 120 520 122 522 124 524 126 526 128 528 12A 52A 12C 52C 12E 52E 3 130 530 132 532 134 534 136 536 138 538 13A 53A 13C 53C 13E 53E 4 140 540 142 542 144 544 146 546 148 548 14A 54A 14C 54C 14E 54C 5 150 550 152 552 154 554 156 556 158 558 15A 55A 15C 55C 15E 55E 6 160 ...

Page 641: ...rameter Number 0 1 2 3 4 5 6 7 14 1E0 5E0 1E2 5E2 1E4 5E4 1E6 5E6 1E8 5E8 1EA 5EA 1EC 5EC 1EE 5EE 15 1F0 5F0 1F2 5F2 1F4 5F4 1F6 5F6 1F8 5F8 1FA 5FA 1FC 5FC 1FE 5FE NOTES 1 These addresses should be added to 0x30 4000 to derive the com plete parameter address Table 17 21 Parameter RAM Address Offset Map1 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go ...

Page 642: ...MPC555 MPC556 TIME PROCESSOR UNIT 3 MOTOROLA USER S MANUAL Rev 15 October 2000 17 24 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 643: ...y an external source The DPTRAM may also be used as the microcode control store for up to two TPU3 modules when placed in a special emulation mode In this mode the DPTRAM array may only be accessed by either or both of the TPU3 units simultaneously via separate emulation buses and not via the IMB3 The DPTRAM contains a multiple input signature calculator MISC in order to provide RAM data corruptio...

Page 644: ...gisters are located in supervisor data space User reads or writes of these will result in a bus error When the TPU3 is using the RAM array for microcode control store none of these con trol registers have any effect on the operation of the RAM array All addresses within the 64 byte control block will respond when accessed properly Unimplemented addresses will return zeros for read accesses Likewis...

Page 645: ...s Address Register Reset Value Supv R W 0x30 0000 DPT RAM Module Configuration Register DPTRMCR See Table 18 2 for bit descriptions 0x0100 Test 0x30 0002 Test Configuration Register DPTTCR 0x0000 Supv R W 0x30 0004 RAM Base Address Register RAMBAR See Table 18 3 for bit descriptions 0x0001 Supv Read Only 0x30 0006 Multiple Input Signature Register High MISRH See 18 3 4 MISR High MISRH and MISR Low...

Page 646: ... determine if the MISC has completed reading the RAM If MISF is set the host should read the MISRH and MISRL registers to obtain the RAM signature 0 First signature not ready 1 MISC has read entire RAM Signature is latched in MISRH and MISRL and is ready to be read 6 MISEN Multiple input signature enable MISEN is readable and writable at any time The MISC will only operate when this bit is set and...

Page 647: ...7 8 9 10 11 12 13 14 LSB 15 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 Reserved RAMDS RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Table 18 3 RAMBAR Bit Descriptions Bit s Name Description 0 10 A 8 18 RAM array base address These bits specify the 11 high order bits address lines ADDR 8 18 in little endian notation of the 24 bit base address of the RAM array This allows the array to be placed on a 8 Kbyte ...

Page 648: ... 18 4 2 Standby Operation The DPTRAM array uses a separate power supply VDDSRAM to maintain the con tents of the DPTRAM array during a power down phase When the RAM array is powered by the VDDSRAM pin of the MCU access to the RAM array is blocked Data read from the RAM array during this condition cannot be guar anteed Data written to the DPTRAM may be corrupted if switching occurs during a write o...

Page 649: ... asynchronous reset such as the loss of clocks or software watchdog time out the contents of the RAM array are not guaranteed Refer to SEC TION 7 RESET for a description of MPC555 MPC556 reset sources operation con trol and status Reset will also reconfigure some of the fields and bits in the DPTRAM control registers to their default reset state See the description of the control registers to dete...

Page 650: ...ccesses set the EMU bit in the corresponding TPU3 module configuration register Through the auxiliary buses the TPU3 units can access word instructions simultaneously at a rate of up to 40 MHz When the RAM array is being used by either or both of the TPU3 units all accesses via the IMB3 are disabled The control registers have no effect on the RAM array Ac cesses to the array are ignored allowing a...

Page 651: ...ters and the host determines if it matches the predetermined signature The MISRH and MISRL registers are updated each time the MISC completes reading the entire RAM regardless of whether or not the previous signature has been read or not This ensures that the host reads the most recently generated signature The MISC can be disabled by clearing the MISEN bit in the DPTMCR Note that the reset state ...

Page 652: ...C555 MPC556 DUAL PORT TPU RAM DPTRAM MOTOROLA USER S MANUAL Rev 15 October 2000 18 10 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 653: ...me The BIU accesses 32 bytes of information in the array at a time These bytes are cop ied into a read page buffer aligned to the low order addresses ADDR 27 31 Each CMF module contains two non overlapping page buffers The first page buffer is as sociated with array blocks zero to three The second page is associated with array blocks four to seven for CMF Module A or blocks four to five for CMF Mo...

Page 654: ...Program up to 512 bytes at a time per CMF module Program up to eight unique 64 byte pages of data in eight separate blocks si multaneously CMF Module A Program up to six unique 64 byte pages of data in six separate blocks simul taneously CMF Module B Program CMF Module A and CMF Module B at the same time Pages located at the same offset address Self timed program and erase pulses Internal pulse wi...

Page 655: ...e read page buffers and requires one clock Over programmed By exceeding the specified programming time and or volt age a CMF bit may be over programmed This bit will cause erased bits on the same column in the same array block to read as programmed Programming write A word write to a CMF array address to transfer informa tion into a program page buffer The CMF EEPROM accepts programming writes fro...

Page 656: ...re special CMF NVM registers which retain their state when power is removed from the CMF EEPROM These special FLASH NVM registers are identified in the individual register field and control bit descriptions The CMF EEPROM control registers are accessible for read or write operation at all times while the device is powered up except during master reset soft reset or erase interlock write The access...

Page 657: ...ogrammer s Model Address Register Control Registers Located in Supervisor Data Space 0x2F C800 0x2F C840 CMF Module Configuration Register CMFMCR See Table 19 2 for bit descriptions 0x2F C804 0x2F C844 CMF EEPROM Test Register CMFTST See Table 19 3 for bit descriptions 0x2F C808 0x2F C848 High Voltage Control Register CMFCTL See Table 19 6 for bit descriptions 0x2F C80C 0x2F C81C 0x2F C84C 0x2F C8...

Page 658: ...censored access Refer to 19 8 Censored and Non Censored Accesses for details Writes to this bit have no effect when CSC 1 This bit can be set only when the MCU is in un censored mode 0 Censored CMF array access allowed only if the CMF censorship is no censorship FIC 0 and CENSOR 0 CENSOR 1 1 Allows all CMF array access 6 7 CENSOR Censor accesses The value of these bits is determined by the state o...

Page 659: ... the CMF EEPROM can be protected from program and erase operation by setting PROTECT M 1 The CMF BIU will perform all programming and erase interlocks except the program and erase voltages will not be applied to MoneT locations within the protected array block s Writes to PROTECT 0 7 have no effect if LOCK 0 or CSC 1 or SES 1 0 Array block M is unprotected 1 Array block M is protected default valu...

Page 660: ...reserved for Motorola factory testing and should always be programmed to 0b0 0 Normal Operation 1 Factory test mode use only This setting could disturb contents of flash 26 GDB Gate drain bias select This bit works in conjunction with the PAWS bits to select between pos itive and negative ramped voltages for programing and erasing This bit is writeable when SES 0b0 0 Positive voltage ramp selected...

Page 661: ...low range 1 100 ms1 1 101 1 Mode 5NL 1 100 ms1 1 110 1 Mode 6NL 1 100 ms1 1 111 1 Mode 7NL 1 100 ms1 0 100 1 Mode 4NL Negative gate ramp high range 1 100 ms1 0 101 1 Mode 5NL 1 100 ms1 0 110 1 Mode 6NL 20 100 ms2 2 Do margin read after each pulse 0 111 1 Mode 7NL CMFCTL CMF EEPROM High Voltage Control Register 0x2F C808 0x2F C848 MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HVS 0 SCLKR 0 CLKPE 0 CLKP...

Page 662: ...ng to the follow ing equation M 1 CLKPM 0 6 The CLKPM bits are write protected by the SES bit Writes to CMFCTL will not change CLKPM if SES 1 The reset state of CLKPM 0 for a multiplier of 1 Refer to 19 7 5 Linear Clock Multiplier for more information 16 23 BLOCK 0 7 Block program and erase select The CMF EEPROM array blocks that are selected to be pro grammed or erased are the blocks for which BL...

Page 663: ...es The CMF samples EPEE when EHV is asserted and holds the EPEE state until EHV is negated EPEE is a read only bit writes have no effect 0 High voltage operations are not possible 1 High voltage operations are possible Refer to 19 9 1 EPEE Signal for more information 27 28 Reserved 29 PE Program or erase select PE configures the CMF EEPROM for programming or erasing When PE 0 the array is configur...

Page 664: ... 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 0000000 USIU Internal Mapping Array Hardware Mapping Block Address Row Address Column Address Byte Addr Table 19 8 CMF EEPROM Array Address Fields Bit s Field Description 0 6 The seven high order address bits of a CMF EEPROM array access or any MPC555 MPC556 internal access must equal zero 7 9 USIU Internal Mapping These bits...

Page 665: ...from the address of the first programming write To select the CMF EEPROM array block that will be programmed the program page buffers use the CMF EEPROM array configuration and BLOCK 0 7 The array block that will be programmed is selected by the BLOCK bit that is set If BLOCK M 1 then program buffer M is active and array block M is selected for pro gramming Bits in the program page buffers select ...

Page 666: ...gram Page Buffer 5 32 Kbyte Array Block 4 0x2 0000 0x2 7FFF 32 Kbyte Array Block 5 0x2 8000 0x2 FFFF 64 byte Program Page Buffer 4 Bus Interface Unit BIU 64 byte Program Page Buffer 6 3 2Kbyte Array Block 7 0x3 8000 0x3 FFFF 32 Kbyte Array Block 6 0x3 0000 0x3 7FFF 32 byte Read Page Buffer 1 64 byte Program Page Buffer 7 1 If SIE 1 then the shadow row is enabled instead of the flash block Shadow l...

Page 667: ... block registers accesses the registers and not the shadow information The read page buffer address monitor is reset whenever SIE is modified making the next CMF array access an off page access The default reset state of SIE is normal array access SIE 0 64 byte Program Page Buffer 4 32 Kbyte Array Block 4 0x6 0000 0x6 7FFF 64 byte Program Page Buffer 5 32 Kbyte Array Block 5 0x6 8000 0x6 FFFF 32 b...

Page 668: ...ions The remaining 240 bytes are available as supervisor data This is shown in Figure 19 2 Figure 19 2 Shadow Information 19 3 2 Reset Configuration Word CMFCFIG The CMF EEPROM reset configuration word is implemented in the first word AD DR 24 29 0x00 of the special shadow locations The reset configuration word along with the rest of the shadow information words is located in supervisor data addre...

Page 669: ...ot the data in the array The type of CMF EEPROM array read is determined by comparing the address of the requested information with the address of the read page buffers If the requested ad dress is not within one of the read page buffers or if the read page buffer has been made invalid an off page read results This read updates the read page buffer address of the selected array block copies the in...

Page 670: ...ng programmed must be done before the CMF EEPROM can be used reliably If block M of the CMF EEPROM is protected PROTECT M 1 it will not be pro grammed Also if EPEE 0 no programming voltages will be applied to the array Software should verify the state of EPEE prior to programming programming will fail if EPEE 0 The user should also insure that the programming voltage 5 0 0 25 volts is applied to V...

Page 671: ...s are disabled until SES has been cleared and set 7 Read the CMFCTL register until HVS 0 8 Write EHV 0 9 To verify the programming read the words of the pages that are being pro grammed These are program margin reads See 19 5 2 Program Margin Reads If any bit is a 1 after reading all of the locations that are being pro grammed then another pulse needs to be applied to the these locations If all th...

Page 672: ...equired per Table 19 4 SCLKR CLKPE CLKPM b Write new values for PAWS NVR and GDB if required per Table 19 4 c Go back to step 6 to apply additional programming pulses 11 If more information needs to be programmed go back to step 2 Figure 19 3 Program State Diagram S1 T1 T2 T3 S2 S4 T4 S3 S5 T5 T8 T7 T6 T9 Reset Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Prod...

Page 673: ...tate of the bit needs no further modification by the program operation If the write is to a register no data will be stored in the program page buffers and the CMF will remain in state S2 S3 Expanded Program Hardware Interlock Operation Program margin reads will occur Programming writes are accepted so that all program pages may be programmed These writes may be to any CMF array location The progr...

Page 674: ... after each program pulse S5 Program Margin Read Operation These reads determines if the state of the bits on the selected page needs further modification by the program operation Once a bit is fully pro grammed the data stored in the program page is updated No further programming occurs for that bit and the value read is a 0 While it is not necessary to read all words on a page to determine if an...

Page 675: ...bulk operation that affects the stored charge of all the isolated elements in an array block To make the CMF module block erasable the array is divided into blocks that are physically isolated from each other Each of the array blocks may be erased in isola tion or in any combination The CMF array block size is fixed for all blocks in the mod ule at 32 Kbytes CMF module A consists of eight array bl...

Page 676: ... locations read as erased go to step 9 NOTE Do not perform erase margin reads until reaching the condition PAWS 0b111 NVR 0 and GDB 1 9 To reduce the time used for erase margin reads upon the first read of a zero do the following a Write new pulse width parameters SCLKR CLKPE and CLKPM if required per Table 19 5 b Write new PAWS value if required per Table 19 5 c Write new values for NVR and GDB i...

Page 677: ...ROLA USER S MANUAL Rev 15 October 2000 19 25 Figure 19 4 Erase State Diagram S1 T1 T2 T3 S2 S4 T4 S3 S5 T5 T8 T7 T6 T9 Reset Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 678: ...are interlock write This write may be to any CMF array location Accesses to the registers are normal register accesses A write to CMFCTL can not set EHV at this time A write to the register is not an erase hardware interlock write and the CMF remains in state S2 S1 T1 Write SES 0 or a master reset S3 T3 Hardware Interlock A successful write to any CMF array lo cation is the erase interlock write I...

Page 679: ... bit and is terminated by clearing EHV or by the pulse width timing control Figure 19 5 Pulse Status Timing The recovery time is the time required for the CMF EEPROM to remove the program or erase voltage from the array or shadow information before switching to another mode of operation The recovery time is determined by the system clock range SCLKR 0 2 and the PE bit If SCLKR 000 the recovery tim...

Page 680: ...event program or erase operation at frequencies below 8 0 MHz Attempting to program or erase the CMF EEPROM at system clock frequencies lower than 8 0 MHz will not damage the device if the maximum pulse times and total times are not exceeded While some bits in the CMF EEPROM array may change state if programmed or erased at system clock frequencies below 8 0 MHz the full program or erase transitio...

Page 681: ...KPM The following example determines the values of the SCLKR CLKPE and CLKPM fields for a 25 6 µs program pulse PE 0 in a system with a 40 MHz system clock Table 19 13 Clock Period Exponent and Pulse Width Range PE CSC CLKPE 0 1 Exponent N Pulse Width Range for all System Clock Frequencies from 8 0 MHz to 40 0 MHz Minimum Pulse Width Maximum Pulse Width 8 MHz1 2N 1 25E 7 NOTES 1 CMF clock frequenc...

Page 682: ...or the erase interlock write NOTE The erase interlock write is a write to any CMF EEPROM array loca tion after SES is set and PE 1 If the PE bit is a zero the CMF BIU accepts programming writes to the CMF array ad dress for programming The first programming write selects the program page offset address ADDR 17 25 to be programmed along with the data for the programming buffers at the location writ...

Page 683: ...se 19 8 Censored and Non Censored Accesses The MPC555 MPC556 always operates in one of two modes censored or uncen sored 19 8 1 Uncensored Mode Uncensored mode provides no censorship In uncensored mode the FIC ACCESS and CENSOR 0 1 bits are irrelevant The MPC555 MPC556 operates in uncensored mode unless a specific event occurs to place the device in censored mode 19 8 2 Censored Mode The MPC555 MP...

Page 684: ...he CENSOR bits have no effect upon censorship If FIC 1 and AC CESS 0 the CMF is in information censorship mode If FIC 1 and ACCESS 1 the CMF is in normal access mode This arrangement aids in the development of custom techniques for controlling the ACCESS bit without setting CENSOR 0 1 to the information censorship state Using FIC to force information censorship allows testing of the hardware and s...

Page 685: ...t CEN SOR 0 1 can be set CENSOR 0 1 can not be cleared 2 CMF array can be accessed ACCESS can not be changed FIC can be set CEN SOR 0 1 can be set CENSOR 0 1 can be cleared 3 CMF array can not be accessed ACCESS can not be changed FIC can be set CEN SOR 0 1 can not be cleared 4 CMF array can not be accessed ACCESS can not be changed FIC can not be changed CENSOR 0 1 can be set CENSOR 0 1 can not b...

Page 686: ... The clear operation changes the state in an NVM fuse from a one to a zero by erasing NVM bit 0 and programming NVM bit 1 simultaneously in the NVM fuse This clear op eration can be done only while erasing the entire CMF array and shadow information To clear CENSOR 0 1 1 Write PROTECT 0 7 0x00 to enable the entire array for erasure 2 Using section 19 7 6 A Technique to Determine SCLKR CLKPE and CL...

Page 687: ...formation censorship These three levels state values transitions and level of censorship are shown in Figure 19 6 Figure 19 6 Censorship States and Transitions CENSOR 0 1 1 CENSOR 0 1 2 CENSOR 0 1 0 T1 T2 T3 No Censorship Cleared Censorship Information Censorship CENSOR 0 1 3 Data Data Data Data Data Data Data Unknown T3 T4 T3 Freescale Semiconductor I Freescale Semiconductor Inc For More Informat...

Page 688: ...use the following pins EPEE VPP VDDF VSSF 19 9 1 EPEE Signal The EPEE bit monitors the state of the external program erase enable EPEE pin EPEE has a digital filter that requires two consecutive samples to be equal before the output of the filter changes The CMF samples EPEE when EHV is asserted and holds the EPEE state until EHV is negated This is shown in Figure 19 7 Figure 19 7 EPEE Digital Fil...

Page 689: ...pin is not provided One high or low clock of EPEE does not cause CMF_EPEE to switch Figure 19 8 CMF_EPEE Timing Diagram 19 9 2 FLASH Program Erase Voltage Conditioning A voltage of at least VDDL 0 35 V must be applied at all times to the VPP pins or damage to the FLASH module can occur FLASH modules can be damaged by power on and power off VPP transients VPP must not rise to programming level whil...

Page 690: ...ve reverse current D2 also protects the FLASH from damage should the programming voltage go to zero Programming power supply voltage must be adjusted to compensate for the forward 100 ns Maximum 6 0 V 5 25 V 4 75 V 3 6 V 3 0 V 2 65 V 0 0 V 0 35 V Power On Normal Program Erase Power Down Maximum Overshoot 5 5 V VPP Envelope VDDL Envelope Suggested VPP Suggested VDDL Normal Combined VPP and VDDL Thi...

Page 691: ...PROM is in program or erase operation EHV 1 and a master reset is gen erated the module will perform the needed interlocks to disable the high voltage with out damage to the high voltage circuits Master reset will terminate any other mode of operation and force the CMF EEPROM BIU to a state ready to receive U bus accesses within 10 clocks of the end of master reset If the HC bit of the reset confi...

Page 692: ...r The default reset enable disable state of the internal memories is user defined with the reset configuration word bit 20 CAUTION The reset configuration word from an erased CMF must be generat ed external to the CMF i e from the default reset configuration word off the external reset configuration word See 7 5 Reset Configura tion EHV is reset to 0 when the CMF is disabled and can not be set unt...

Page 693: ...The SRAM modules are accessible to the CPU and other bus masters via the L bus on the CPU chip To improve access time each SRAM module resides on a separate bus interface unit BIU Each BIU has its own module control register 20 1 Features One cycle access Byte half word or word read write accesses Individual protection control bits provided for 4 Kbyte block boundaries read only region data only r...

Page 694: ...er for use in testing 20 3 1 SRAM Module Configuration Register SRAMMCR Each SRAM module configuration register contains bits for setting access rights to the array Table 20 1 provides definitions for the bits SRAMMCR_A SRAMTST_A 0 31 0x38 0000 0x38 0004 SRAMMCR_B SRAMTST_B 0x38 0008 0x38 000C 6 Kbytes Unused Sub Block 0 Sub Block 1 0x3F 8000 0x3F 8FFF 0x3F 9000 0x3F 97FF 10 Kbytes SRAM Sub Block ...

Page 695: ...mode In this mode the first cycle is used for decoding the address and the second cycle is used for accepting or providing data This mode provides some power savings while keeping the memory active 3 19 Reserved 20 23 26 29 Rx x 0 1 2 3 Read only R0 controls the highest 4 Kbyte block lowest address of the SRAM array R3 controls the lowest block highest address 0 4 Kbyte block is readable and writa...

Page 696: ...5 MPC556 STATIC RANDOM ACCESS MEMORY SRAM MOTOROLA USER S MANUAL Rev 15 October 2000 20 4 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 697: ...re defined below The program instructions flow is visible on the external bus when the MPC555 MPC556 is programmed to operate in serial mode and show all fetch cycles on the ex ternal bus This mode is selected by programming the ISCT_SER instruction fetch show cycle control field in the I bus support control register ICTRL as shown in Ta ble 21 21 In this mode the processor is fetch serialized and...

Page 698: ... For more information on the activity of the external hardware during program trace refer to 21 2 4 The External Hardware In order to keep the pin count of the chip as low as possible VSYNC is not implement ed as one of the chip s external pins It is asserted and negated using the serial inter face implemented in the development port For more information on this interface refer to 21 5 Development...

Page 699: ...rmation 010 Branch direct or indirect not taken More instruction type information 011 VSYNC was asserted negated and therefore the next instruction will be marked with the indirect change of flow attribute More instruction type information 100 Exception taken the target will be marked with the indirect change of flow attribute Queue flush information1 NOTES 1 Unless next clock VF 111 See below 101...

Page 700: ...mode refer to 21 4 Development System Inter face If VSYNC is asserted negated while the CPU is in debug mode this information is re ported as the first VF pins report when the CPU returns to regular mode If VSYNC was not changed while in debug mode the first VF pins report will be of an indirect branch taken VF 101 suitable for the rfi instruction that is being issued In both Table 21 2 VF Pins Qu...

Page 701: ... example of such an event is some system failure In case back trace is needed the external hardware should start sampling the sta tus pins VF and VFLS and the address of all cycles marked with the program trace cycle attribute immediately when reset is negated If show cycles is pro grammed out of reset to show all all cycles marked with program trace cycle at tribute are visible on the external bu...

Page 702: ... starts sampling the program trace information upon the report on the VF pins of VSYNC 10 The hardware generates a breakpoint when the programmed event is detected and the machine enters debug mode 11 Negate VSYNC 12 Return to the regular code run issue an rfi The first report on the VF pins is a VSYNC VF 011 13 The external hardware stops sampling the program trace information upon the report on ...

Page 703: ...visible externally Therefore the external hardware should stop sampling the value of the status pins VF and VFLS and the address of the cycles marked as program trace cycle immediately after the VSYNC report on the VF pins The last two instructions reported on the VF pins are not always valid Therefore at the last stage of the reconstruction software the last two instructions should be ignored 21 ...

Page 704: ...ble bit or on the fly using the serial interface implement ed in the development port to set the corresponding development port trap enable bit External breakpoints can be generated by any of the peripherals of the system includ ing those found on the MPC555 MPC556 or externally and also by an external de velopment system Peripherals found on the external bus use the serial interface of the develo...

Page 705: ...ble external breakpoint Watchpoints are not masked and therefore always reported on the external pins re gardless of the value of the MSR RI bit The counters although counting watchpoints are part of the internal breakpoints logic and therefore are not decremented when the CPU is operating in the masked mode and the MSR RI bit is clear The following figure illustrates the watchpoints and breakpoin...

Page 706: ...hpoints pins Maskable Breakpoint Development Port Trap Enable Bits Counters Non masked Control Bit Internal Watchpoints Logic Development Port LCTRL2 MSR Software trap Enable Bits to CPU Development System OR External Peripherals Internal Peripherals X X X bit wise AND bit wise OR X X Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com...

Page 707: ...reakpoint are generated The instruction watchpoints when asserted may generate the instruction breakpoint Two of them may decrement one of the counters If one of the instruction watchpoints ex pires in a counter that is counting the instruction breakpoint is asserted The instruction watchpoints and the load store match events address and data enter the load store AND OR logic where the load store ...

Page 708: ...Only architecturally execut ed events are counted count up is performed in case of recovery On the fly trap enable programming of the different internal breakpoints using the serial interface of the development port refer to 21 5 Development Port Soft ware control is also available Watchpoints do not change the timing of the machine Internal breakpoints and watchpoints are detected on the instruct...

Page 709: ...taken or not on the instruction and the value of the IFM bit can be either zero or one Also do not put a breakpoint on an mtspr ICTRL Rx instruction when Rx contains one in bit 28 21 3 1 2 Byte and Half Word Working Modes The CPU watchpoints and breakpoints support enables the user to detect matches on bytes and half words even when accessed using a load store instruction of larger data widths for...

Page 710: ...oth byte masks 0x0 Both L data comparators program to half word mode Result The event will be correctly detected as long as the compiler does not use a load store instruction with data size of byte A partially supported scenario Looking for Data size half word Address greater than or equal 0x00000002 and less than 0x0000000e Data value greater than 0x4e204e20 and less than 0x9c409c40 Programming o...

Page 711: ... internal breakpoints detected when MSRRI 0 are lost Watchpoints detected in this case are not counted by the debug counters Watchpoints detected are always reported on the external pins regardless of the value of the MSRRI bit Out of reset the CPU is in masked mode Programming the CPU to be in non masked mode is done by setting the BRKNOMSK bit in the LCTRL2 register Refer to 21 7 8 L Bus Support...

Page 712: ...or to the needed value plus 1 This method does not work for the following boundary cases Less than or equal of the largest unsigned number 1111 1 Greater than or equal of the smallest unsigned number 0000 0 Less than or equal of the maximum positive number when in signed mode 0111 1 Greater than or equal of the maximum negative number when in signed mode 1000 These boundary cases need no special s...

Page 713: ...oint Comparator A Comparators A B IWP1 Second instruction watchpoint Comparator B Comparator A B IWP2 Third instruction watchpoint Comparator C Comparators C D IWP3 Fourth instruction watchpoint Comparator D Comparator C D Comparator A eq lt Compare Type Comparator B eq lt Comparator C eq lt Comparator D eq lt Events Generator AND OR Logic Control Bits A B A B A B C D C D C D I Watchpoint 0 I Watc...

Page 714: ...ator are significant From the new equal and less than signals and according to the compare type pro grammed by the user one of the following four match events are generated equal not equal greater than less than Therefore from the two 32 bit comparators eight match indications are generated Gmatch 0 3 Hmatch 0 3 According to the lower bits of the address and the size of the cycle only match indica...

Page 715: ...ogramming Options L address Events Programming Options L data Events Programming Options LWP0 First Load store watch point IWP0 IWP1 IWP2 IWP3 ignore instruction events Comparator E Comparator F Comparators E F Comparators E F ignore L addr events Comparator G Comparator H Comparators G H Comparators G H ignore L data events LWP1 Second Load store watch point IWP0 IWP1 IWP2 IWP3 ignore instruction...

Page 716: ...t add 30 31 Data Cycle Size Compare Size Valid 0 Valid 1 Valid 2 Valid 3 G H G H G H Instruction Watchpoints L watchpoint 0 L watchpoint 1 L breakpoint Size Logic Compare Byte Qualifier Logic Events Generator AND OR Logic Size Logic Byte Qualifier Logic Control bits E F E F E F Comparator E Type Logic Events Generator lt eq Comparator F Type Logic lt eq Compare Type Type Logic Compare Type Logic B...

Page 717: ...struction which decre ments the counter to ZERO is treated like any other load store breakpoint in the sense that it is executed and the machine branches to the breakpoint exception routine AF TER it executes this instruction Therefore the value of the counter inside the break point exception routine equals ZERO 21 3 3 1 Trap Enable Programming The trap enable bits can be programmed by regular sof...

Page 718: ...development tool emulator connected to the development port For protection purposes two possible working modes are defined debug mode en able and debug mode disable These working modes are selected only during reset For more information refer to 21 4 1 1 Debug Mode Enable vs Debug Mode Disable The user can work in debug mode starting from reset or the CPU can be programmed to enter debug mode as a...

Page 719: ...ollowing control signals 1 Instruction trap enable bits used for on the fly programming of the instruction breakpoint 2 Load store trap enable bits used for on the fly programming of the load store breakpoint 3 Non maskable breakpoint used to assert the non maskable external break point 4 Maskable breakpoint used to assert the maskable external breakpoint 5 VSYNC used to assert and negate VSYNC 32...

Page 720: ... Entering into the debug mode in all regular cases is restartable in the sense that the user is able to continue to run his regular program from the location where it entered the debug mode When in debug mode all instructions are fetched from the development port but load store accesses are performed on the real system memory Data Register of the development port is accessed using mtspr and mfspr ...

Page 721: ...6 Debug Mode Logic 5 Event valid Event set reset ECR_OR freeze rfi Decoder Exception Cause Register Debug Enable Register Q ECR DER debug mode enable internal debug mode signal Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 722: ... information on the software monitor debugger support refer to 21 6 Software Monitor Debugger Sup port When working in debug mode enable all development support registers are accessi ble only when the CPU is in debug mode Therefore even supervisor code that may be still under debug cannot prevent the CPU from entering debug mode The develop ment system has full control of all development support f...

Page 723: ...s result in regular interrupt handling DSCK OUT CLK SRESET DSCK asserts high while SRESET asserted to enable debug mode operation 0 1 2 3 4 5 8 9 10 11 12 13 14 15 16 17 DSCK asserts high following SRESET negation to enable debug mode immediately Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 724: ... instruction protection error Implementation specific data protection error External interrupt recognized when MSREE 1 Alignment interrupt Program interrupt Floating point unavailable exception Floating point assist exception Decrementer exception recognized when MSREE 1 System call exception Trace asserted when in single trace mode or when in branch trace mode refer to 3 15 4 10 Trace Interrupt I...

Page 725: ...check stop state if the machine check interrupt is disabled MSRME 0 and a machine check interrupt is detected However if a machine check interrupt is detected when MSRME 0 debug mode is enabled and the check stop enable bit in the debug enable register DER is set the CPU enters debug mode rath er then the check stop state The different actions taken by the CPU when a machine check interrupt is det...

Page 726: ...OR is asserted before the next fetch occurs to allow the de velopment system to detect the excepting instruction Not all exceptions are recognized when in debug mode Breakpoints and watchpoints are not generated by the hardware when in debug mode regardless of the value of MSRRI Upon entering debug mode MSREE is cleared by the hardware thus forcing the hardware to ignore external and decrementer i...

Page 727: ...er is presented at the DSDO pin In all further discussions references to the DSCK signal imply the internal synchronized value of the clock The DSCK input must be driv en either high or low at all times and not allowed to float A typical target environment would pull this input low with a resistor The clock may be implemented as a free running clock or as gated clock As discussed in section 21 5 6...

Page 728: ...so be monitored through status in the data shifted out of the debug port 21 5 5 1 SGPIO6 FRZ PTR Pin The SGPIO6 FRZ PTR pin powers up as the PTR function and its function is controlled by the GPC bits in the SIUMCR 21 5 5 2 IWP 0 1 VFLS 0 1 Pins The IWP 0 1 VFLS 0 1 pins power up as the VFLS 0 1 function and their function can be changed via the DBGC bits in the SIUMCR see 6 13 1 1 SIU Module Conf...

Page 729: ...x trap en able signals the two breakpoint signals and the VSYNC signal to the CPU The transfer data to trap enable control register commands will cause the appropriate bits to be transferred to the control register The trap enable control register is not accessed by the CPU but instead supplies sig nals to the CPU The trap enable bits VSYNC bit and the breakpoint bits of this reg ister are loaded ...

Page 730: ...CLKOUT signal or where the CLKOUT signal has been delayed or skewed Refer to the timing diagram in Figure 21 8 The second clock mode is called synchronous self clock It does not require an input clock Instead the port is timed by the system clock The DSDI input is required to meet setup and hold time requirements with respect to CLKOUT rising edge The data rate for this mode is always the same as ...

Page 731: ...d follows the ready bit with two status bits and 7 or 32 output data bits Development Tool drives the start bit on DSDI after detecting ready bit on DSDO when in debug mode The start bit is immediately followed by a mode bit and a control bit and then 7 or 32 input data bits NOTE DSCK and DSDI transitions are not required to be synchronous with CLKOUT DI DI DI N N 1 N 2 DO DO DO N N 1 N 2 Freescal...

Page 732: ...IR or DPDR DSDI Debug Port detects the start bit on DSDI and follows the ready bit with two status bits and 7 or 32 output data bits MODE CNTRL DI 0 START DI DI DI DI 1 DI 1 N N 1 N 2 N 3 DI DSDO when in debug mode The start bit is immediately followed by a mode bit and a control bit and then 7 or 32 input data bits S 0 S 1 DO 0 READY DO DO DO DSDO DO DO 1 N N 1 N 2 N 3 Freescale Semiconductor I F...

Page 733: ...SRESET negation to enable clocked mode CLKEN Internal clock enable signal asserts 8 clocks after SRESET negation if DSDI is negated This enables clocked mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 First Start bit detected after DSDI negation self clocked mode Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 734: ...its wide but trap enable mode transmissions only use the start ready bit a mode status bit a control status bit and the seven least significant data bits The encoding of data shifted into the development port shift reg ister through the DSDI pin is shown in Table 21 10 and Table 21 11 below The watchpoint trap enables and VSYNC functions are described in section 21 3 Watchpoints and Breakpoints Su...

Page 735: ...to occur the status output is not needed 21 5 6 8 Development Port Serial Communications Debug Mode When in debug mode the development port starts communications by setting DSDO low to indicate that the CPU is trying to read an instruction from DPIR or data from DP DR When the CPU writes data to the port to be shifted out the ready bit is not set The port waits for the CPU to read the next instruc...

Page 736: ... when the CPU was expecting data and vice versa If this occurs a sequence error indication is shifted out in the next serial transmission The trap enable function allows the development tool to transfer data to the trap enable control register The debug port command function allows the development tool to either negate break point requests reset the processor activate or deactivate the fast down l...

Page 737: ...s bus error will cause the CPU to signal that an interrupt exception occurred Since a status of sequencing error has a higher priority than exception the port will report the sequencing error first and the CPU interrupt on the next transmission The development port will ignore the command instruction or data shifted in while the se quencing error or CPU interrupt is shifted out The next transmissi...

Page 738: ...ransactions needed are those required to transfer the data to be placed in system memory Figure 21 12 and Figure 21 13 illustrate the time benefit of the fast download procedure Figure 21 12 Slow Download Procedure Loop Figure 21 13 Fast Download Procedure Loop INIT Save RX RY RY Memory Block address 4 repeat mfsprRX DPDR DATA word to be moved to memory stwuRX 0x4 RY until here Restore RX RY Exter...

Page 739: ...eeze signal is connected to all relevant internal modules These modules can be programmed to stop all operations in response to the assertion of the freeze signal In order to enable a software monitor debugger to broadcast the fact that the debug software is now executed it is possible to assert and negate the internal freeze signal also when debug mode is disabled The assertion and negation of th...

Page 740: ...ntrol Register COUNTA See Table 21 25 for bit descriptions 151 Breakpoint Counter B Value and Control Register COUNTB See Table 21 26 for bit descriptions 152 Comparator E Value Register CMPE See Table 21 18 for bit descriptions 153 Comparator F Value Register CMPF See Table 21 18 for bit descriptions 154 Comparator G Value Register CMPG See Table 21 20 for bit descriptions 155 Comparator H Value ...

Page 741: ...evelopment Support Registers Write Access Protection MSR PR Debug Mode Enable In Debug Mode Result 0 0 X Write is performed Write to ECR is ignored Writing to DPDR is ignored 0 1 0 Write is not performed Writing to DPDR is ignored 0 1 1 Write is performed Write to ECR is ignored 1 X X Write is not performed Program exception is generated CMPA CMPD Comparator A D Value Register SPR 144 SPR 147 0 1 ...

Page 742: ...its Mnemonic Description 0 31 CMPV Address bits to be compared BAR Breakpoint Address Register SPR 159 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 CMPEF RESET UNAFFECTED Table 21 19 BAR Bit Descriptions Bits Mnemonic Description 0 31 BARV 0 31 The address of the load store cycle that generated the breakpoint CMPG CMPH Comparator G H Value Registers SPR 154...

Page 743: ...arget is not always visible on the external pins Program trace is not affected by this phenomenon ICTRL I Bus Support Control Register SPR 158 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CTA CTB CTC CTD IWP0 IWP1 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 IWP2 IWP3 SIWP0 EN SIWP1 EN SIWP2 EN SIWP3 EN DIWP0 EN DIWP 1 EN DIWP 2 EN DIWP 3 EN IIFM ISCT_SER RESET 0 ...

Page 744: ...IWP1EN Software trap enable selection of the 2nd I bus watchpoint 22 SIWP2EN Software trap enable selection of the 3rd I bus watchpoint 23 SIWP3EN Software trap enable selection of the 4th I bus watchpoint 24 DIWP0EN Development port trap enable se lection of the 1st I bus watchpoint read only bit 0 trap disabled reset value 1 trap enabled 25 DIWP1EN Development port trap enable se lection of the ...

Page 745: ...e performed for fetched instructions 1 00 Illegal This mode should not be selected 1 01 RCPU is not serialized normal mode and show cycle will be performed for all changes in the program flow 1 10 RCPU is not serialized normal mode and show cycle will be performed for all indirect changes in the program flow 1 11 RCPU is not serialized normal mode and no show cycles will be performed for fetched i...

Page 746: ...g point compares 18 19 CSH Compare size comparator H 20 SUSG Signed unsigned operating mode for comparator G 0 unsigned 1 signed Must be programmed to signed for floating point compares 21 SUSH Signed unsigned operating mode for comparator H 22 25 CGBMSK Byte mask for 1st L data compara tor 0000 all bytes are not masked 0001 the last byte of the word is masked 1111 all bytes are masked 26 29 CHBMS...

Page 747: ...s 0 Don t care 1 Care 10 LW1EN 2nd L bus watchpoint enable bit 0 watchpoint not enabled reset value 1 watchpoint enabled 11 12 LW1IA 2nd L bus watchpoint I addr watchpoint selection 00 first I bus watchpoint 01 second I bus watchpoint 10 third I bus watchpoint 11 fourth I bus watchpoint 13 LW1IADC 2nd L bus watchpoint care don t care I addr events 0 Don t care 1 Care 14 15 LW1LA 2nd L bus watchpoi...

Page 748: ...nly bit 30 SLW0EN Software trap enable selection of the 1st L bus watchpoint 31 SLW1EN Software trap enable selection of the 2nd L bus watchpoint COUNTA Breakpoint Counter A Value and Control Register SPR 150 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CNTV RESET UNAFFECTED 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED CNTC RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 21 25 Breakpoint Counter ...

Page 749: ... mode is entered only if debug mode is enabled and the corresponding mask bit in the DER is set All bits are cleared to zero following reset COUNTB Breakpoint Counter B Value and Control Register SPR 151 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CNTV RESET UNAFFECTED 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RESERVED CNTC RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 21 26 Breakpoint Counter B Val...

Page 750: ...n bit Set when the program exception is asserted 9 FPUVE Floating point unavailable exception bit Set when the program exception is asserted 10 DECE Decrementer exception bit Set when the decrementer exception is asserted 11 12 Reserved 13 SYSE System call exception bit Set when the system call exception is asserted 14 TR Trace exception bit Set when in single step mode or when in branch trace mod...

Page 751: ...de is enabled and the corresponding enable bit is set 31 DPI Development port interrupt bit Set by the development port as a result of a debug station non maskable request or when debug mode is entered immediately out of reset DER Debug Enable Register SPR 149 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 RSTE CHST PE MCEE RESERVED EXTIE ALEE PREE FPU VEE DE CEE RESERVED SY SEE TRE FPAS E RESET 0 0 1 0 ...

Page 752: ...ug mode entry enabled 16 Reserved 17 SEEE Software emulation exception enable bit 0 Debug mode entry disabled reset value 1 Debug mode entry enabled 18 Reserved 19 ITLBERE Implementation specific instruction protection error enable bit 0 Debug mode entry disabled reset value 1 Debug mode entry enabled 20 Reserved 21 DTLBERE Implementation specific data protection error enable bit 0 Debug mode entr...

Page 753: ...cally resides in the development port logic It is used for data interchange between the core and the development system An ac cess to this register is initiated using mtspr and mfspr SPR 630 and implemented using a special bus cycle on the internal bus Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 754: ...MPC555 MPC556 DEVELOPMENT SUPPORT MOTOROLA USER S MANUAL Rev 15 October 2000 21 58 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 755: ...by the standard to be de fined and in certain cases provides additional information specific to the implementa tion For internal details and applications of the standard refer to the IEEE 1149 1 1990 document An overview of the JTAG pins on the MPC555 MPC556 is shown in Figure 22 1 Figure 22 1 JTAG Pins Boundary scan cells BSC are placed at the digital boundary of the chip normally the package pin...

Page 756: ...t se quence To enable JTAG on reset for board test bit 11 DGPC select JTAG pins and bit 16 PRPM peripheral mode enable of the reset configuration word should be held high during the rising edge of reset see 7 5 2 Hard Reset Configuration Word These need to be configurable on the user board to allow JTAG test of a board To allow nor mal operation of the board these bits need to be low in the reset ...

Page 757: ... to meet the IEEE 1149 1 standard Refer to Figure 22 3 Table 22 1 JTAG Interface Pin Descriptions Signal Name Input Output I O Internal Pull Up Pull Down Provided Description TDI Input Pull up Test data input pin Sampled on the rising edge of TCK Has a pull up resistor TDO Output None Test data output pin Actively driven during the Shift IR and Shift DR controller states Changes on the falling edg...

Page 758: ... bit instruction register without parity consisting of a shift register with four parallel outputs Data is transferred from the shift register to the parallel outputs during the update IR controller state The four bits are used to decode the five unique instructions listed in Table 22 2 TEST LOGIC RESET RUN TEST IDLE SELECT DR_SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR SELECT IR...

Page 759: ... 2 SAMPLE PRELOAD The SAMPLE PRELOAD instruction initializes the boundary scan register output cells prior to selection of EXTEST This initialization ensures that known data will appear on the outputs when entering the EXTEST instruction The SAMPLE PRELOAD instruc tion also provides a means to obtain a snapshot of system data and control signals NOTE Since there is no internal synchronization betw...

Page 760: ...circuit board testing When HI Z is in voked all output drivers including the two state drivers are turned off i e high impedance The instruction selects the bypass register 22 6 Restrictions The MPC555 MPC556 provides flexible control of external signals using the bound ary scan register and EXTEST or CLAMP instructions As a result the circuit board test environment must be designed to avoid signa...

Page 761: ... least five TCK pulses with TMS held high The best approach is to connect a pull down resistor to TRST or to connect it to PORESET with a resistor If bounday scan is required the JTAG controller should drive TRST to the negated state 1 value following PORESET 22 9 Boundary Scan Register The MPC555 MPC556 scan chain implementation has a 346 bit boundary scan reg ister This register contains bits fo...

Page 762: ...ll I Obs 1 1 MUX G1 1 1 Mux G1 C D C D FROM LAST CELL CLOCK DR UPDATE DR SHIFT DR 1 EXTEST CLAMP DATA FROM TO OUTPUT BUFFER 0 OTHERWIZE LOGIC SYSTEM TO NEXT CELL 1 1 MUX G1 C D FROM LAST CELL CLOCK DR DATA TO SYSTEM LOGIC INPUT PIN SHIFT DR TO NEXT CELL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 763: ...ins that are associated with them Below in Table 22 3 is the bit order starting 1 1 MUX G1 C D C D FROM LAST CELL CLOCK DR UPDATE DR SHIFT DR 1 EXTEST CLAMP OUTPUT TO OUTPUT BUFFER 0 OTHERWISE LOGIC FROM SYSTEM TO NEXT CELL CONTROL 1 1 MUX G1 I O PIN FROM LAST CELL OUTPUT DATA INPUT DATA OUTPUT ENABLE I Obs En FROM SYSTEM LOGIC O Pin I O CTL TO NEXT PIN PAIR TO NEXT CELL Freescale Semiconductor I ...

Page 764: ... pin type The last column in dicates the associated boundary scan register control bit for bi directional output pins Bi directional pins include two scan cells for data IO Cell as depicted in Figure 22 8 These bits are controlled by the cell shown in Figure 22 7 The value of the control bit controls the output function of the bidirectional pin One or more bidirectional data cells can be serially ...

Page 765: ...g265 ctl 31 IO ctl g265 ctl 32 IO PIN b_tpuch15 io g266 ctl 33 IO ctl g266 ctl 34 IO PIN b_t2clk io g267 ctl 35 IO ctl g267 ctl 36 IO PIN a_t2clk io g268 ctl 37 IO ctl g268 ctl 38 IO PIN a_tpuch0 io g269 ctl 39 IO ctl g269 ctl 40 IO PIN a_tpuch1 io g302 ctl 41 IO ctl g302 ctl 42 IO PIN a_tpuch2 io g303 ctl 43 IO ctl g303 ctl 44 IO PIN a_tpuch3 io g304 ctl 45 IO ctl g304 ctl 46 IO PIN a_tpuch4 io g...

Page 766: ...O PIN a_tpuch12 io g313 ctl 63 IO ctl g313 ctl 64 IO PIN a_tpuch13 io g314 ctl 65 IO ctl g314 ctl 66 IO PIN a_tpuch14 io g315 ctl 67 IO ctl g315 ctl 68 IO PIN a_tpuch15 io g316 ctl 69 IO ctl g316 ctl 70 i obs a_an0_anw_pqb0 i 71 i obs a_an1_anx_pqb1 i 72 i obs a_an2_any_pqb2 i 73 i obs a_an3_anz_pqb3 i 74 i obs a_an48_pqb4 i 75 i obs a_an49_pqb5 i 76 IO PIN a_an50_pqb6 io g333 ctl 77 IO ctl g333 c...

Page 767: ...1 ctl 93 IO ctl g341 ctl 94 IO PIN a_an59_pqa7 io g342 ctl 95 IO ctl g342 ctl 96 i obs b_an0_anw_pqb0 i 97 i obs b_an1_anx_pqb1 i 98 i obs b_an2_any_pqb2 i 99 i obs b_an3_anz_pqb3 i 100 i obs b_an48_pqb4 i 101 i obs b_an49_pqb5 i 102 IO PIN b_an50_pqb6 io g349 ctl 103 IO ctl g349 ctl 104 IO PIN b_an51_pqb7 io g350 ctl 105 IO ctl g350 ctl 106 IO PIN b_an52_ma0_pqa0 io g351 ctl 107 IO ctl g351 ctl 1...

Page 768: ... i obs etrig1 i 124 IO PIN mda11 io g365 ctl 125 IO ctl g365 ctl 126 IO PIN mda12 io g366 ctl 127 IO ctl g366 ctl 128 IO PIN mda13 io g367 ctl 129 IO ctl g367 ctl 130 IO PIN mda14 io g368 ctl 131 IO ctl g368 ctl 132 IO PIN mda15 io g369 ctl 133 IO ctl g369 ctl 134 IO PIN mda27 io g370 ctl 135 IO ctl g370 ctl 136 IO PIN mda28 io g371 ctl 137 IO ctl g371 ctl 138 IO PIN mda29 io g372 ctl 139 IO ctl g...

Page 769: ... IO ctl g410 ctl 156 IO PIN mpwm18 io g411 ctl 157 IO ctl g411 ctl 158 IO PIN mpwm19 io g412 ctl 159 IO ctl g412 ctl 160 IO PIN mpio32b5 io g413 ctl 161 IO ctl g413 ctl 162 IO PIN mpio32b6 io g414 ctl 163 IO ctl g414 ctl 164 IO PIN mpio32b7 io g415 ctl 165 IO ctl g415 ctl 166 IO PIN mpio32b8 io g416 ctl 167 IO ctl g416 ctl 168 IO PIN mpio32b9 io g417 ctl 169 IO ctl g417 ctl 170 IO PIN mpio32b10 io...

Page 770: ...PIN vf2_mpio32b2 io g426 ctl 187 IO ctl g426 ctl 188 IO PIN vfls0_mpio32b3 io g427 ctl 189 IO ctl g427 ctl 190 IO PIN vfls1_mpio32b4 io g428 ctl 191 IO ctl g428 ctl 192 o pin a_cntx0 o 193 i obs a_cnrx0 i 194 IO PIN pcs0_ss_b_qgpio0 io g435 ctl 195 IO ctl g435 ctl 196 IO PIN pcs1_qgpio1 io g436 ctl 197 IO ctl g436 ctl 198 IO PIN pcs2_qgpio2 io g437 ctl 199 IO ctl g437 ctl 200 IO PIN pcs3_qgpio3 io...

Page 771: ...b io 219 o pin sreset_b io g465 ctl 220 IO ctl g465 ctl 221 i obs hreset_b io 222 o pin hreset_b io g466 ctl 223 IO ctl g466 ctl 224 IO PIN rstconf_b_texp io g467 ctl 225 IO ctl g467 ctl 226 i obs irq7_b_modck3 i 227 i obs irq6_b_modck2 i 228 IO PIN irq5_b_sgpioc5_modck1 io g503 ctl 229 IO ctl g503 ctl 230 IO PIN data_sgpiod 16 io g112 ctl 231 IO ctl g112 ctl 232 IO PIN data_sgpiod 17 io g112 ctl ...

Page 772: ...PIN data_sgpiod 9 io g111 ctl 248 IO PIN data_sgpiod 24 io g524 ctl 249 IO ctl g524 ctl 250 IO PIN data_sgpiod 25 io g525 ctl 251 IO ctl g525 ctl 252 IO PIN data_sgpiod 6 io g110 ctl 253 IO PIN data_sgpiod 7 io g110 ctl 254 IO PIN data_sgpiod 26 io g528 ctl 255 IO ctl g528 ctl 256 IO PIN data_sgpiod 27 io g529 ctl 257 IO ctl g529 ctl 258 IO PIN data_sgpiod 4 io g110 ctl 259 IO PIN data_sgpiod 5 io...

Page 773: ...tl 280 IO PIN addr_sgpioa 23 io g101 ctl 281 IO PIN addr_sgpioa 22 io g101 ctl 282 IO PIN addr_sgpioa 30 io g102 ctl 283 IO PIN addr_sgpioa 21 io g101 ctl 284 IO PIN addr_sgpioa 20 io g101 ctl 285 IO PIN addr_sgpioa 8 io g100 ctl 286 IO ctl g100 ctl 287 IO PIN addr_sgpioa 31 io g102 ctl 288 IO PIN addr_sgpioa 19 io g101 ctl 289 IO PIN addr_sgpioa 18 io g101 ctl 290 IO PIN addr_sgpioa 9 io g100 ctl...

Page 774: ...8 IO PIN tsiz1 io g130 ctl 309 IO PIN tsiz0 io g130 ctl 310 IO ctl g130 ctl 311 IO PIN tea_b io g214 ctl 312 IO ctl g214 ctl 313 o pin oe_b o 314 IO PIN rd_wr_b io g131 ctl 315 IO ctl g131 ctl 316 o pin cs3_b o 317 o pin cs2_b o 318 o pin cs1_b o 319 o pin cs0_b o 320 o pin we_b_at 3 o 321 o pin we_b_at 2 o 322 o pin we_b_at 1 o 323 o pin we_b_at 0 o 324 IO PIN br_b_vf1_iwp2 io g227 ctl 325 IO ctl...

Page 775: ... 335 IO ctl g232 ctl 336 IO PIN irq2_b_cr_b_sgpioc2 io g233 ctl 337 IO ctl g233 ctl 338 IO PIN irq4_b_at2_sgpioc4 io g234 ctl 339 IO ctl g234 ctl 340 IO PIN irq3_b_kr_b_retry_b_sgpio c3 io g237 ctl 341 IO ctl g237 ctl 342 o pin iwp0_vfls0 o 343 o pin iwp1_vfls1 o 344 IO PIN sgpioc6_frz_ptr_b io g240 ctl 345 IO ctl g240 ctl Table 22 3 Boundary Scan Bit Definition Continued Bit Cell Type Pin Cell Na...

Page 776: ...PC556 IEEE 1149 1 COMPLIANT INTERFACE JTAG MOTOROLA USER S MANUAL Rev 15 October 2000 22 22 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 777: ...ial Purpose Registers Table A 2 CMF CDR MoneT Flash EEPROM Flash Array Table A 3 USIU Unified System Interface Unit Table A 4 CMF CDR MoneT Flash EEPROM Table A 5 DPTRAM Dual Port TPU RAM Table A 6 DPTRAM Array Table A 7 TPU3 Time Processor Unit Table A 8 QADC64 Queued Analog to Digital Converter Table A 9 QSMCM Queued Serial Multi Channel Module Table A 10 MIOS1 Modular Input Output Subsystem Tab...

Page 778: ...egister 1 See 3 9 7 Machine Status Save Restore Register 1 SRR1 for bit descriptions 32 U SPR 80 S EIE External Interrupt Enable Register See 3 9 10 1 EIE EID and NRI Special Pur pose Registers for bit descriptions 32 SPR 81 S EID External Interrupt Disable Register See 3 9 10 1 EIE EID and NRI Special Pur pose Registers for bit descriptions 32 SPR 82 S NRI Non Recoverable Interrupt Register See 3...

Page 779: ...r bit descriptions 32 U SPR 273 S SPRG1 General Special Purpose Registers See 3 9 8 General SPRs SPRG0 SPRG3 for bit descriptions 32 U SPR 274 S SPRG2 General Special Purpose Registers See 3 9 8 General SPRs SPRG0 SPRG3 for bit descriptions 32 U SPR 275 S SPRG3 General Special Purpose Registers See 3 9 8 General SPRs SPRG0 SPRG3 for bit descriptions 32 U SPR 284 285 S write only TB Time Base Regis...

Page 780: ...ster 1 See Table 4 6 for bit descriptions 32 U SPR 818 S MI_RA2 Region Attribute Register 2 See Table 4 6 for bit descriptions 32 U SPR 819 S MI_RA3 Region Attribute Register 3 See Table 4 6 for bit descriptions 32 U SPR 824 S L2U_RA0 L2U Region 0 Attribute Register See Table 11 9 for bit descriptions 32 POR H SPR 825 S L2U_RA1 L2U Region 1 Attribute Register See Table 11 9 for bit descriptions 32...

Page 781: ...t descriptions 32 S 0x2F C024 U SGPIODT1 USIU General Purpose I O Data Register 1 See Table 6 21 for bit descriptions 32 H 0x2F C028 U SGPIODT2 USIU General Purpose I O Data Register 2 See Table 6 22 for bit descriptions 32 H 0x2F C02C U SGPIOCR USIU General Purpose I O Control Register See Table 6 23 for bit descriptions 32 H 0x2F C030 U EMCR External Master Mode Control Register See Table 6 12 f...

Page 782: ... 0x2F C21C Reserved 0x2F C220 U4 RTCSC Real Time Clock Status and Control See Table 6 17 for bit descriptions 16 H 0x2F C224 U4 RTC Real Time Clock See 6 13 4 6 Real Time Clock Register RTC for bit descriptions 32 U 0x2F C228 T4 RTSEC Real Time Alarm Seconds reserved 32 0x2F C22C U4 RTCAL Real Time Alarm See 6 13 4 7 Real Time Clock Alarm Regis ter RTCAL for bit descriptions 32 U 0x2F C230 0x2F C2...

Page 783: ...F C320 U RTCSCK Real Time Clock Status and Control Key See Table 8 8 for bit descriptions 32 POR 0x2F C324 U RTCK Real Time Clock Key See Table 8 8 for bit descriptions 32 POR 0x2F C328 U RTSECK Real Time Alarm Seconds Key See Table 8 8 for bit descriptions 32 POR 0x2F C32C U RTCALK Real Time Alarm Key See Table 8 8 for bit descriptions 32 POR 0x2F C330 0x2F C33C Reserved 0x2F C340 U PISCRIK PIT S...

Page 784: ... reset Table A 4 CMF CDR MoneT Flash EEPROM Address Access Symbol Register Size Reset CMF_A 0x2F C800 S1 NOTES 1 Bit 3 FIC is write once Bit 0 LOCK is write once unless in freeze or test mode CMFMCR CMF_A EEPROM Configuration Register See Table 19 2 for bit descriptions 32 POR H 0x2F C804 S CMFTST CMF_A EEPROM Test Register See Table 19 3 for bit descriptions 32 POR H 0x2F C808 S CMFCTL CMF_A EEPR...

Page 785: ... Multiple Input Signature Register High See 18 3 4 MISR High MISRH and MISR Low MISRL for bit descriptions 16 S 0x30 0008 S read only MISRL Multiple Input Signature Register Low See 18 3 4 MISR High MISRH and MISR Low MISRL for bit descriptions 16 S 0x30 000A S read only MISCNT MISC Counter See 18 3 5 MISC Counter MISCNT for bit descriptions 16 S Table A 6 DPTRAM Array Address Access Symbol Regist...

Page 786: ...Selection Register 2 See Table 17 11 for bit descriptions 162 S M 0x30 4012 S CFSR3_A TPU_A Channel Function Selection Register 3 See Table 17 11 for bit descriptions 162 S M 0x30 4014 S U3 HSQR0_A TPU_A Host Sequence Register 0 See Table 17 12 for bit descriptions 162 S M 0x30 4016 S U3 HSQR1_A TPU_A Host Sequence Register 1 See Table 17 12 for bit descriptions 162 S M 0x30 4018 S U3 HSRR0_A TPU_...

Page 787: ... Registers 16 322 0x30 4190 0x30 419F S U3 TPU_A Channel 9 Parameter Registers 16 322 0x30 41A0 0x30 41AF S U3 TPU_A Channel 10 Parameter Registers 16 322 0x30 41B0 0x30 41BF S U3 TPU_A Channel 11 Parameter Registers 16 322 0x30 41C0 0x30 41CF S U3 TPU_A Channel 11 Parameter Registers 16 322 0x30 41D0 0x30 41DF S U3 TPU_A Channel 11 Parameter Registers 16 322 0x30 41E0 0x30 41EF S U3 TPU_A Channel...

Page 788: ...0 4428 S4 TPUMCR2_B TPU_B Module Configuration Register 2 162 S M 0x30 442A S TPUMCR3_B TPU_B Module Configuration Register 3 16 322 S M 0x30 442C T ISDR_B TPU_B Internal Scan Data Register 16 322 0x30 442E T ISCR_B TPU_B Internal Scan Control Register 16 322 0x30 4500 0x30 450E S U3 TPU_B Channel 0 Parameter Registers 16 322 0x30 4510 0x30 451E S U3 TPU_B Channel 1 Parameter Registers 16 322 0x30...

Page 789: ... Size Reset QADC_A Note Bit descriptions apply to QADC_B as well 0x30 4800 S QADC64MCR_A QADC64 Module Configuration Register See Table 13 7 for bit descriptions 16 S 0x30 4802 T QADC64TEST_ A QADC64 Test Register 16 0x30 4804 S QADC64INT_A Interrupt Register See Table 13 8 for bit descriptions 16 S 0x30 4806 S U PORTQA_A PORTQB_A Port A and Port B Data See Table 13 9 for bit descriptions 16 U 0x3...

Page 790: ...ata and Port B Direction Register 16 S 0x30 4C0A S U QACR0_B QADC64 Control Register 0 16 S 0x30 4C0C S U1 QACR1_B QADC64 Control Register 1 16 S 0x30 4C0E S U1 QACR2_B QADC64 Control Register 2 16 S 0x30 4C10 S U QASR0_B QADC64 Status Register 0 16 S 0x30 4C12 S U QASR1_B QADC64 Status Register 1 16 S 0x30 4C14 0x30 4DFE Reserved 0x30 4E00 0x30 4E7E S U CCW_B Conversion Command Word Table 16 U 0x...

Page 791: ...16 S U PQSPAR DDRQST QSMCM Port QS PIn Assignment Register QSMCM Port QS Data Direction Register See Table 14 11 for bit descriptions 16 S 0x30 5018 S U SPCR0 QSPI Control Register 0 See Table 14 13 for bit descriptions 16 S 0x30 501A S U SPCR1 QSPI Control Register 1 See Table 14 15 for bit descriptions 16 S 0x30 501C S U SPCR2 QSPI Control Register 2 See Table 14 16 for bit descriptions 16 S 0x3...

Page 792: ...0 600A S U MPWMSMPULR MPWMSM1 Pulse Register See Table 15 21 for bit descriptions 16 X 0x30 600C S U MPWMSMCNTR MPWMSM1 Count Register See Table 15 22 for bit descriptions 16 X 0x30 600E S U MPWMSMSCR MPWMSM1 Status Control Register See Table 15 23 for bit descriptions 16 S MPWMSM2 MIOS Pulse Width Modulation Submodule 2 0x30 6010 S U MPWMSMPERR MPWMSM2 Period Register See Table 15 20 for bit desc...

Page 793: ...t descriptions 16 S 0x30 605E S U MDASMSCR MDASM11 Status Control Register See Table 15 17 for bit descriptions 16 S MDASM12 MIOS Double Action Submodule 12 0x30 6060 S U MDASMAR MDASM12 Data A Register See 15 11 1 1 MDASM Data A Register for bit descriptions 16 X 0x30 6062 S U MDASMBR MDASM12 Data B Register See 15 11 1 2 MDASM Data B Register MDASMBR for bit descriptions 16 X 0x30 6064 S U MDASM...

Page 794: ...e 15 11 1 3 MDASM Status Control Reg ister Duplicated for bit descriptions 16 S 0x30 607E S U MDASMSCR MDASM15 Status Control Register See Table 15 17 for bit descriptions 16 S MPWMSM16 MIOS Pulse Width Modulation Submodule 16 0x30 6080 S U MPWMSMPERR MPWMSM16 Period Register See Table 15 20 for bit descriptions 16 X 0x30 6082 S U MPWMSMPULR MPWMSM16 Pulse Register See Table 15 21 for bit descript...

Page 795: ...SM Modulus Latch Register See Table 15 12 for bit descriptions 16 X 0x30 60B4 S U MMCSMSCRD MMCSM Status Control Register Duplicated See 15 10 1 3 MMCSM Status Control Reg ister Duplicated for bit descriptions 16 S 0x30 60B6 S U MMCSMSCR MMCSM Status Control Register See Table 15 14 for bit descriptions 16 S MDASM27 MIOS Double Action Submodule 27 0x30 60D8 S U MDASMAR MDASM27 Data A Register See ...

Page 796: ... MDASM Data B Register MDASMBR for bit descriptions 16 X 0x30 60F4 S U MDASMSCRD MDASM30 Status Control Register Duplicat ed See 15 11 1 3 MDASM Status Control Reg ister Duplicated for bit descriptions 16 S 0x30 60F6 S U MDASMSCR MDASM30 Status Control Register See Table 15 17 for bit descriptions 16 S MDASM31 MIOS Double Action Submodule 31 0x30 60F8 S U MDASMAR MDASM31 Data A Register See 15 11 ...

Page 797: ...nterrupt Enable Register See Table 15 30 for bit descriptions 16 S 0x30 6C06 S read only MIOS1RPR0 MIRSM0 Request Pending Register See Table 15 31 for bit descriptions 16 S MIRSM MIOS Interrupt Request Submodule 0x30 6C30 S MIOS1LVL0 MIOS1 Interrupt Level Register 0 See Table 15 7 for bit descriptions 16 S MIRSM1 MIOS Interrupt Request Submodule 1 0x30 6C40 S MIOS1SR1 MIRSM1 Interrupt Status Regis...

Page 798: ... descriptions 16 S 0x30 7092 S U RXGMSKLO_A TouCAN_A Receive Global Mask Low See Table 16 20 for bit descriptions 16 S 0x30 7094 S U RX14MSKHI_A TouCAN_A Receive Buffer 14 Mask High See 16 7 10 Receive Buffer 14 Mask Regis ters for bit descriptions 16 S 0x30 7096 S U RX14MSKLO_A TouCAN_A Receive Buffer 14 Mask Low See 16 7 10 Receive Buffer 14 Mask Regis ters for bit descriptions 16 S 0x30 7098 S ...

Page 799: ...16 4 for mes sage buffer definitions U 0x307180 0x30718F S U MBUFF8_A TouCAN_A Message Buffer 8 See Figure 16 3 and Figure 16 4 for mes sage buffer definitions U 0x307190 0x30719F S U MBUFF9_A TouCAN_A Message Buffer 9 See Figure 16 3 and Figure 16 4 for mes sage buffer definitions U 0x3071A0 0x3071AF S U MBUFF10_A TouCAN_A Message Buffer 10 See Figure 16 3 and Figure 16 4 for mes sage buffer defi...

Page 800: ...LO_B TouCAN_B Receive Buffer 15 Mask Low 16 S 0x30 749C 0x30 749E Reserved 0x30 74A0 S U ESTAT_B TouCAN_B Error and Status Register 16 S 0x30 74A2 S U IMASK_B TouCAN_B Interrupt Masks 16 S 0x30 74A4 S U IFLAG_B TouCAN_B Interrupt Flags 16 S 0x30 74A6 S U RXECTR_B TXECTR_B TouCAN_B Receive Error Counter TouCAN_B Transmit Error Counter 16 S 0x307500 0x30750F S U MBUFF0_B TouCAN_B Message Buffer 0 U ...

Page 801: ... H 0x30 7F90 S T UTSTCREG Test Register Reserved 32 0x30 7FA0 S read only UIPEND Pending Interrupt Request Register See Table 12 7 for bit descriptions 32 H Table A 13 SRAM Static RAM Access Memory Address Access Symbol Register Size Reset SRAM_A 0x38 0000 S1 NOTES 1 Bit 0 LCK locks the register write protected except in test mode and is write once SRAMMCR_A SRAM_A Module Configuration Register Se...

Page 802: ...cess Memory Array Address Access Symbol Register Size Reset 0x3F 8000 0x3F 97FF Reserved 0x3F 9800 0x3F BFFF U S SRAM_A RAM Array 10 K Bytes 8 16 32 0x3F C000 0x3F FFFF U S SRAM_B RAM Array 16 K Bytes 8 16 32 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 803: ... 16 CFSR2 TPU3 channel function select register 2 17 16 CFSR3 TPU3 channel function select register 3 17 16 CIER TPU3 channel interrupt enable register 17 15 CISR TPU3 channel interrupt status register 17 19 CMF EEPROM configuration register CMFMCR 19 5 EEPROM control registers 19 4 EEPROM high voltage control register CMFCTL 19 9 CMFCFIG hard reset configuration word 19 17 CMFCTL CMF EEPROM high ...

Page 804: ...se register DMBR 10 31 Dual mapping option register 10 32 E ECR exception cause register 21 54 EMCR external master control register 6 22 ESTAT error and status register 16 30 Exception cause register ECR 21 53 External master control register EMCR 6 22 F FPRs floating point registers 3 12 FPSCR floating point status and control register 3 13 G General Purpose I O registers 6 34 GPRs general purpo...

Page 805: ...status control register 15 23 MDASMSCRD MDASM status control register duplicated 15 22 Memory controller base registers BR0 BR3 10 28 Memory controller option registers OR0 OR3 10 30 Memory controller status registers MSTAT 10 28 MI_GRA global region attribute register 4 23 MIOS 16 bit parallel port I O submodule MPIOSM Registers 15 30 bus interface MBISM Registers 15 8 counter prescaler submodule...

Page 806: ... direction register MPIOSMDDR 15 31 data register MPIOSMDR 15 30 MPIOSMDDR MPIOSM data direction register 15 31 MPIOSMDR MPIOSM data register 15 31 MPWMSM counter register MPWMSMCNTR 15 28 period register MPWMSMPERR 15 27 pulse width register MPWMSMPULR 15 27 status control register MPWMSMCR 15 28 MPWMSMCNTR MPWMSM counter register 15 28 MPWMSMPERR MPWMSM period register 15 27 MPWMSMPULR MPWMSM pu...

Page 807: ...figuration register QMCR 14 7 interrupt level registers QDSCI_IL QSPI_IL 14 8 port QS data register PORTQS 14 10 PORTQS data direction register DDRQS 14 12 PORTQS pin assignment register PQSPAR 14 11 QSCI1 control register QSCI1CR 14 59 QSCI1 status register QSCI1SR 14 61 QSPI command RAM CRx 14 22 QSPI control register 0 SPCR0 14 16 QSPI control register 1 SPCR1 14 18 QSPI control register 2 SPCR...

Page 808: ... RJURR right justified unsigned result register 13 49 RSR reset status register 7 5 RTC real time clock alarm register 6 31 RTC real time clock register 6 31 RTCSC real time clock status and control register 6 30 RXECTR receive error counter 16 33 RXGMSKHI receive global mask register high 16 29 S SCCR system clock control register 8 30 SCCxR0 QSMCM SCI control register 0 14 45 SCCxR1 QSMCM SCI co...

Page 809: ...trol and status register TBSCR 6 29 Time base reference registers TBREF0 6 29 TIMER free running timer register 16 29 TouCAN control register 0 CANCTRL0 16 25 control register 1 CANCTRL1 16 26 control register 2 CANCTRL2 16 28 error and status register ESTAT 16 30 interrupt configuration register CANICR 16 24 interrupt flag register IFLAG 16 33 interrupt mask register IMASK 16 32 module configurat...

Page 810: ...CR3 TPU3 module configuration register 3 17 21 Transfer error status register TESR 6 27 U UIMB module configuration register UMCR 12 7 pending interrupt request register UIPEND 12 8 test control register UTSTCREG 12 8 UIPEND UIMB pending interrupt reqiuest register 12 8 UMCR UIMB module configuration register 12 7 V VDDSRM sensor register VSRMSR 8 36 VSRMSR VDDSRM control register 8 36 X XER integ...

Page 811: ...9 5 CMPA CMPD comparator A D value register 21 45 CMPE CMPF comparator E F value registers 21 46 CMPG CMPH comparator G H value registers 21 46 COLIR change of lock interrupt register 8 35 COUNTA breakpoint counter A value and control register 21 52 COUNTB breakpoint counter B value and control register 21 53 CPR0 TPU3 channel priority register 0 17 18 CPR1 TPU3 channel priority register 1 17 18 C...

Page 812: ... A register 15 21 MDASMBR MDASM data B register 15 22 MDASMSCR MDASM status control register 15 23 MDASMSCRD MDASM status control register duplicated 15 22 MI_GRA global region attribute register 4 23 MIOS1ER0 MIRSM0 interrupt enable register 15 35 MIOS1ER1 interrupt enable register 15 37 MIOS1LVL0 MIOS1 interrupt level register 0 15 11 MIOS1LVL1 MIOS1 interrupt level 1 register 15 11 MIOS1MCR MIO...

Page 813: ... register 13 33 QADC64MCR QADC64 module configuration register 13 33 QASR0 QADC64 status register 0 13 41 13 42 QDSCI_IL QSM2 dual SCI interrupt level register 14 8 QSCI1CR QSCI1 control register 14 59 QSCI1SR QSCI1 status register 14 61 QSMCMMCR QSMCM module configuration register 14 7 QSPI_IL QSPI interrupt level register 14 9 R RAMBAR ram array base address register 18 5 Regionattribute registe...

Page 814: ...ce register 6 27 SYPCR system protection control register 6 26 T TB time base 3 19 3 23 6 29 TBREF0 time base reference register 0 6 29 TBREF1 time base reference register 1 6 29 TBSCR time base control and status register 6 30 TESR transfer error status register 6 27 TICR TPU3 interrupt configuration register 17 14 TIMER free running timer register 16 29 TPUMCR TPU3 module configuration register ...

Page 815: ...Memory Map The TPU3 can address up to eight Kbytes of memory at any one time It has four Kbytes of internal ROM located in Bank 0 and Bank 1 and six Kbytes of dual ported SRAM DPTRAM located in Bank 0 Bank 1and Bank 2 As only one type of memory can be used at a time the TPU3 must either use the internal ROM or the SRAM Func tions from both memory types cannot be used in conjunction Bank 1 Bank 0 0...

Page 816: ...ault entry table in Bank 0 are listed in Table D 1 The functions in the entry table in bank one are listed in Table D 2 Table D 1 Bank 0 Functions Function Number Function Nickname Function Name 0xF PTA Programmable Time Accumulator 0xE QOM Queued Output Match 0xD TSM Table Stepper Motor 0xC FQM Frequency Measurement 0xB UART Universal Asynchronous Receiver Transmitter 0xA NITC New Input Capture I...

Page 817: ... entry table using the soft reset feature of the TPU3 The procedure should be 1 Set ETBANK field in TPUMCR2 to 0b01 to select the entry table in Bank 1 2 Run the ID function 3 Stop the TPU3 by setting the STOP bit in the TPUMCR to one 4 Reset the TPU3 by setting the SOFTRST bit in the TPUMCR2 register 5 Wait at least nine clocks 6 Clear the SOFTRST bit in the TPUMCR2 register The TPU3 stays in res...

Page 818: ...input signal over a programmable number of periods or pulses The period accumulation can start on a rising or falling edge After the specified number of periods or pulses the PTA generates an interrupt request From one to 255 period measurements can be accumulated before the TPU interrupts the CPU providing instantaneous or average frequency measurement capability See Motorola TPU Progamming Note ...

Page 819: ...x30YY1C 0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupts Disabled 0x30YY0A 1 Channel Interrupts Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Interrupt Asserted PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 CHANNEL_CONTROL 0x30YYW2 MAX_COUNT PERIOD_COUNT 0x30YYW4 LAST_TIME 0x30YYW6 A...

Page 820: ...ng waveforms with high times of 0 or 100 QOM also allows a TPU channel to be used as a discrete output pin See Motorola TPU Progamming Note Queued Output Match TPU Function QOM TPUPN01 D Figure D 3 shows all of the host interface areas for the QOM function The bit encod ings shown in Table D 3 describe the corresponding fields in parameter RAM Table D 3 QOM Bit Encoding A Timebase Selection 0 Use ...

Page 821: ...nnel Interrupt Enable 0 Channel Interrupts Disabled 0x30YY0A 1 Channel Interrupts Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Interrupt Asserted PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 REF_ADDR B LAST_OFF_ADDR A 0x30YYW2 LOOP_CNT OFF_PTR C LAST_MATCH_TM 0x30YYW4 OFFSET_1 0x30YYW6 OFFSET_2 0x30YYW8 OFFSET_3 0x30YYWA OFFSET_4 0x30YYWC O...

Page 822: ...independent of the acceleration table The CPU need only write a desired position and the TPU accelerates slews and deceler ates the motor to the required position Full and half step support is provided for two phase motors In addition a slew rate parameter allows fine control of the terminal run ning speed of the motor independent of the acceleration table See Motorola TPU Pro gamming Note Table S...

Page 823: ...iority 00 Disabled 0x30YY1C 0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupts Disabled 0x30YY0A 1 Channel Interrupts Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Interrupt Asserted PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 DESIRED_POSITION 0x30YYW2 CURRENT_POSITION 0x30YYW4 TABLE...

Page 824: ...Disabled 0x30YY0A 1 Channel Interrupts Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Interrupt Asserted PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YY W 1 0 ACCEL_RATIO_2 ACCEL_RATIO_1 0x30YY W 1 2 ACCEL_RATIO_4 ACCEL_RATIO_3 0x30YY W 1 4 ACCEL_RATIO_6 ACCEL_RATIO_5 0x30YY W 1 6 ACCEL_RATIO_8 ACCEL_RATIO_7 0x30YY W 1 8 ACCEL_RATIO_10 ACCEL_RATIO...

Page 825: ...ndows in continuous mode The user selects whether to detect pulses on the rising or falling edge This function is intended for high speed measure ment measurement of slow pulses with noise rejection can be made with PTA See Motorola TPU Progamming Note Frequency Measurement TPU Function FQM TPUPN03 D Figure D 6 shows all of the host interface areas for the FQM function Freescale Semiconductor I Fr...

Page 826: ...Bits 00 No Host Service Reset Condition 0x30YY18 0x30YY1A 01 Not Used 10 Initialize 11 Not Used 1 0 cChannel Priority 00 Disabled 0x30YY1C 0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Interrupt Asserted PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 0x30YYW2 0x30YYW4 CHANEL_CONTROL 0x30YYW...

Page 827: ...en odd and no parity Baud rate is freely programmable and can be higher than 100 Kbaud Eight bi directional UART channels running in excess of 9600 baud could be implemented on the TPU See Motorola TPU Progamming Note Asynchronous Serial Interface TPU Function UART TPUPN07 D Figure D 7 and Figure D 8 show all of the host interface areas for the UART function in transmitting and receiving modes res...

Page 828: ...High Priority 0 Channel Interrupt Enable 0 Channel Interrupts Disabled 0x30YY0A 1 Channel Interrupts Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Interrupt Asserted PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 PARITY_TEMP 0x30YYW2 MATCH_RATE 0x30YYW4 TDRE TRANSMIT_DATA_REG 0x30YYW6 DATA_SIZE 0x30YYW8 ACTUAL_BIT_COUNT 0x30YYWA SHIFT_REGISTER...

Page 829: ... High Priority 0 Channel Interrupt Enable 0 Channel Interrupts Disabled 0x30YY0A 1 Channel Interrupts Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Interrupt Asserted PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 PARITY_TEMP 0x30YYW2 MATCH_RATE 0x30YYW4 PE RE TRANSMIT_DATA_REG 0x30YYW6 DATA_SIZE 0x30YYW8 ACTUAL_BIT_COUNT 0x30YYWA SHIFT_REGIST...

Page 830: ...tions are maintained in parameter RAM A channel can perform input captures continually or a channel can detect a single transition or specified number of transitions ceasing channel activity until reinitialization After each transition or specified number of transitions the channel can generate a link to other channels See Motorola TPU Progamming Note New Input Capture Input Transition Counter TPU...

Page 831: ... 01 Low Priority 10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupts Disabled 0x30YY0A 1 Channel Interrupts Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Interrupt Asserted PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 CHANNEL_CONTROL 0x30YYW2 START_LINK_ CHANNEL LINK_CHAN NEL_COUNT PARAM_ADDR 0 0x30YYW4 MAX_CO...

Page 832: ...ence is implemented as a user configurable state machine thus pro viding a flexible approach with other general applications A CPU offset parameter is provided to allow all the switching angles to be advanced or retarded on the fly by the CPU This feature is useful for torque maintenance at high speeds See Motorola TPU Progamming Note Multiphase Motor Commutation TPU Function COMM TPUPN09 D Figure...

Page 833: ...10 Initialize or Force State 11 Initialize or Force Immediate State Test 1 0 cChannel Priority 00 Disabled 0x30YY1C 0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Interrupt Asserted PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 START_LINK_ CHANNEL COUNTER_ADDR 0x30YYW2 NO_OF_STATES STATE_NO...

Page 834: ...ost interface areas for the HALLD function CONTROL BITS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YY W 1 0 LENGTH STATE 0 PIN_CONFIG 0x30YY W 1 2 LENGTH STATE 1 PIN_CONFIG 0x30YY W 1 4 LENGTH STATE 2 PIN_CONFIG 0x30YY W 1 6 LENGTH STATE 3 PIN_CONFIG 0x30YY W 1 8 LENGTH STATE 4 PIN_CONFIG 0x30YY W 1 A LENGTH STATE 5 PIN_CONFIG 0x30YY W 1 C LENGTH STATE 6 PIN_CONFIG 0x30YY W 1 E LENGTH STATE 7 PIN_C...

Page 835: ...tialize 2 Channel Mode 11 Initialize 3 Channel Mode 1 0 cChannel Priority 00 Disabled 0x30YY1C 0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Status x Not Used 0x30YY20 PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 0x30YYW2 0x30YYW4 0x30YYW6 DIRECTION 1 0x30YYW8 STATE_NO_ADDR 2 0x30YYWA PINSTATE 0x30YYWC 0x30YYWE Written By CPU Written by CPU and T...

Page 836: ...high time alignment edge aligned and center aligned Edge aligned mode uses n 1 TPU channels for n PWMs center aligned mode uses 2n 1 channels Center aligned mode allows a user de fined dead time to be specified so that two PWMs can be used to drive an H bridge without destructive current spikes This feature is important for motor control applica tions See Motorola TPU Progamming Note Multichannel ...

Page 837: ...itialize as Slave Inverted 10 Initialize as Slave Normal 11 Initialize as Master 1 0 cChannel Priority 00 Disabled 0x30YY1C 0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Interrupt Asserted PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 PERIOD 0x30YYW2 IRQ_RATE PERIOD_COUNT 0x30YYW4 LAST_RIS...

Page 838: ...rity 00 Disabled 0x30YY18 0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable 0 Channel Interrupts Disabled 0x30YY1C 0x30YY1E 1 Channel Interrupts Enabled 0 cChannel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Interrupt Asserted PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 PERIOD 0x30YYW2 HIGH_TIME 0x30YYW4 0x30YYW6 HIGH...

Page 839: ...0x30YY1A 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable 0 Channel Interrupts Disabled 0x30YY1C 0x30YY1E 1 Channel Interrupts Enabled 0 cChannel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Interrupt Asserted PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 PERIOD 0x30YYW2 NXT_B_RISE_TIME 0x30YYW4 NXT_B_FALL_TIME 0x30YYW6 DEAD_TIM...

Page 840: ...Disabled 0x30YY1C 0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable 0 Channel Interrupts Disabled 0x30YY0A 1 Channel Interrupts Enabled 0 cChannel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Interrupt Asserted PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 HIGH_TIME 0x30YYW2 CURRENT_HIGH_TIME 0x30YYW4 TEMP_STORAGE 0x30YY...

Page 841: ...8 0x30YY1A 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable 0 Channel Interrupts Disabled 0x30YY1C 0x30YY1E 1 Channel Interrupts Enabled 0 cChannel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Interrupt Asserted PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 PERIOD 0x30YYW2 NXT_B_RISE_TIME 0x30YYW4 NXT_B_FALL_TIME 0x30YYW6 DEAD_T...

Page 842: ...Disabled 0x30YY1C 0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable 0 Channel Interrupts Disabled 0x30YY0A 1 Channel Interrupts Enabled 0 cChannel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Interrupt Asserted PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 HIGH_TIME 0x30YYW2 CURRENT_HIGH_TIME 0x30YYW4 TEMP_STORAGE 0x30YY...

Page 843: ...als to be decoded A time stamp is provided on every counter update to allow position interpolation and better velocity determination at low speed or when low resolution encoders are used The third index channel provided by some encoders is handled by the ITC function See Motorola TPU Progamming Note Fast Quadrature Decode TPU Function FQD TPUPN02 D Figure D 19 and Figure D 20 show the host interfa...

Page 844: ...tialize 1 0 cChannel Priority 00 Disabled 0x30YY1C 0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable x Not Used 0x30YY0A 0 cChannel Interrupt Status xx Not Used 0x30YY20 PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 EDGE_TIME 0x30YYW2 POSITION_COUNT 0x30YYW4 TCR1_VALUE 0x30YYW6 CHAN_PINSTATE 0x30YYW8 CORR_PINSTATE_ADDR 0x30YYWA EDGE_TIME_LSB_AD...

Page 845: ...TCR1 11 Initialize 1 0 cChannel Priority 00 Disabled 0x30YY1C 0x30YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable x Not Used 0x30YY0A 0 cChannel Interrupt Status xx Not Used 0x30YY20 PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 0x30YYW2 0x30YYW4 TCR1_VALUE 0x30YYW6 CHAN_PINSTATE 0x30YYW8 CORR_PINSTATE_ADDR 0x30YYWA EDGE_TIME_LSB_ADDR 0x30YYWC 0x...

Page 846: ...ncy measurement and the latest complete accumulation over the programmed number of periods The pulse width high time portion of an input signal can be measured up to 24 bits and added to a previous measurement over a programmable number of periods one to 255 This provides an instantaneous or average pulse width measurement capa bility allowing the latest complete accumulation over the specified nu...

Page 847: ... cInterrupt Status 0x30YY20 PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 START_LINK_ CHANNEL LINK_CHANNEL _COUNT CHANNEL_CONTROL 0x30YYW2 MAX_COUNT PERIOD_COUNT 0x30YYW4 LAST_ACCUM 0x30YYW6 ACCUM 0x30YYW8 ACCUM_RATE PPWA_UB 0x30YYWA PPWA_LW 0x30YYWC 0x30YYWE Written By CPU Written by CPU and TPU W Channel Number YY 41 for TPU_A and 44 for TPU_B Written By TPU Unused Parameters NOTE...

Page 848: ... channel OC references without CPU interaction a specifiable period and calculates an offset where RATIO is a parameter supplied This algorithm generates a 50 duty cycle continuous square wave with each high low time equal to the calculated OFFSET Due to offset calculation there is an initial link time before continuous pulse generation begins See Motorola TPU Progamming Note Output Compare TPU Fu...

Page 849: ...0YY18 0x30YY1A 01 Host Initiated Pulse 10 Not Used 11 Initialize Continuous Pulses 0 cInterrupt Enable 0 Interrupt Not Asserted 0x30YY0A 1 Interrupt Asserted 0 cInterrupt Status 0x30YY20 PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 CHANNEL_CONTROL 0x30YYW2 OFFSET 0x30YYW4 RATIO REF_ADDR1 0 0x30YYW6 REF_ADDR2 0 REF_ADDR3 0 0x30YYW8 REF_TIME 0x30YYWA ACTUAL_MATCH_TIME 0x30YYWC TCR1 0...

Page 850: ...cates the period and another parameter that indicates the high time Updates to one or both of these pa rameters can direct the waveform change to take effect immediately or coherently beginning at the next low to high transition of the pin See Motorola TPU Progam ming Note Pulse Width Modulation TPU Function PWM TPUPN17 D Figure D 23 shows the host interface areas and parameter RAM for the PWM fun...

Page 851: ...0YY18 0x30YY1A 01 Immediate Update of PWM 10 Initialize 11 Not Used 0 cInterrupt Enable 0 Interrupt Not Asserted 0x30YY0A 1 Interrupt Asserted 0 cInterrupt Status 0x30YY20 PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 CHANNEL_CONTROL 0x30YYW2 OLDRIS 0x30YYW4 PWMHI 1 3 0x30YYW6 PWMPER 2 3 0x30YYW8 PWMRIS 0x30YYWA 0x30YYWC 0x30YYWE c Written By CPU c Written by CPU and TPU W Channel N...

Page 852: ...s the next most recent state and so on The programmer can choose one of the three following conditions to update the pa rameter 1 when a transition occurs 2 when the CPU makes a request or 3 when a rate specified in another parameter is matched When a pin is used as a discrete output it is set high or low only upon request by the CPU See Motorola TPU Progamming Note Discrete Input Output TPU Funct...

Page 853: ...Not Used 1 0 cHost Service Bits 00 Not Used 0x30YY18 0x30YY1A 01 Drive Pin High 10 Drive Pin Low 11 Initialize 0 cInterrupt Enable 0 Interrupt Not Asserted 0x30YY0A 1 Interrupt Asserted 0 cInterrupt Status 0x30YY20 PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 CHANNEL_CONTROL 0x30YYW2 PIN_LEVEL 0x30YYW4 MATCH_RATE 0x30YYW6 0x30YYW8 0x30YYWA 0x30YYWC 0x30YYWE Written By CPU Written b...

Page 854: ...ex timing relationships between channels without CPU intervention The SPWM output waveform duty cycle excludes 0 and 100 If a PWM does not need to maintain a time relationship to another PWM the PWM function should be used instead See Motorola TPU Progamming Note Synchronized Pulse Width Modulation TPU Function SPWM TPUPN19 D Figure D 25 and Figure D 26 show all of the host interface areas for the...

Page 855: ... Request 0x30YY18 0x30YY1A 01 Not Used 10 Initialize 11 Immediate Update Mode 1 0 cInterrupt Enable 0 Interrupt Not Asserted 0x30YY0A 1 Interrupt Asserted 0 cInterrupt Status 0x30YY20 PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 LASTRISE CHANNEL_CONTROL 0x30YYW2 NEXTRISE 0x30YYW4 HIGH_TIME 0x30YYW6 PERIOD 0x30YYW8 REF_ADDR1 0x30YYWA DELAY 0x30YYWC 0x30YYWE Written By CPU Written by...

Page 856: ...M MODE 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 LASTRISE CHANNEL_CONTROL 0x30YYW2 NEXTRISE 0x30YYW4 HIGH_TIME 0x30YYW6 PERIOD 0x30YYW8 START_LINK_ CHANNEL LINK_CHANNEL _COUNT REF_ADDR1 0x30YYWA DELAY 0x30YYWC 0x30YYWE Written By CPU Written by CPU and TPU W Channel Number YY 41 for TPU_A and 44 for TPU_B Written By TPU Unused Parameters Figure D 26 SPWM Parameters Part 2 of 2 Freescale Sem...

Page 857: ...ceives links and upon receipt will read the two TCRs into PRAM updating the pinstate parameter A maskable interrupt request to the CPU is generated The CPU can control the channel pin the channel pin and the TCRs or just the TCRs To control the pin only the read TCR option is used and the values returned ignored Controlling the TCRs without effect on the pin allows this function to be run on a TPU...

Page 858: ...0YY1E 01 Low Priority 10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupts Disabled 0x30YY0A 1 Channel Interrupts Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Interrupt Asserted PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 0x30YYW2 0x30YYW4 CHANNEL_CONTROL 0x30YYW6 CHANNEL_PIN_STATE 0x30YYW8 TCR1_VALUE 0x30YYW...

Page 859: ...PU Function ID This is a simple function that returns the version of the TPU ROM on the current device Figure D 28 shows all of the host interface areas for the ID function Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 860: ...ty 10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupts Disabled 0x30YY0A 1 Channel Interrupts Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 0x30YY20 1 Channel Interrupt Asserted PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 TPU3_ID ROM_REVISION 0x30YYW2 0x30YYW4 0x30YYW6 0x30YYW8 0x30YYWA 0x30YYWC 0x30YYWE Written By CPU Written ...

Page 861: ...ceive three channels operating modes 2 Baud rate period is freely programmable over a 15 bit range of TCR1 counts 3 Selection of msb or lsb first shift direction 4 Variable transfer size from one to 16 bits 5 Clock polarity is programmable When a transfer of data is complete the SIOP function notifies the host CPU by issuing an interrupt request The arrangement of the multiple SIOP channels is fix...

Page 862: ...as and parameter RAM for the SIOP func tion The following sections describe these parameters Note that only the clock chan nel requires any programming the data in and out channels are entirely under TPU microcode control Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 863: ...e 1 0 cHost Service Bits 00 No Host Service Reset Condition 0x30YY18 0x30YY1A 01 No Action 10 No Action 11 Initialize Clock Channel and Start Transfer 0 cInterrupt Enable 0 Interrupt Not Asserted 0x30YY0A 1 Interrupt Asserted 0 cInterrupt Status 0 Interrupt Not Asserted 0x30YY20 1 Interrupt Asserted PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30YYW0 S CHANNEL_CONTROL 0x30YYW2 HALF PERIOD...

Page 864: ...COUNT This parameter is used by the TPU to count down the number bits remaining while a transfer is in progress During the SIOP initialization state BIT_COUNT is loaded with the value contained in XFER_SIZE It is then decremented as the data is transferred and when it reaches zero the transfer is complete and the TPU issues an interrupt re quest to the CPU D 19 1 5 XFER_SIZE This CPU written param...

Page 865: ...ng H M or L priority to the clock channel via the two channel priority bits The TPU then starts the data transfer and issues an interrupt request when the trans fer is complete Once the function has been initialized the CPU only needs to write SIOP_DATA with the new data and issue a HSR 0b11 to initiate a new transfer In input or clock only modes just the HSR 0b11 is required D 19 3 SIOP Function ...

Page 866: ...data input is latched exactly on the opposite clock edge This is the simplest way to show the examples but is not strictly true Since the TPU is a multi tasking system and the data channels are manipulated directly by microcode software while servicing the clock edge there is a finite delay between the relevant clock edge and the data out being valid or the data in being latched This delay is equi...

Page 867: ... device A transmitting device must also hold data valid for a minimum time of Td after the clock Figure D 31 SIOP Function Data Transition Example DATA OUT ch a n x 1 CLO C K ch a n x DATA IN ch a n x 1 Td Td Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 868: ...MPC555 MPC556 TPU ROM FUNCTIONS MOTOROLA USER S MANUAL Rev 15 October 2000 D 54 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 869: ... describes how the clock supplies and external components should be connected in the board These guidelines must be fulfilled to reduce switching noise which is generated on internal and external buses during op eration Any noise injected into the sensitive clock and PLL logic reduces clock perfor mance The USIU maintains a PLL loss of lock warning indication that can be used to determine the cloc...

Page 870: ...OTE 3 All 100 nF capacitors should be placed close to the pin MPC555 MPC556 1 for each pad 8 total 1 for each pad 4 total shorted to vss Main Supply NOTE 1 The main power supply may optionally supply operating current to reduce the keep alive current requirements See the circuit in 8 12 1 System Clock Control Register SCCR NOTE 2 Resistor R1 is currently not required Space should be left on the bo...

Page 871: ...DDA VSSA Vrh Vrl An Analog Input Keyed Vcc 5 V 100 nF 1uF 1nF 10k Ω 50 Ω 50 Ω To From Sensors 100 nF 10 nF R2 Sensors NOTE The size of resistor R2 depends on the sensor load current It should be sized to match the voltage at Vrh MPC555 MPC556 100 nF Analog ground plane Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 872: ... Different Crystals Q1 Component NDK CP32C 20 MHz KINSEKI CX 11F 20 MHz MURATA CCSTC 4 MHz Units CL 1 NOTES 1 CL according to crystal specification CL CX CY 6 14 pF R1 3 1MEG3 1MEG3 1MEG3 Ohm CX 6 16 2 2 The Murata ceramic resonator includes the load capacitors 8pF should be selected 3 Resistor R1 is currently not required Space should be left on the board to add it in the future if necessary pF C...

Page 873: ...pacitors taken into account is 10 E 3 2 KAPWR Filtering KAPWR pin is the MPC555 MPC556 keep alive power KAPWR is used for the crys tal oscillator circuit and should be isolated from the noisy supplies It is recommended that an RC filter be used on KAPWR or bypass capacitors which are located as close as possible to the part Figure E 4 RC Filter Example CXX CYY 2CL CXX CX Cpad Csocket CYY CY Cpad C...

Page 874: ...solated from all other noisy signals in the board VDDSYN could be isolated with RC filter see Figure E 1 or LC filter The maximum noise allowed on VDDSYN and VSSSYN is 50 mV with typical cut off frequency of 500 Hz Figure E 6 RC Filter Example KAPWR BOARD MPC555 MPC556 VSSSYN KAP 3 V 100 nF 1 µF VDDSYN BOARD MPC555 MPC556 VSSSYN Keyed 100 nF 10 Ω Vcc 3 V Freescale Semiconductor I Freescale Semicon...

Page 875: ...in the PLPRCR register refer to Table 8 10 1 0 MF 1 4 CXFC 680 x MF 1 120 pF 2 MF 1 4 CXFC 1100 x MF 1 pF Figure E 8 PLL Off Chip Capacitor Example E 4 Clock Oscillator and PLL External Components Layout Requirements E 4 1 Traces and Placement Traces connecting capacitors crystal resistor should be as short as possible There fore the components crystal resistor and capacitors should be placed as c...

Page 876: ...he supplies should be located as close as possible to the chip package It is recommended to design individual VSSSYN plane to improve VSSSYN quietness E 4 2 Grounding Guarding The traces from the oscillator pins and PLL pins of the MPC555 MPC556 should be guarded from all other traces to reduce crosstalk It can be provided by keeping other traces away from the oscillator circuit and placing a grou...

Page 877: ...external bus to U bus is four clocks external master case All IMB accesses are assumed to be 16 bit accesses only If 32 bit accesses are used then each such IMB access is split into two separate 16 bit cycles with nor mal IMB performance for each Table F 1 Memory Access Times Using Different Buses INTERNAL EXTERNAL RAM FLASH SHOW CYCLE FLASH RAM IMB SIU Internal Memory Mapped External Non mapped I...

Page 878: ... page 3 concecutive accesses C U 2 U2 2 Core instruction fetch data bus is usualy the UBUS C U 1 U C U 1 U Instruction Fetch cmf new page Load Store IMB C U 2 U L U IMB 6 IMB U L Instruction Fetch cmf new page Load Store IMB C U 6 U L U IMB 6 IMB U L External Bus cmf new page E U 5 U E External Bus IMB E U IMB 7 IMB U E Instruction Fetch cmf 2 concecutive accesses External Bus cmf C U 2 U C 3 3 8 ...

Page 879: ...V Oscillator Keep Alive Reg Supply Voltage1 KAPWR 6 0 4 0 V SRAM Supply Voltage1 VDDSRAM 6 0 4 0 V Clock Synthesizer Supply Voltage1 VDDSYN 6 0 4 0 V QADC Supply Voltage4 VDDA 6 0 6 0 V 5 V Supply Voltage VDDH 0 3 6 0 V DC Input Voltages5 VIN VSS 0 3 VDDH 0 3 V Reference Supply VRH with Reference to VRL VRH VRL 0 3 6 0 V VSS Differential Voltage VSS VSSA 0 1 0 1 V VDD Differential Voltage6 VDDL VD...

Page 880: ...awing or contact Motorola For die characteristics contact the Motorola factory G 4 EMI Characteristics G 4 1 Reference Documents The documents referenced for the EMC testing of MPC555 MPC556 are listed below 1 SAE J1752 3 Issued 1995 03 2 VDE UK 767 14 ZVEI Ad Hoc HL AK Version1 0 May 1994 G 4 2 Definitions and Acronyms EMC Electromagnetic compatibility EMI Electromagnetic interference TEM cell Tr...

Page 881: ... convection RθMA 30 43 4 3 Junction temperature is a function of on chip power dissipation package thermal resistance mounting site board temperature ambient temperature air flow power dissipation of other components on the board and the board thermal resistance 4 Per JESD51 6 with the board horizontal C W BGA Package Thermal Resistance Junction to Board RθJB 19 95 5 Thermal resistance between the...

Page 882: ...in stance the user can change the air flow around the device add a heat sink change the mounting arrangement on printed circuit board or change the thermal dissipation on the printed circuit board surrounding the device This description is most useful for ceramic packages with heat sinks where some 90 of the heat flow is through the case to the heat sink to ambient For most packages a better model...

Page 883: ...re of the device in the application after prototypes are available the thermal characterization parameter ΨJT can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation TJ TT ΨJA x PD where TT thermocouple temperature on top of package C RθJA thermal characterization parameter PD power dissipation in pa...

Page 884: ...alue Units ESD Target for Human Body Model HBM 2000 V HBM Circuit Description R1 1500 Ω C 100 pF ESD Target for Machine Model MM 200 V MM Circuit Description R1 0 Ω C 200 pF Number of Pulses Per Pin Positive Pulses MM Negative Pulses MM Positive Pulses HBM Negative Pulses HBM 3 3 1 1 Interval of Pulses 1 Second Notes 1 All ESD testing is in conformity with CDF AEC Q100 Stress Test Qualification fo...

Page 885: ...XTCLK VIL3 VSS 0 3 0 8 V 3 V Input Low Voltage EXTCLK VIL3C VSS 0 3 0 4 V 5 V Input Low Voltage VIL5 VSS 0 3 0 4 VDDH V 5 V Input Low Voltage QADC PQA PQB VILA5 VSSA 0 3 0 4 VDDA V Muxed 3 V 5 V Pins GPIO Muxed with Addr Port A Data Port D and Control Port C 3 V Input Low Voltage Addr Port A Data Port D Control Port C 5 V Input Low Voltage GPIO VIL3M VIL5M VSS 0 3 VSS 0 3 0 8 0 4 VDDH V V QADC Ana...

Page 886: ...V Output Low Voltage IOL 3 2 mA 5 V Output Low Voltage IOL 2 mA VOL3M VOL5M 0 5 0 45 V Output Low Current CLKOUT VOL 0 5 V IOL 2 0 mA Output High Current CLKOUT VOH 2 4 V IOH 2 0 mA CLKOUT Capacitance 40 MHz COM 1 0 of SCCR 0b01 COM 1 0 of SCCR 0b00 Cclk 305 90 pF ENGCLK Capacitance 20Mhz EECLK 1 0 of SCCR 0b01 EECLK 1 0 of SCCR 0b00 Ceng 255 506 pF Capacitance for Input Output and Bidirectional V...

Page 887: ...DDSRAM VDDSYN Crystal Frequency 20 Mhz VDDF 9 IDDL IDDKAP IDDSRM IDDSYN IDDF IDDL IDDKAP IDDSRM IDDSYN IDDF 250 8 0 2 0 2 0 10 250 8 0 2 0 2 10 mA Operating Current 5 V Supplies 40 MHz VDDH VDDA 12 VPP 10 IDDH5 IDDA IDDVPP 20 5 0 30 mA QADC64 Low Power Stop Mode VDDA IDDA 10 µA Low Power Current 40 MHz VDDI DOZE Active PLL and Active Clocks SLEEP Active PLL with Clocks off DEEP SLEEP13 PLL and Clo...

Page 888: ...Current TJ 90 C VDDSRAM Only RAM Standby Current TJ 90 C with Low Voltage Protection Circuitry VDDSRAM Only RAM Standby Current TJ 150 C 4 100 150 250 mA µA µA µA RAM Standby Voltage for Data Retention Powered down Mode Specified VDD Applied VDD VSS VDDSRAM 1 417 3 6 V DC Injection Current per Pin GPIO TPU MIOS QSM EPEE and 5 V 18 19 IIC5 1 0 1 0 mA DC Injection Current Per Pin 3 V 18 19 IIC3 1 0 ...

Page 889: ...13 This parameter is periodically sampled rather than 100 tested 14 KAPWR and VDDSRAM are powered up prior to any other supply 15 To obtain full range results VSSA VRL VINDC VRH VDDA 16 To obtain full range results VSSA VRL VINDC VRH VDDA 17 The voltage at which the LVSRS bits in the VSRMCR register will be set ranges from 1 5 2 4 V 18 All injection current is transferred to the VDDH An external l...

Page 890: ...LOCK 500 Input Clocks PLL Operating Range FVCOOUT 30 80 MHz Crystal Operating Range MODCK 1 3 0b010 or 0b110 MODCK 1 3 0b001 0b011 0b100 0b101 0b111 FCRYSTAL 2 15 5 25 MHz PLL Jitter PLL Jitter averaged over 10 µs MF 20 FJIT FJIT10 1 0 3 1 0 3 Limp Mode Clock Frequency FLIMP 31 NOTES 1 Values to be evaluated upon further characterization 7 121 MHz Oscillator Bias Current XTAL 4 MHz 20 MHz IBIAS 0 ...

Page 891: ...sed on initial device characterization and may not be tested in production Pulses PPULSE 5 0 Vpp Number of Program Pulses VPP 5 00 800 7000 Pulses PPULSE 5 25 Vpp Number of Program Pulses VPP 5 25 250 20003 3 The best case fastest programming time of 50 pulses is at VPP 5 25 V and TA 125 C Pulses TPROG Program Pulse Time 48 50 256 5 µS CPULSE 4 75 Vpp Number of CENSOR Clear Pulses VPP 4 75 47 87 7...

Page 892: ...ltaneously 100 301 301 µA mA mA Table G 8 Flash Module Life Symbol Meaning Value P E Cycles1 NOTES 1 Target failure rate at specified number of program erase cycles of 2 ppm pending characterization of production silicon Maximum Number of Program Erase Cycles2 to Guarantee Data Retention Array Blocks 2 A program erase cycle is defined as switching the bits from 1 0 1 1003 4 3 Reprogramming of a CM...

Page 893: ...s 0 101 1 Mode 5NL 20 50 µs 0 110 1 Mode 6NL max 48 000 50 µs 0 111 1 Mode 7NL Table G 10 CMF Erase Algorithm v6 No of Pulses Pulse Width NVR PAWs GDB PAWs Mode Description 1 100 ms1 NOTES 1 No margin read after pulse 1 100 1 Mode 4NL Negative gate ramp low range 1 100 ms1 1 101 1 Mode 5NL 1 100 ms1 1 110 1 Mode 6NL 1 100 ms1 1 111 1 Mode 7NL 1 100 ms1 0 100 1 Mode 4NL Negative gate ramp high rang...

Page 894: ...H VIL VIH VIH VIL VIL VIH VIH VIL VIL VIH VIH VIL VIL VIH A B C D C D A Maximum Output Delay Characteristic B Minimum Output Hold Time C Minimum input Setup Time Characteristic D Minimum input Hold Time Characteristic OUTPUTS VIH VIL VIL VIH A B VIL Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 895: ...e 5 5 ns 5a ENGCLK Fall Time 20 20 ns 6 Circuit Parameter TCC 8 7 75 ns 7 CLKOUT to Signal Invalid Hold Time A 0 31 RD WR BURST D 0 31 0 2TC 1 0 5 4 ns 7a CLKOUT to Signal Invalid Hold Time TSIZ 0 1 RSV AT 0 3 BDIP 0 2TC 1 0 5 4 ns 7b CLKOUT to Signal Invalid Hold Time 3 BR BG FRZ VFLS 0 1 VF 0 2 IWP 0 2 LWP 0 1 PTR RETRY STS4 0 2TC 1 0 5 4 ns 7c Slave mode CLKOUT to Signal Invalid D 0 31 0 25TC T...

Page 896: ... 25 13 ns 10 CLKOUT to TS BB Assertion 0 25TC TCC 7 5 15 6 25 14 ns 10a CLKOUT to TA BI Assertion When Driven by the Memory Controller 10 10 ns 10b CLKOUT to RETRY Assertion When Driven by the Memory Controller 10 10 ns 11 CLKOUT to TS BB Negation 0 25TC TCC 7 5 15 6 25 14 ns 11a CLKOUT to TA BI Negation When Driven by the Memory Controller 11 11 ns 11b CLKOUT to RETRY Negation When Driven by the ...

Page 897: ... 2 ns 16a CLKOUT to Signal Invalid Hold Time RETRY KR CR 2 2 ns 17 Signal Valid to CLKOUT Rising Edge Setup Time D 0 31 6 7 6 ns 18 CLKOUT Rising Edge to Signal Invalid Hold Time D 0 31 6 1 1 ns 19 CLKOUT Rising Edge to CS asserted GPCM ACS 00 0 25TC TCC 1 7 5 16 6 25 14 ns 19a CLKOUT Falling Edge to CS Asserted GPCM ACS 10 TRLX 0 or 1 TCC 1 9 8 ns 19b CLKOUT Falling Edge to CS Asserted GPCM ACS 1...

Page 898: ... 9 8 ns 25a CLKOUT Falling Edge to WE 0 3 BE 0 3 Negated GPCM Write Access TRLX 0 or 1 CSNT 1 EBDF 0 0 25TC TCC 1 7 5 6 25 5 14 ns 25b CLKOUT Falling Edge to CS Negated GPCM Write Access TRLX 0 or 1 CSNT 1 ACS 10 or ACS 11 EBDF 0 0 25TC TCC 1 7 5 16 5 14 ns 25c CLKOUT Falling Edge to WE 0 3 BE 0 3 Negated GPCM Write Access TRLX 0 CSNT 1 EBDF 1 0 25TC TCC 4 7 5 20 6 25 17 ns 25d CLKOUT Falling Edge...

Page 899: ... 26g CS Negated to D 0 31 Signal invalid GPCM Write Access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 1 12 5 ns 26h WE 0 3 BE 0 3 Negated to D 0 31 Signal invalid GPCM Write Access TRLX 1 CSNT 1 EBDF 1 30 24 ns 26i CS Negated to D 0 31 Signal invalid GPCM Write Access TRLX 1 CSNT 1 ACS 10 or ACS 11 EBDF 1 30 24 ns 27 CS WE 0 3 Negated to A 0 31 Invalid GPCM Write Access7 0 0 ns 27a WE 0 3 BE 0 3 Negated ...

Page 900: ...This is the maximum frequency at which ENGCLK will meet output drive and rise fall time specifications 3 The timing for BR ouput is relevant when the MPC555 MPC556 is selected to work with external bus arbiter The timing for BG output is relevant when the MPC555 MPC556 is selected to work with internal bus arbiter 4 The setup times required for TA TEA and BI are relevant only when they are supplie...

Page 901: ...RACTERISTICS MOTOROLA USER S MANUAL Rev 15 October 2000 G 23 Figure G 2 External Clock Timing CLKOUT 1 1 3 2 4 5 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 902: ...AL Rev 15 October 2000 G 24 Figure G 3 Synchronous Output Signals Timing 8 8a 7b 9 9 7a 7 8b OUTPUT SIGNALS CLKOUT OUTPUT SIGNALS OUTPUT SIGNALS Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 903: ...ev 15 October 2000 G 25 Figure G 4 Synchronous Active Pull Up and Open Drain Outputs Signals Timing CLKOUT TS BB TA BI TEA 10 12 11 10a 12a 11a 13 14 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 904: ... S MANUAL Rev 15 October 2000 G 26 Figure G 5 Synchronous Input Signals Timing CLKOUT TA BI TEA KR RETRY CR BB BG BR 15 16 15a 16a 15b 16 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 905: ...S MOTOROLA USER S MANUAL Rev 15 October 2000 G 27 Figure G 6 Input Data Timing in Normal Case CLKOUT TA D 0 31 15a 16 17 18 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 906: ...ev 15 October 2000 G 28 Figure G 7 External Bus Read Timing GPCM Controlled ACS 00 CLKOUT TS A 0 31 CSx OE WE 0 3 D 0 31 8 10 19 22 11 20 23 17 18 25 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 907: ...v 15 October 2000 G 29 Figure G 8 External Bus Read Timing GPCM Controlled TRLX 0 ACS 10 CLKOUT TS A 0 31 CSx OE D 0 31 8 10 19a 22 11 20 23 17 18 21 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 908: ...15 October 2000 G 30 Figure G 9 External Bus Read Timing GPCM Controlled TRLX 0 ACS 11 19c 19b CLKOUT TS A 0 31 CSx OE D 0 31 8 10 22 11 20 23 17 18 21a Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 909: ...ober 2000 G 31 Figure G 10 External Bus Read Timing GPCM Controlled TRLX 1 ACS 10 ACS 11 8 19a 11 20 23 17 18 24 24a 19b 19c 10 CLKOUT TS A 0 31 CSx OE D 0 31 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 910: ...ICS MOTOROLA USER S MANUAL Rev 15 October 2000 G 32 Figure G 11 Address Show Cycle Bus Timing 11 10 8 9 CLKOUT TS A 0 31 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 911: ...ANUAL Rev 15 October 2000 G 33 Figure G 12 Address and Data Show Cycle Bus Timing 8 10 11 20 9 8 26 26b 27 D 0 31 CLKOUT TS A 0 31 CSx WE 0 3 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 912: ...ober 2000 G 34 Figure G 13 External Bus Write Timing GPCM Controlled TRLX 0 CSNT 0 8 10 19 22 11 20 25 9 23 8 26 26b 27 D 0 31 OE WE 0 3 CSx A 0 31 TS CLKOUT Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 913: ...5 Figure G 14 External Bus Write Timing GPCM Controlled TRLX 0 CSNT 1 8 10 19 22 11 20 9 23 8 26a 25a 25b 26c 27a 27c 25d 26g 26g 25c D 0 31 OE WE 0 3 CSx A 0 31 TS CLKOUT Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 914: ...Figure G 15 External Bus Write Timing GPCM Controlled TRLX 1 CSNT 1 8 10 19 22 11 20 9 23 8 26d 25a 25b 26e 26b 27b 27d 25d 26i 26h 25c D 0 31 OE WE 0 3 CSx TS CLKOUT A 0 31 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 915: ...G 37 Figure G 16 External Master Read from Internal Registers Timing 28 10a 12a 11a 13 14 9 8 10b 11b RETRY D 0 31 TEA TA BI A 0 31 TSIZ 0 1 RD WR BURST TS CLKOUT 29 30 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 916: ... 38 Figure G 17 External Master Write to Internal Registers Timing 29 28 30 10a 12a 11a 13 14 28a 18 10b 11b RETRY D 0 31 TEA TA BI A 0 31 TSIZ 0 1 RD WR BURST TS CLKOUT Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 917: ...TES 1 The timings 31 and 32 describe the testing conditions under which the IRQ lines are tested when being defined as level sensitive The IRQ lines are synchronized internally and do not have to be asserted or negated with ref erence to the CLKOUT 10 10 ns 32 IRQx Hold Time After CLKOUT1 2 2 ns 33 IRQx Pulse Width Low 3 3 ns 34 IRQx Pulse Width High 3 3 ns 35 IRQx Edge to Edge Time 4 TC 121 100 n...

Page 918: ...c Expression 33MHz 40MHz Unit Min Max Min Max 36 DSCK Cycle Time 120 60 ns 37 DSCK Clock Pulse Width 50 25 ns 38 DSCK Rise and Fall Times 0 3 0 3 ns 39 DSDI Input Data Setup Time 12 12 ns 40 DSDI Data Hold Time 5 5 ns 41 DSCK low to DSDO Data Valid 0 18 0 18 ns 42 DSCK low to DSDO Invalid 0 0 ns 35 33 34 31 35 CLKOUT IRQx Freescale Semiconductor I Freescale Semiconductor Inc For More Information O...

Page 919: ...STICS MOTOROLA USER S MANUAL Rev 15 October 2000 G 41 Figure G 20 Debug Port Clock Input Timing 36 36 37 37 38 38 DSCK Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 920: ...TERISTICS MOTOROLA USER S MANUAL Rev 15 October 2000 G 42 Figure G 21 Debug Port Timings 40 42 41 39 DSDO DSDI DSCK Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 921: ...d in Table G 4 The simplest way to insure meeting this requirement in systems that require the use of the TEXP func tion is to connect RSTCONF TEXP to SRESET The maximum rise time of HRESET should be less than six clock cycles 60 50 ns 50 HRESET and RSTCONF Asserted to Data Out Drive 25 25 ns 51 RSTCONF Negated to Data Out High Impedance 25 25 ns 52 CLKOUT of Last Rising Edge Before Chip Tristates...

Page 922: ...SER S MANUAL Rev 15 October 2000 G 44 Figure G 22 Reset Timing Configuration from Data Bus 46 48 49 45 47 49a D 0 31 IN RSTCONF HRESET Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 923: ...L Rev 15 October 2000 G 45 Figure G 23 Reset Timing Data Bus Weak Drive During Configuration 50 51 52 43 55 CLKOUT HRESET RSTCONF D 0 31 OUT Weak Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 924: ...A USER S MANUAL Rev 15 October 2000 G 46 Figure G 24 Reset Timing Debug Port Configuration 53 44 54 54 53 55 DSCK DSDI SRESET CLKOUT Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 925: ...5 ns 60 TMS TDI Data Hold Time 25 25 ns 61 TCK Low to TDO Data Valid 20 20 ns 62 TCK Low to TDO Data Invalid 0 0 ns 63 TCK Low to TDO High Impedance 20 20 ns 64 TRST Assert Time 100 100 ns 65 TRST Setup Time to TCK Low 40 40 ns 66 TCK Falling Edge to Output Valid 50 50 ns 67 TCK Falling Edge to Output Valid out of High Impedance 50 50 ns 68 TCK Falling Edge to Output High Impedance 50 50 ns 69 Bou...

Page 926: ...ERISTICS MOTOROLA USER S MANUAL Rev 15 October 2000 G 48 Figure G 25 JTAG Test Clock Input Timing TCK 56 56 57 57 58 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 927: ...OTOROLA USER S MANUAL Rev 15 October 2000 G 49 Figure G 26 JTAG Test Access Port Timing Diagram 60 62 59 61 63 TDO TMS TDI TCK Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 928: ...RACTERISTICS MOTOROLA USER S MANUAL Rev 15 October 2000 G 50 Figure G 27 JTAG TRST Timing Diagram TCK TRST 65 64 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 929: ...MANUAL Rev 15 October 2000 G 51 Figure G 28 Boundary Scan JTAG Timing Diagram 66 67 68 69 70 OUTPUT SIGNALS TCK OUTPUT SIGNALS OUTPUT SIGNALS Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 930: ...c assumes that adequate low pass filtering is present on analog input pins capacitive filter with 0 01 µF to 0 1 µF capacitor between analog input and analog ground typical source isolation imped ance of 10 Kbytes 9 Input signals with large slew rates or high frequency noise components cannot be converted accurately These signals may affect the conversion accuracy of other channels AE 2 0 2 0 Coun...

Page 931: ...ternal capacitance Error from junction leakage is a function of external source impedance and input leakage current In the following expression expected error in result value due to junction leakage is expressed in voltage Verrj Verrj RS IOFF where IOFF is a function of operating temperature Charge sharing leakage is a function of input source impedance conversion rate change in voltage between su...

Page 932: ...tro 10 20 2 1 50 100 25 µs ns ns ns 121 Fall Time Input Output up to 50 pF Load SLRC Bit of PDMCR 0 up to 200 pF Load SLRC Bit of PDMCR 0 up to 50 pF SLRC Bit of PDMCR 1 tfi tfo 10 20 2 1 50 100 25 µs ns ns ns NOTES 1 All AC timing is tested to the 5 V levels outlined in Table G 4 2 TC is defined to be the clock period of fSYS IMB Clock 3 For high time n External SCK rise time for low time n Exter...

Page 933: ...MISO INPUT MOSI OUTPUT SCK CPOL 0 OUTPUT SCK CPOL 1 OUTPUT 111 110 113 121 120 112 109 114 115 111 120 121 119 118 121 120 QSPI MAST CPHA1 MSB PCS 3 0 OUTPUT MISO INPUT MSB MSB OUT DATA LSB OUT PORT DATA PORT DATA MOSI OUTPUT DATA LSB IN MSB IN SCK CPOL 0 OUTPUT SCK CPOL 1 OUTPUT 111 110 113 120 121 109 112 109 115 112 120 121 114 119 118 121 120 Freescale Semiconductor I Freescale Semiconductor I...

Page 934: ...SCK CPOL 1 INPUT MISO OUTPUT MOSI INPUT QSPI SLV CPHA0 111 110 121 120 113 112 109 111 120 121 116 119 118 119 117 114 115 121 QSPI SLV CPHA1 SS INPUT DATA SLAVE LSB OUT PD MSB OUT MSB IN DATA LSB IN PD MISO OUTPUT SCK CPOL 1 INPUT MOSI INPUT SCK CPOL 0 INPUT 114 115 121 118 119 117 111 113 109 111 120 121 116 118 110 112 121 120 Freescale Semiconductor I Freescale Semiconductor Inc For More Infor...

Page 935: ... to a 1 under these conditions tri tro 90 2000 3 1 600 7500 25 µs ns ns ns 123 Fall Time Input Output2 SLR0 of PDMCR 0 50 pF to 200 pF Load Output2 SLR0 of PDMCR 0 up to 20 nF Load3 Output SLR0 of PDMCR 1 up to 50 pF Load tfi tfo 90 2000 3 1 600 7500 25 µs ns ns ns Table G 19 TPU3 Timing TA TL to TH Num Rating Symbol Min Max Unit 124 Slew Rate of TPU Output Channel Valid1 2 SLR0 of PDMCR 0 50 pF t...

Page 936: ...ICLOCK Rise tCNRX0 0 ns 129 Rise Time Input Output Up to 50 pF Load SLRC Bit of PDMCR 0 Up to 200 pF Load SLRC Bit of PDMCR 0 Up to 50 pF Load SLRC Bit of PDMCR 1 tri tro 10 20 2 1 50 100 25 µs ns ns ns 130 Fall Time Input Output Up to 50 pF Load SLRC Bit of PDMCR 0 Up to 200 pF Load SLRC bit of PDMCR 0 Up to 50 pF Load SLRC Bit of PDMCR 1 tfi tfo 10 20 2 1 50 100 25 µs ns ns ns Serial Pins tf 1 M...

Page 937: ...egister before rewriting the MCPSMSCR to set the enable bit MCPSMSCR_PREN If this is not done the prescaler will start with the old value in the MCPSMSCR_PSL 3 0 before reloading the new value into the counter vs_pclk is the MIOS prescaler clock which is distributed to all the counter e g MPWMSM and MMCSM submod ules tCPSMC MCPSMSCR_PSL 3 0 12 2 After reset MCPSMSCR_PSL 3 0 is set to 0b0000 IMB Cl...

Page 938: ...also see Note 1 on the MCPSM timing informa tion tPWMP MPWMPERR MPWMPULR 1 256 MPWMSCR_CP MCPSMSCR_PSL 1 MPWMSM Enable to Output Set MIN 5 5 The exact timing from mpwmsm enable to the pin being set depends on the timing of the register write and the MCPSM vs_pclk tPWME MPWMPERR MPWMPULR 256 MPWMSCR_CP MCPSMSCR_PSL 3 255 MPWMSCR_CP MCPSMSCR_PSL 6 6 When MCPSMSCR_PSL 0x0000 this gives a prescale val...

Page 939: ...ure G 37 MPWMSM Enable to MPWMO Output Pin Rising Edge Timing Diagram fSYS bit PREN MIOB vs_pclk tPWMP Prescaler enable 3 4 1 MPWMO output pin Note FSYS is the internal IMB clock for the IMB3 bus fSYS bit tPWME MPWMSCR enable 3 4 1 MPWMO output pin Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 940: ... setting CPSMPSL 3 0 0x2 and MMCSMSCR_CP 7 0 0xFF Counter Bus Overflow Reload to Interrupt Flag tCBFLG 1 MCPSM Enable to Counter Bus Increment tMCMP 256 MMCSMSCR_CP MCPSMSCR_PSL 23 3 When MCPSMSCR_PSL 0x0000 this gives a prescale value of 16 and it is 16 which should be used in these calculations When MCPSMSCR_PSL 0x0001 the CPSM is inactive MMCSM Enable to Counter Bus Increment MIN 4 4 The exact ...

Page 941: ...us Increment Timing Diagram Figure G 41 MMCSM Load Pin to Counter Bus Reload Timing Diagram fSYS MMCSM pin tPHI min tPLO min tPPER min fSYS MMCSM clock pin tPCCB Counter bus 15 0 A A 1 Note FSYS is the internal IMB clock for the IMB3 bus fSYS MMCSM load pin tPLCB Counter bus 15 0 A B Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com ...

Page 942: ...g Diagram Figure G 43 MMCSM Prescaler Clock Select to Counter Bus Increment Timing Diagram fSYS MMCSM interrupt flag tCBFLG Counter bus 15 0 FFFF 5AFE FFFE MMCSMML 15 0 5AFE fSYS MMCSMSCR_CLS 1 0 tMCME Counter bus 15 0 A A 1 3 4 2 1 1 00 11 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 943: ... the counter bus is stable when the input capture occurs the tPCAP has a maximum delay of 2 cycles the 1 cycle uncertainty is due to the synchronizer Input Pin to Interrupt Flag Delay tPFLG 2 3 Input Pin to PIN Delay tPIN 1 2 Counter Bus Resolution tCBR 22 2 Maximum resolution is obtained by setting CPSMPSL 3 0 0x2 and MDASMSCR_CP 7 0 0xFF Output Modes OC OPWM Output Pulse Width3 3 Maximum output ...

Page 944: ...SM Input Pin to MDASM Interrupt Flag Timing Diagram Figure G 47 MDASM Minimum Output Pulse Width Timing Diagram fSYS MDAI input pin tPCAP Counter bus 15 0 A MDASMAR 15 0 XXXX A fSYS MDAI input pin tPFLG MDASM interrupt flag fSYS MDAO output pin tPULW min Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 945: ...gram Figure G 49 Counter Bus to MDASM Interrupt Flag Setting Timing Diagram fSYS MDAO output pin tCBP Counter bus 15 0 5AFD 5AFE 5AFC MDASMAR 15 0 5AFE fSYS MDASM interrupt flag tCBFLG Counter bus 15 0 5AFD 5AFE 5AFC MDASMAR 15 0 5AFE Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 946: ...pend on the rate at which the MPIOSM_DR reg ister is polled MPIOSM Pin Low Time tPLO 1 MPIOSM Pin High Time tPHI 1 Input Pin to MPIOSM_DR Delay tPDR 0 1 Output Mode Output Pulse Width2 2 The minimum output pulse width depends on how quickly the CPU updates the value inside the MIOPSM_DR register The MPC555 RCPU core takes six clock cycles to access the MIOPSM_DR register therefore the minimum outp...

Page 947: ...004 4 The typical number of pulses is at VPP 5 00 v and TA 25 C 10005 5 Assumes pulse width 25 6 µs Pulses PPULSE 5 25 Vpp Number of Program Pulses6 VPP 5 25 6 The best case fastest programming time of 50 pulses is at VPP 5 25 V and TA 125 C 1257 7 The typical number of pulses is at VPP 5 25 V and TA 25 C 5005 Pulses TPROG Program Pulse Time 21 2 25 6 32 0 µS CPULSE 4 75 Vpp Number of CENSOR Clear...

Page 948: ...m or Erase Operation Disabled 22 5 mA VPP External Program or Erase voltage Read Program or Erase VDDF 0 35 4 75 5 5 5 25 V IDDPP External Program and Erase Current1 Read VPP 5 V Program VPP 5 25 V Erase VPP 5 25 V NOTES 1 Average current is less than 30 mA when programming both modules simultaneously 1001 301 301 µA1 mA1 mA1 Program Time vs VPP Temperature 2325 447 140 1180 270 81 438 117 46 1 10...

Page 949: ...fined as switching the bits from 1 0 1 1003 4 3 Reprogramming of a CMF array block prior to erase is not required 4 Number of program erase cycles to be adjusted pending characterization of production silicon Retention Data Retention at Average Operating Temperature of 85 C Minimum 10 years Table H 4 CMF Programming Algorithm v5 No of Pulses Maximum Pulse Width NVR PAWs GDB PAWs Mode Description 3...

Page 950: ...L CHARACTERISTICS FOR ALL J76N MASK SETS AND 0K02A AND 1K02A ONLY MOTOROLA USER S MANUAL Rev 15 October 2000 H 4 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 951: ...7 Boundary scan cells 22 1 descriptor language 22 7 register 22 1 BPU 3 5 BQ2 13 17 13 39 BR 9 7 Branch prediction 3 5 processing unit 3 5 trace enable 3 21 Branch latch control BLC 17 13 Branch processing unit 3 5 Break frame 14 51 Breakpoint asserted flag BKPT 17 14 flag PCBK 17 14 Breakpoint counter A value and control register 21 52 Breakpoint counter B value and control register 21 53 BRKNOMS...

Page 952: ...7 8 17 19 class instruction 3 38 CLKOUT to TA BI assertion when driven by the Memory Controller G 18 CLKOUT 9 7 CLKS 17 13 Clock block diagram 13 26 frequency 13 26 generation 13 24 phase CPHA 14 17 polarity CPOL 14 17 CMPA CMPD 21 45 CMPE CMPF 21 46 CMPG CMPH 21 46 CNRX TX pins 16 2 CNTC 21 52 CNTV 21 52 Code 16 5 Coherency 13 6 13 22 17 4 COMM D 18 Command RAM 14 22 word pointer CWP 13 42 Compar...

Page 953: ...18 Discrete input output DIO D 38 DIV2 17 20 DIV8 clock 17 7 Divide by two control field DIV2 17 20 DIW0EN 21 48 DIW1EN 21 48 DIW2EN 21 48 DIW3EN 21 48 DLW0EN 21 52 DLW1EN 21 52 Double buffered 14 52 14 56 DPI 21 55 DPTRAM 18 4 DSCK 14 23 DSCKL 14 18 DSCR 17 12 DSISR 3 22 3 46 3 51 3 52 DSSR 17 14 DT 14 23 DTL 14 18 DTPU 17 20 E EA 3 33 EBRK 21 55 ECR 21 53 EE bit 3 21 3 26 Effective address 3 33 ...

Page 954: ...xception enable 3 15 for 0 3 14 for 3 14 for 3 14 for 0 0 3 14 for invalid compare 3 14 for invalid integer convert 3 15 for invalid square root 3 15 for SNaN 3 14 for software request 3 15 summary 3 14 less than or negative 3 14 overflow exception 3 14 enable 3 15 registers 3 12 result class descriptor 3 14 result flags 3 14 rounding control 3 15 status and control register 3 12 underflow excepti...

Page 955: ...rrupt 3 50 implementation specific debug interrupt 3 51 implementation specific instruction TLB error interrupt 3 49 IMUL IDIV 3 5 Information processing time IPT 16 9 Initial sample time 13 12 Input sample time IST 13 28 13 47 Instruction pipeline 3 36 sequencer 3 3 set summary 3 29 timing 3 36 Instruction fetch show cycle control 21 1 instruction storage interrupt 3 46 instructions cache control...

Page 956: ... mode select MSTR 14 17 master external arbitration phase 9 30 MCE 21 54 MCEE 21 55 MCPWM D 22 ME bit 3 21 Message buffer address map 16 22 code for RX TX buffers 16 5 deactivation 16 13 structure 16 3 format error FORMERR 16 31 Mid analog supply voltage 13 14 MISO 14 33 14 37 Mode fault flag MODF 14 21 14 26 select M 14 46 Mode Fault Flag MODF 14 41 Modes disabled 13 18 reserved 13 18 scan See Sc...

Page 957: ...ce interfaces illustration 9 29 port width 9 1 PORTQA 13 33 13 34 PORTQB 13 33 13 34 PORTQS 14 10 PowerPC standards PowerPC Operating Environment Architecture Book 3 branch processor 3 43 fixed point processor special purpose registers 3 43 fixed point processor 3 43 interrupts 3 44 optional facilities and instructions 3 53 storage control instructions 3 44 timer facilities 3 53 PowerPC Operating ...

Page 958: ...3 QASR 13 40 QASR0 13 41 QASR1 13 42 QCLK 13 21 13 24 frequency 13 25 QDDR 14 12 14 41 QILR 14 8 QOM D 6 QPAR 14 11 QPDR 14 10 14 41 QS 13 42 QSM pin function 14 10 QSPI 14 13 operating modes 14 26 operation 14 24 RAM 14 21 registers pin control registers 14 9 port QS data direction register DDRQS 14 9 data register PORTQS 14 10 QSPI control register 0 SPCR0 14 16 control register 1 SPCR1 14 18 co...

Page 959: ...Recoverable exception 3 22 3 26 Registers CMPA CMPD 21 45 CMPE CMPF 21 46 CMPG CMPH 21 46 COUNTA 21 52 COUNTB 21 53 DER 21 55 ECR 21 53 ICTRL 21 47 LCTRL1 21 49 LCTRL2 21 50 MI_RA 0 3 region attribute register 4 21 supervisor level 3 20 test RAMTST 18 4 user level 3 11 registers special purpose added registers 3 44 unsupported registers 3 43 special purpose 3 43 Remote frames 16 15 transmission re...

Page 960: ...UMCR 6 18 SIW0EN 21 48 SIW1EN 21 48 SIW2EN 21 48 SIW3EN 21 48 Slave Select SS 14 41 Slave select signal SS 14 37 14 38 SLW0EN 21 52 SLW1EN 21 52 snooping external bus activity 3 42 SO bit 3 18 SOF 16 9 Soft reset control field SOFT_RST 17 20 SOFT_RST 17 20 SOFTRST 16 11 Software trap enable selection 21 48 SPBR 14 17 SPCR0 14 16 SPCR1 14 18 SPCR2 14 18 SPCR3 14 19 SPE 14 18 14 41 Special purpose r...

Page 961: ...4 46 14 54 Time quanta clock 16 9 stamp 16 5 16 10 Time base 3 19 timebase 3 43 TIMER 16 29 Timer count register 1 prescaler control TCR1P 17 11 synchronize mode TSYNC 16 27 Timing instruction 3 36 TMS 22 3 TOR1 13 41 TOR2 13 41 TOUCAN address map 16 20 bit timing configuration 16 8 operation 16 9 external pins 16 2 initialization sequence 16 11 interrupts 16 19 message buffer address map 16 22 op...

Page 962: ...A 9 38 transfer error acknowledge TEA 9 39 transfer size TSIZ 9 37 transfer start TS 9 36 transfers alignment and packaging 9 28 transfers burst inhibited 9 16 transfers termination signals 9 39 Transmission complete TC flag 14 53 interrupt enable TCIE 14 54 Transmit receive status TX RX 16 31 bit error BITERR 16 31 complete bit TC 14 48 interrupt enable TCIE 14 46 data register empty TDRE flag 14...

Page 963: ... WAKEINT 16 17 16 32 WAKEMSK 16 17 Wakeup address mark WAKE 14 46 14 58 Wired OR mode for QSPI pins WOMQ 14 17 for SCI pins WOMS 14 46 14 53 WOMQ 14 17 WOMS 14 46 14 53 Wrap enable WREN 14 19 to WRTO 14 19 Wraparound mode 14 15 master 14 37 WREN 14 19 write cycle data bus contents 9 30 WRTO 14 19 X XE bit 3 15 XER 3 17 XX bit 3 14 Z ZE bit 3 15 ZX bit 3 14 Freescale Semiconductor I Freescale Semic...

Page 964: ...MPC555 MPC556 INDEX MOTOROLA USER S MANUAL Rev 15 October 2000 Index 14 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 965: ...Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 966: ...cur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintend...

Page 967: ...uthorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Freescale Semiconductor MPC555LFCZP40 MPC555LFMVR40 MPC555LFMZP40 MPC555LFCVR40 MPC555LFAVR40 MPC555LFAZP40 SA555CMESLK NXP SC511660MZP40 ...

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