MPC555
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MPC556
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
MOTOROLA
USER’S MANUAL
Rev. 15 October 2000
13-37
Table 13-12 QACR1 Bit Descriptions
Bit(s)
Name
Description
0
CIE1
Queue 1 completion interrupt enable. CIE1 enables completion interrupts for queue 1. The inter-
rupt request is generated when the conversion is complete for the last CCW in queue 1.
0 = Queue 1 completion interrupts disabled
1 = Generate an interrupt request after completing the last CCW in queue 1
1
PIE1
Queue 1 pause interrupt enable. PIE1 enables pause interrupts for queue 1. The interrupt re-
quest is generated when the conversion is complete for a CCW that has the pause bit set.
0 = Queue 1 pause interrupts disabled
1 = Generate an interrupt request after completing a CCW in queue 1 which has the pause bit set
2
SSE1
Queue 1 single-scan enable. SSE1 enables a single-scan of queue 1 after a trigger event occurs.
The SSE1 bit may be set to a one during the same write cycle that sets the MQ1 bits for the sin-
gle-scan queue operating mode. The single-scan enable bit can be written as a one or a zero,
but is always read as a zero.
The SSE1 bit allows a trigger event to initiate queue execution for any single-scan operation on
queue 1. The QADC64 clears SSE1 when the single-scan is complete.
3:7
MQ1
Queue 1 operating mode. The MQ1 field selects the queue operating mode for queue 1.
shows the different queue 1 operating modes.
8:15
—
Reserved
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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