MPC555
/
MPC556
CLOCKS AND POWER CONTROL
MOTOROLA
USER’S MANUAL
Rev. 15 October 2000
8-20
8.9 Basic Power Structure
8.9.1 Clock Unit Power Supply
KAPWR and VSS power the following clock unit modules: oscillator, PITRTCLK and
TMBCLK
generation logic, timebase, decrementer, RTC, PIT, system clock control
register (SCCR), low-power and reset-control register (PLPRCR), and reset status
register
(RSR). All other circuits are powered by the normal supply pins, VDDI, VDDL,
VDDH and VSS. The power supply for each block is listed in
The following are the relations between different power supplies:
• VDDL = VDDI = VDDSYN = VDDF = 3.3 V ±10%
• KAPWR
≥
VDDL – 0.2 V (during normal operation)
• VDDSRAM
≥
VDDL – 0.3 V (during normal operation)
• VDDSRAM
≥
1.4 V (during standby operation)
• VPP
≥
VDDL – 0.3 V, but VPP – VDDL < 4.0 volts
8.9.2 Chip Power Structure
The MPC555 / MPC556 provides a wide range of possibilities for power supply con-
nections.
illustrates the different power supply sources for each of the ba-
sic units on the chip.
8.9.2.1 VDDL
The I/O buffers and logic are fed by a 3.3-V power supply.
8.9.2.2 VDDI
VDDI powers the internal logic of the MPC555 / MPC556, nominally 3.3 V.
Table 8-7 Clock Unit Power Supply
Circuit
Power Supply
CLKOUT
SPLL (digital),
System low-power control
Internal logic
Clock drivers
VDDL/VDDI
SPLL (analog)
VDDSYN
Main oscillator
Reset machine
Limp mode mechanism
Register control
SCCR, PLLRCR and RSR
RTC, PIT, TB, and DEC
KAPWR
SRAM,
VDDSRAM detector,
VSRMCR
VDDSRAM
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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