MPC555
/
MPC556
DUAL-PORT TPU RAM (DPTRAM)
MOTOROLA
USER’S MANUAL
Rev. 15 October 2000
18-6
18.3.5 MISC Counter (MISCNT)
The MISCNT contains the address of the current MISC memory access. This registers
is read-only. Note that the naming of the A[31:0] bits represents little-endian bit encod-
ing.
Exiting TPU3 emulation mode or clearing the MISEN bit in the DPTMCR results in the
reset of this register.
18.4 Operation
The DPTRAM module has several modes of operation. The following sections de-
scribe DPTRAM operation in each of these modes.
18.4.1 Normal Operation
In normal operation, the DPTRAM is powered by V
DDL
and may be accessed via the
IMB3 by a bus master.
Read or write accesses of 8, 16, or 32 bits are supported. In normal operation, neither
TPU3 accesses the array, nor do they have any effect on the operation of the DP-
TRAM module.
18.4.2 Standby Operation
The DPTRAM array uses a separate power supply VDDSRAM to maintain the con-
tents of the DPTRAM array during a power-down phase.
When the RAM array is powered by the VDDSRAM pin of the MCU, access to the RAM
array is blocked. Data read from the RAM array during this condition cannot be guar-
anteed. Data written to the DPTRAM may be corrupted if switching occurs during a
write operation.
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MISRL —
Multiple Input Signature Register Low
0x30 0008
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LSB
15
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MISCNT —
MISC Counter
0x30 000A
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LSB
15
RESERVED
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RESET:
Last Memory Address
MISRH —
Multiple Input Signature Register High
0x30 0006
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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