MPC555
/
MPC556
DEVELOPMENT SUPPORT
MOTOROLA
USER’S MANUAL
Rev. 15 October 2000
21-17
Figure 21-3 Instruction Support General Structure
21.3.2.1 Load/Store Support
There are two load/store address comparators E, and F. Each compares the 32 ad-
dress bits and the cycle’s attributes (read/write). The two least-significant bits are
Table 21-6 Instruction Watchpoints Programming Options
Name
Description
Programming options
IWP0
First instruction watchpoint
Comparator A
Comparators (A&B)
IWP1
Second instruction watchpoint
Comparator B
Comparator (A | B)
IWP2
Third instruction watchpoint
Comparator C
Comparators (C&D)
IWP3
Fourth instruction watchpoint
Comparator D
Comparator (C | D)
Comparator A
eq
lt
Compare Type
Comparator B
eq
lt
Comparator C
eq
lt
Comparator D
eq
lt
Eve
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ts G
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nerat
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r
AND-OR
Logic
Control Bits
A
B
(A&B)
(A | B)
C
D
(C&D)
(C | D)
I-Watchpoint 0
I-Watchpoint 1
I-Breakpoint
I-Watchpoint 2
I-Watchpoint 3
Compare
Type
Logic
Compare
Type
Logic
Compare
Type
Logic
Compare
Type
Logic
F
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le
S
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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