MPC555
/
MPC556
MEMORY CONTROLLER
MOTOROLA
USER’S MANUAL
Rev. 15 October 2000
10-4
Figure 10-4 Bank Base Address and Match Structure
When a match is found on one of the memory banks, its attributes are selected for the
functional operation of the external memory access:
• Read-only or read/write operation
• Number of wait states for a single memory access, and for any beat in a burst
access
• Burst-inhibit indication. Internal burst requests are still possible during burst-inhib-
ited cycles; the memory controller emulates the burst cycles
• Port size of the external device
Note that if more than one region matches the internal address supplied, then the low-
est region is selected to provide the attributes and the chip select.
10.2.1 Associated Registers
Status bits for each memory bank are found in the memory control status register
(MSTAT). The MSTAT reports write-protect violations for all the banks.
Each of the four banks has a base register (BR) and an option register (OR). The BRx
and ORx registers contain the attributes specific to bank x. The base register contains
a valid bit (V) that indicates that the register information for that chip select is valid.
10.2.2 Port Size Configuration
The memory controller supports dynamic bus sizing. Defined 8-bit ports can be ac-
cessed as odd or even bytes. Defined 16-bit ports, when connected to data bus lines
zero to 15, can be accessed as odd bytes, even bytes, or even half-words. Defined 32-
bit ports can be accessed as odd bytes, even bytes, odd half-words, even half-words,
M
[0]
M
[1]
M
[2]
M
[3]
M
[4]
M
[5]
M
[6]
M
[7]
[16]
[15]
[1]
[4]
[3]
[2]
RB A
[0]
comp comp comp comp comp comp comp comp comp comp comp
M[0:16]
A[0:16]
Base Address
Address Mask
Match
RB A
RB A
RB A
RB A
RB A
RB A
M
[16]
O O O O O O O O O
O O O O
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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