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dc2326af

DEMO MANUAL DC2326A

Description

LTC2345 

16-/18-Bit, Octal 200ksps, SAR ADC 

Demonstration circuit 2326A shows the proper way to drive 

the 

LTC

®

2345

 ADC. The LTC2345 is a low noise, high speed, 

simultaneous sampling 16-/18-bit successive approximation 

register (SAR) ADC. The LTC2345 has a flexible SoftSpan

 

interface that allows conversion-by-conversion control of 

the input voltage span on a per-channel basis. An internal 

2.048V reference and 2

×

 buffer simplify basic operation 

while an external reference can be used to increase the 

input range and the SNR of the ADC.
The DC2326A demonstrates the DC and AC performance of 

the LTC2345 in conjunction with the DC590/DC2026 and 

DC890 data collection boards. Use the DC590/DC2026 to 

L

, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope, 

QuikEval and SoftSpan are trademarks of Linear Technology Corporation. All other trademarks 

are the property of their respective owners.

assembly options

boarD photo

demonstrate DC performance such as peak-to-peak noise 

and DC linearity. Use the DC890 if precise sampling rates 

are required or to demonstrate AC performance such as 

SNR, THD, SINAD and SFDR. The DC2326A is intended 

to  demonstrate  recommended  grounding,  component 

placement and selection, routing and bypassing for this 

ADC. A suggested driver circuit for the analog inputs is 

also presented.

Design files for this circuit board including the schematic, 

layout and BOM are available at

http://www.linear.com/demo/DC2326A

Figure 1. DC2326A Connection Diagram

Assembly 

Version

U1 Part Number

Max Conversion  

Rate

Number of 

Channels

Number of 

Bits

Max CLK IN  

Frequency

CLK IN/fs  

Ratio

DC2326A-A

LTC2345-18

200ksps

8

18

60MHz

300

DC2326A-B

LTC2345-16

200ksps

8

16

60MHz

300

–9V

V

IN2

0V to 4.096V

V

IN1

0V to 4.096V

CLK

100MHz MAX

2.5V

P-P

+9V

DC890

DC590 OR DC2026

GND

Summary of Contents for LTC2345

Page 1: ...l and SoftSpan are trademarks of Linear Technology Corporation All other trademarks are the property of their respective owners assembly options Board Photo demonstrate DC performance such as peak to peak noise and DC linearity Use the DC890 if precise sampling rates are required or to demonstrate AC performance such as SNR THD SINAD and SFDR The DC2326A is intended to demonstrate recommended grou...

Page 2: ...lp menu Updates can be downloaded from the Tools menu Check for updates periodically as new features may be added The PScope software should recognize the DC2326A and configure itself automatically Click the Collect button See Figure 3 to begin acquiring data The Collect button then changes to Pause which can be clicked to stop data acquisition dc590 dc2026 Quick Start Procedure IMPORTANT To avoid...

Page 3: ...it is recommended for lower sample rates to divide down a higher frequency clock to the desired sample rate The ratio of clock frequency to conversion rate is shown in the Assembly Options table If theclockinputistobedrivenwithlogic itisrecommended that the 49 9Ω termination resistor R4 be removed Driving R4 with discrete logic may result in slow rising edges TheseslowrisingedgesmaycompromisetheSN...

Page 4: ...Options button in the PScope tool bar shown in Figure 4 This will open the Configure Channels menu of Figure 5 In this menu it is possible to set the input signal range setting for each channel There is also a button to return PScope to the default DC2326A settings which are optimized for the default hardware settings of the DC2326A Thereareanumberofscenariosthatcanproducemislead ing results when ...

Page 5: ...of a symmetricallayoutaroundtheanaloginputswillminimize theeffectsofparasiticelements Shieldanaloginputtraces with ground to minimize coupling from other traces Keep traces as short as possible Component Selection When driving a low noise low distortion ADC such as the LTC2345 component selection is important so as to not degrade performance Resistors should have low values to minimize noise and d...

Page 6: ...6 dc2326af DEMO MANUAL DC2326A DC2326A Setup Figure 3 PScope Screen Shot Figure 4 PScope Tool Bar ...

Page 7: ...7 dc2326af DEMO MANUAL DC2326A DC2326A Setup Figure 5 PScope Configuration Menu ...

Page 8: ...8 dc2326af DEMO MANUAL DC2326A DC2326A Setup Figure 6 QuikEval Screen Shot Figure 7 QuikEval Configuration Menu ...

Page 9: ... logic levels The default setting is CMOS Only CMOS is currently supported Definitions P1 DC890 interface is used to communicate with the DC890 controller J1 CLK provides the master clock for the DC2326A when interfaced to the DC890 J2 FPGA PROGRAM is used to program the FPGA This is for factory use only JP4 EEPROM is for factory use only The default posi tion is WP JP5 JP12 AIN0 AIN7 can be used ...

Page 10: ...UDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE EXCEPT TO THE EXTENT OF THIS INDEMNITY NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES The user assumes all responsibility and liability for proper and safe handling of the goods Further the user releases LTC from all claims arising from the handling or use of the goo...

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