NXP Semiconductors LPC1751, User Manual, Page: 618 / 808

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UM10360_0 © NXP B.V. 2009. All rights reserved.
User manual Rev. 00.06 — 5 June 2009 618 of 808
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 User Guide
SDIV {Rd,} Rn, Rm
Signed Divide - Section 34–2.6.3
SEV
- Send Event - Section 34–2.10.9
SMLAL RdLo, RdHi, Rn, Rm
Signed Multiply with Accumulate (32 x 32 + 64),
64-bit result - Section 34–2.6.2
SMULL RdLo, RdHi, Rn, Rm
Signed Multiply (32 x 32), 64-bit result - Section 34–2.6.2
SSAT Rd, #n, Rm {,shift #s}
Signed Saturate Q Section 34–2.7.1
STM Rn{!}, reglist
Store Multiple registers, increment after - Section 34–2.4.6
STMDB, STMEA Rn{!}, reglist
Store Multiple registers, decrement before - Section 34–2.4.6
STMFD, STMIA Rn{!}, reglist
Store Multiple registers, increment after - Section 34–2.4.6
STR Rt, [Rn, #offset]
Store Register word - Section 34–2.4
STRB, STRBT Rt, [Rn, #offset]
Store Register byte - Section 34–2.4
STRD Rt, Rt2, [Rn, #offset]
Store Register two words - Section 34–2.4.2
STREX Rd, Rt, [Rn, #offset]
Store Register Exclusive - Section 34–2.4.8
STREXB Rd, Rt, [Rn]
Store Register Exclusive byte - Section 34–2.4.8
STREXH Rd, Rt, [Rn]
Store Register Exclusive halfword - Section 34–2.4.8
STRH, STRHT Rt, [Rn, #offset]
Store Register halfword - Section 34–2.4
STRT Rt, [Rn, #offset]
Store Register word - Section 34–2.4
SUB, SUBS {Rd,} Rn, Op2
Subtract N,Z,C,V Section 34–2.5.1
SUB, SUBW {Rd,} Rn, #imm12
Subtract N,Z,C,V Section 34–2.5.1
SVC #imm
Supervisor Call - Section 34–2.10.1
0
SXTB {Rd,} Rm {,ROR #n}
Sign extend a byte - Section 34–2.8.3
SXTH {Rd,} Rm {,ROR #n}
Sign extend a halfword - Section 34–2.8.3
TBB [Rn, Rm]
Table Branch Byte - Section 34–2.9.4
TBH [Rn, Rm, LSL #1]
Table Branch Halfword - Section 34–2.9.4
TEQ Rn, Op2
Test Equivalence N,Z,C Section 34–2.5.9
TST Rn, Op2
Test N,Z,C Section 34–2.5.9
UBFX Rd, Rn, #lsb, #width
Unsigned Bit Field Extract - Section 34–2.8.2
UDIV {Rd,} Rn, Rm
Unsigned Divide - Section 34–2.6.3
UMLAL RdLo, RdHi, Rn, Rm
Unsigned Multiply with Accumulate
(32 x 32 + 64), 64-bit result - Section 34–2.6.2
UMULL RdLo, RdHi, Rn, Rm
Unsigned Multiply (32 x 32), 64-bit result - Section 34–2.6.2
USAT Rd, #n, Rm {,shift #s}
Unsigned Saturate Q Section 34–2.7.1
UXTB {Rd,} Rm {,ROR #n}
Zero extend a byte - Section 34–2.8.3
UXTH {Rd,} Rm {,ROR #n}
Zero extend a halfword - Section 34–2.8.3
WFE
- Wait For Event - Section 34–2.10.1
1
WFI
- Wait For Interrupt - Section 34–2.10.1
2
Table 584. Cortex-M3 instructions
…continued
Mnemonic Operands Brief description Flags Page