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UM10360_0
© NXP B.V. 2009. All rights reserved.
User manual
Rev. 00.06 — 5 June 2009
153 of 808
NXP Semiconductors
UM10360
Chapter 10: LPC17xx Ethernet
been committed to memory, set the Interrupt bit in the descriptor Control field to 1. To have
the hardware add a CRC in the frame sequence control field of this Ethernet frame, set
the CRC bit in the descriptor. This should be done if the CRC has not already been added
by software. To enable automatic padding of small frames to the minimum required frame
size, set the Pad bit in the Control field of the descriptor to 1. In typical applications bits
CRC and Pad are both set to 1.
The device driver can set up interrupts using the IntEnable register to wait for a signal of
completion from the hardware or can periodically inspect (poll) the progress of
transmission. It can also add new frames at the end of the descriptor array, while
hardware consumes descriptors at the start of the array.
The device driver can stop the transmit process by resetting the TxEnable bit in the
Command register to 0. The transmission will not stop immediately; frames already being
transmitted will be transmitted completely and the status will be committed to memory
before deactivating the data path. The status of the transmit data path can be monitored
by the device driver reading the TxStatus bit in the Status register.
As soon as the transmit data path is enabled and the corresponding TxConsumeIndex
and TxProduceIndex are not equal i.e. the hardware still needs to process frames from
the descriptor array, the TxStatus bit in the Status register will return to 1 (active).
Tx DMA manager reads the Tx descriptor array
When the TxEnable bit is set, the Tx DMA manager reads the descriptors from memory at
the address determined by TxDescriptor and TxConsumeIndex. The number of
descriptors requested is determined by the total number of descriptors owned by the
hardware: TxProduceIndex - TxConsumeIndex. Block transferring descriptors minimizes
memory loading. Read data returned from memory is buffered and consumed as needed.
Tx DMA manager transmits data
After reading the descriptor the transmit DMA engine reads the associated frame data
from memory and transmits the frame. After transfer completion, the Tx DMA manager
writes status information back to the StatusInfo and StatusHashCRC words of the status
field. The value of the TxConsumeIndex is only updated after status information has been
committed to memory, which is checked by an internal tag protocol in the memory
interface. The Tx DMA manager continues to transmit frames until the descriptor array is
empty. If the transmit descriptor array is empty the TxStatus bit in the Status register will
return to 0 (inactive). If the descriptor array is empty the Ethernet hardware will set the
TxFinishedInt bit of the IntStatus register. The transmit data path will still be enabled.
The Tx DMA manager inspects the Last bit of the descriptor Control field when loading the
descriptor. If the Last bit is 0, this indicates that the frame consists of multiple fragments.
The Tx DMA manager gathers all the fragments from the host memory, visiting a string of
frame descriptors, and sends them out as one Ethernet frame on the Ethernet connection.
When the Tx DMA manager finds a descriptor with the Last bit in the Control field set to 1,
this indicates the last fragment of the frame and thus the end of the frame is found.