NXP Semiconductors LPC1751, User Manual, Page: 29 / 808

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UM10360_0 © NXP B.V. 2009. All rights reserved.
User manual Rev. 00.06 — 5 June 2009 29 of 808
NXP Semiconductors
UM10360
Chapter 4: LPC17xx Clocking and power control
•
The IRC oscillator should not be used (via PLL0) as the clock source for the USB
subsystem.
•
The IRC oscillator should not be used (via PLL0) as the clock source for the CAN
controllers if the CAN baud rate is higher than 100 kbit/s.
4.1 Clock Source Select register (CLKSRCSEL - 0x400F C10C)
The CLKSRCSEL register contains the bits that select the clock source for PLL0.
5. PLL0 (Phase Locked Loop 0)
PLL0 accepts an input clock frequency in the range of 32 kHz to 50 MHz. The clock
source is selected in the CLKSRCSEL register (see
Section 4–4 ). The input frequency is
multiplied up to a high frequency, then divided down to provide the actual clock used by
the CPU, peripherals, and optionally the USB subsystem. Note that the USB subsystem
has its own dedicated PLL (see
Section 4–6 ). PLL0 can produce a clock up to the
maximum allowed for the CPU, which is 100 MHz.
5.1 PLL0 operation
The PLL input, in the range of 32 kHZ to 50 MHz, may initially be divided down by a value
"N", which may be in the range of 1 to 256. This input division provides a greater number
of possibilities in providing a wide range of output frequencies from the same input
frequency.
Following the PLL input divider is the PLL multiplier. This can multiply the input divider
output through the use of a Current Controlled Oscillator (CCO) by a value "M", in the
range of 6 through 512, plus additional values listed in
Table 4–21 . The resulting
frequency must be in the range of 275 MHz to 550 MHz. The multiplier works by dividing
the CCO output by the value of M, then using a phase-frequency detector to compare the
divided CCO output to the multiplier input. The error value is used to adjust the CCO
frequency.
Table 17. Clock Source Select register (CLKSRCSEL - address 0x400F C10C) bit
description
Bit Symbol Value Description Reset
value
1:0 CLKSRC Selects the clock source for PLL0 as follows: 0
00 Selects the Internal RC oscillator as the PLL0 clock source
(default).
01 Selects the main oscillator as the PLL0 clock source.
10 Selects the RTC oscillator as the PLL0 clock source.
11 Reserved, do not use this setting.
Warning: Improper setting of this value, or an incorrect sequence of
changing this value may result in incorrect operation of the device.
7:2 - 0 Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined. NA